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Fix disassembly of XCHG
[nasm/autotest.git] / assemble.c
bloba56887ec70f3d3f49f47fff709c4f54495b728d0
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the licence given in the file "Licence"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into next opcode byte if operand 0..3
37 * is a signed byte rather than a word.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into next opcode byte if operand 0..3
40 * is a signed byte rather than a dword.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
43 * operand 0..3.
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
46 * operand 0..3.
47 * \170 - encodes the literal byte 0. (Some compilers don't take
48 * kindly to a zero byte in the _middle_ of a compile time
49 * string constant, so I had to put this hack in.)
50 * \171 - placement of DREX suffix in the absence of an EA
51 * \2ab - a ModRM, calculated on EA in operand a, with the spare
52 * field equal to digit b.
53 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
54 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
55 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
56 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
57 * \314 - (disassembler only) invalid with REX.B
58 * \315 - (disassembler only) invalid with REX.X
59 * \316 - (disassembler only) invalid with REX.R
60 * \317 - (disassembler only) invalid with REX.W
61 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
62 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
63 * \322 - indicates that this instruction is only valid when the
64 * operand size is the default (instruction to disassembler,
65 * generates no code in the assembler)
66 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
67 * \324 - indicates 64-bit operand size requiring REX prefix.
68 * \330 - a literal byte follows in the code stream, to be added
69 * to the condition code value of the instruction.
70 * \331 - instruction not valid with REP prefix. Hint for
71 * disassembler only; for SSE instructions.
72 * \332 - REP prefix (0xF2 byte) used as opcode extension.
73 * \333 - REP prefix (0xF3 byte) used as opcode extension.
74 * \334 - LOCK prefix used instead of REX.R
75 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
76 * \340 - reserve <operand 0> bytes of uninitialized storage.
77 * Operand 0 had better be a segmentless constant.
78 * \364 - operand-size prefix (0x66) not permitted
79 * \365 - address-size prefix (0x67) not permitted
80 * \366 - operand-size prefix (0x66) used as opcode extension
81 * \367 - address-size prefix (0x67) used as opcode extension
82 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
83 * 370 is used for Jcc, 371 is used for JMP.
84 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
85 * used for conditional jump over longer jump
86 */
87
88 #include "compiler.h"
89
90 #include <stdio.h>
91 #include <string.h>
92 #include <inttypes.h>
93
94 #include "nasm.h"
95 #include "nasmlib.h"
96 #include "assemble.h"
97 #include "insns.h"
98 #include "preproc.h"
99 #include "regflags.c"
100 #include "regvals.c"
101
102 typedef struct {
103 int sib_present; /* is a SIB byte necessary? */
104 int bytes; /* # of bytes of offset needed */
105 int size; /* lazy - this is sib+bytes+1 */
106 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
107 } ea;
108
109 static uint32_t cpu; /* cpu level received from nasm.c */
110 static efunc errfunc;
111 static struct ofmt *outfmt;
112 static ListGen *list;
113
114 static int64_t calcsize(int32_t, int64_t, int, insn *, const char *);
115 static void gencode(int32_t, int64_t, int, insn *, const char *, int64_t);
116 static int matches(const struct itemplate *, insn *, int bits);
117 static int32_t regflag(const operand *);
118 static int32_t regval(const operand *);
119 static int rexflags(int, int32_t, int);
120 static int op_rexflags(const operand *, int);
121 static ea *process_ea(operand *, ea *, int, int, int, int32_t, int);
122 static void add_asp(insn *, int);
123
124 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
125 {
126 return ins->prefixes[pos] == prefix;
127 }
128
129 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
130 {
131 if (ins->prefixes[pos])
132 errfunc(ERR_NONFATAL, "invalid %s prefix",
133 prefix_name(ins->prefixes[pos]));
134 }
135
136 static const char *size_name(int size)
137 {
138 switch (size) {
139 case 1:
140 return "byte";
141 case 2:
142 return "word";
143 case 4:
144 return "dword";
145 case 8:
146 return "qword";
147 case 10:
148 return "tword";
149 case 16:
150 return "oword";
151 default:
152 return "???";
153 }
154 }
155
156 static void warn_overflow(int size, int64_t data)
157 {
158 if (size < 8) {
159 int64_t lim = ((int64_t)1 << (size*8))-1;
160
161 if (data < ~lim || data > lim)
162 errfunc(ERR_WARNING, "%s data exceeds bounds", size_name(size));
163 }
164 }
165 /*
166 * This routine wrappers the real output format's output routine,
167 * in order to pass a copy of the data off to the listing file
168 * generator at the same time.
169 */
170 static void out(int64_t offset, int32_t segto, const void *data,
171 enum out_type type, uint64_t size,
172 int32_t segment, int32_t wrt)
173 {
174 static int32_t lineno = 0; /* static!!! */
175 static char *lnfname = NULL;
176 uint8_t p[8];
177
178 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
179 /*
180 * This is a non-relocated address, and we're going to
181 * convert it into RAWDATA format.
182 */
183 uint8_t *q = p;
184
185 switch (size) {
186 case 2:
187 WRITESHORT(q, *(int32_t *)data);
188 break;
189 case 4:
190 WRITELONG(q, *(int32_t *)data);
191 break;
192 case 8:
193 WRITEDLONG(q, *(int64_t *)data);
194 break;
195 }
196 data = p;
197 type = OUT_RAWDATA;
198 }
199
200 list->output(offset, data, type, size);
201
202 /*
203 * this call to src_get determines when we call the
204 * debug-format-specific "linenum" function
205 * it updates lineno and lnfname to the current values
206 * returning 0 if "same as last time", -2 if lnfname
207 * changed, and the amount by which lineno changed,
208 * if it did. thus, these variables must be static
209 */
210
211 if (src_get(&lineno, &lnfname)) {
212 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
213 }
214
215 outfmt->output(segto, data, type, size, segment, wrt);
216 }
217
218 static int jmp_match(int32_t segment, int64_t offset, int bits,
219 insn * ins, const char *code)
220 {
221 int64_t isize;
222 uint8_t c = code[0];
223
224 if (c != 0370 && c != 0371)
225 return 0;
226 if (ins->oprs[0].opflags & OPFLAG_FORWARD) {
227 if ((optimizing < 0 || (ins->oprs[0].type & STRICT))
228 && c == 0370)
229 return 1;
230 else
231 return (pass0 == 0); /* match a forward reference */
232 }
233 isize = calcsize(segment, offset, bits, ins, code);
234 if (ins->oprs[0].segment != segment)
235 return 0;
236 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
237 if (isize >= -128L && isize <= 127L)
238 return 1; /* it is byte size */
239
240 return 0;
241 }
242
243 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
244 insn * instruction, struct ofmt *output, efunc error,
245 ListGen * listgen)
246 {
247 const struct itemplate *temp;
248 int j;
249 int size_prob;
250 int64_t insn_end;
251 int32_t itimes;
252 int64_t start = offset;
253 int64_t wsize = 0; /* size for DB etc. */
254
255 errfunc = error; /* to pass to other functions */
256 cpu = cp;
257 outfmt = output; /* likewise */
258 list = listgen; /* and again */
259
260 switch (instruction->opcode) {
261 case -1:
262 return 0;
263 case I_DB:
264 wsize = 1;
265 break;
266 case I_DW:
267 wsize = 2;
268 break;
269 case I_DD:
270 wsize = 4;
271 break;
272 case I_DQ:
273 wsize = 8;
274 break;
275 case I_DT:
276 wsize = 10;
277 break;
278 case I_DO:
279 wsize = 16;
280 break;
281 default:
282 break;
283 }
284
285 if (wsize) {
286 extop *e;
287 int32_t t = instruction->times;
288 if (t < 0)
289 errfunc(ERR_PANIC,
290 "instruction->times < 0 (%ld) in assemble()", t);
291
292 while (t--) { /* repeat TIMES times */
293 for (e = instruction->eops; e; e = e->next) {
294 if (e->type == EOT_DB_NUMBER) {
295 if (wsize == 1) {
296 if (e->segment != NO_SEG)
297 errfunc(ERR_NONFATAL,
298 "one-byte relocation attempted");
299 else {
300 uint8_t out_byte = e->offset;
301 out(offset, segment, &out_byte,
302 OUT_RAWDATA, 1, NO_SEG, NO_SEG);
303 }
304 } else if (wsize > 8) {
305 errfunc(ERR_NONFATAL, "integer supplied to a DT or DO"
306 " instruction");
307 } else
308 out(offset, segment, &e->offset,
309 OUT_ADDRESS, wsize, e->segment, e->wrt);
310 offset += wsize;
311 } else if (e->type == EOT_DB_STRING) {
312 int align;
313
314 out(offset, segment, e->stringval,
315 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
316 align = e->stringlen % wsize;
317
318 if (align) {
319 align = wsize - align;
320 out(offset, segment, "\0\0\0\0\0\0\0\0",
321 OUT_RAWDATA, align, NO_SEG, NO_SEG);
322 }
323 offset += e->stringlen + align;
324 }
325 }
326 if (t > 0 && t == instruction->times - 1) {
327 /*
328 * Dummy call to list->output to give the offset to the
329 * listing module.
330 */
331 list->output(offset, NULL, OUT_RAWDATA, 0);
332 list->uplevel(LIST_TIMES);
333 }
334 }
335 if (instruction->times > 1)
336 list->downlevel(LIST_TIMES);
337 return offset - start;
338 }
339
340 if (instruction->opcode == I_INCBIN) {
341 static char fname[FILENAME_MAX];
342 FILE *fp;
343 int32_t len;
344 char *prefix = "", *combine;
345 char **pPrevPath = NULL;
346
347 len = FILENAME_MAX - 1;
348 if (len > instruction->eops->stringlen)
349 len = instruction->eops->stringlen;
350 strncpy(fname, instruction->eops->stringval, len);
351 fname[len] = '\0';
352
353 while (1) { /* added by alexfru: 'incbin' uses include paths */
354 combine = nasm_malloc(strlen(prefix) + len + 1);
355 strcpy(combine, prefix);
356 strcat(combine, fname);
357
358 if ((fp = fopen(combine, "rb")) != NULL) {
359 nasm_free(combine);
360 break;
361 }
362
363 nasm_free(combine);
364 pPrevPath = pp_get_include_path_ptr(pPrevPath);
365 if (pPrevPath == NULL)
366 break;
367 prefix = *pPrevPath;
368 }
369
370 if (fp == NULL)
371 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
372 fname);
373 else if (fseek(fp, 0L, SEEK_END) < 0)
374 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
375 fname);
376 else {
377 static char buf[2048];
378 int32_t t = instruction->times;
379 int32_t base = 0;
380
381 len = ftell(fp);
382 if (instruction->eops->next) {
383 base = instruction->eops->next->offset;
384 len -= base;
385 if (instruction->eops->next->next &&
386 len > instruction->eops->next->next->offset)
387 len = instruction->eops->next->next->offset;
388 }
389 /*
390 * Dummy call to list->output to give the offset to the
391 * listing module.
392 */
393 list->output(offset, NULL, OUT_RAWDATA, 0);
394 list->uplevel(LIST_INCBIN);
395 while (t--) {
396 int32_t l;
397
398 fseek(fp, base, SEEK_SET);
399 l = len;
400 while (l > 0) {
401 int32_t m =
402 fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l),
403 fp);
404 if (!m) {
405 /*
406 * This shouldn't happen unless the file
407 * actually changes while we are reading
408 * it.
409 */
410 error(ERR_NONFATAL,
411 "`incbin': unexpected EOF while"
412 " reading file `%s'", fname);
413 t = 0; /* Try to exit cleanly */
414 break;
415 }
416 out(offset, segment, buf, OUT_RAWDATA, m,
417 NO_SEG, NO_SEG);
418 l -= m;
419 }
420 }
421 list->downlevel(LIST_INCBIN);
422 if (instruction->times > 1) {
423 /*
424 * Dummy call to list->output to give the offset to the
425 * listing module.
426 */
427 list->output(offset, NULL, OUT_RAWDATA, 0);
428 list->uplevel(LIST_TIMES);
429 list->downlevel(LIST_TIMES);
430 }
431 fclose(fp);
432 return instruction->times * len;
433 }
434 return 0; /* if we're here, there's an error */
435 }
436
437 /* Check to see if we need an address-size prefix */
438 add_asp(instruction, bits);
439
440 size_prob = false;
441
442 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
443 int m = matches(temp, instruction, bits);
444
445 if (m == 99)
446 m += jmp_match(segment, offset, bits, instruction, temp->code);
447
448 if (m == 100) { /* matches! */
449 const char *codes = temp->code;
450 int64_t insn_size = calcsize(segment, offset, bits,
451 instruction, codes);
452 itimes = instruction->times;
453 if (insn_size < 0) /* shouldn't be, on pass two */
454 error(ERR_PANIC, "errors made it through from pass one");
455 else
456 while (itimes--) {
457 for (j = 0; j < MAXPREFIX; j++) {
458 uint8_t c = 0;
459 switch (instruction->prefixes[j]) {
460 case P_LOCK:
461 c = 0xF0;
462 break;
463 case P_REPNE:
464 case P_REPNZ:
465 c = 0xF2;
466 break;
467 case P_REPE:
468 case P_REPZ:
469 case P_REP:
470 c = 0xF3;
471 break;
472 case R_CS:
473 if (bits == 64) {
474 error(ERR_WARNING,
475 "cs segment base generated, but will be ignored in 64-bit mode");
476 }
477 c = 0x2E;
478 break;
479 case R_DS:
480 if (bits == 64) {
481 error(ERR_WARNING,
482 "ds segment base generated, but will be ignored in 64-bit mode");
483 }
484 c = 0x3E;
485 break;
486 case R_ES:
487 if (bits == 64) {
488 error(ERR_WARNING,
489 "es segment base generated, but will be ignored in 64-bit mode");
490 }
491 c = 0x26;
492 break;
493 case R_FS:
494 c = 0x64;
495 break;
496 case R_GS:
497 c = 0x65;
498 break;
499 case R_SS:
500 if (bits == 64) {
501 error(ERR_WARNING,
502 "ss segment base generated, but will be ignored in 64-bit mode");
503 }
504 c = 0x36;
505 break;
506 case R_SEGR6:
507 case R_SEGR7:
508 error(ERR_NONFATAL,
509 "segr6 and segr7 cannot be used as prefixes");
510 break;
511 case P_A16:
512 if (bits == 64) {
513 error(ERR_NONFATAL,
514 "16-bit addressing is not supported "
515 "in 64-bit mode");
516 } else if (bits != 16)
517 c = 0x67;
518 break;
519 case P_A32:
520 if (bits != 32)
521 c = 0x67;
522 break;
523 case P_A64:
524 if (bits != 64) {
525 error(ERR_NONFATAL,
526 "64-bit addressing is only supported "
527 "in 64-bit mode");
528 }
529 break;
530 case P_ASP:
531 c = 0x67;
532 break;
533 case P_O16:
534 if (bits != 16)
535 c = 0x66;
536 break;
537 case P_O32:
538 if (bits == 16)
539 c = 0x66;
540 break;
541 case P_O64:
542 /* REX.W */
543 break;
544 case P_OSP:
545 c = 0x66;
546 break;
547 case P_none:
548 break;
549 default:
550 error(ERR_PANIC, "invalid instruction prefix");
551 }
552 if (c != 0) {
553 out(offset, segment, &c, OUT_RAWDATA, 1,
554 NO_SEG, NO_SEG);
555 offset++;
556 }
557 }
558 insn_end = offset + insn_size;
559 gencode(segment, offset, bits, instruction, codes,
560 insn_end);
561 offset += insn_size;
562 if (itimes > 0 && itimes == instruction->times - 1) {
563 /*
564 * Dummy call to list->output to give the offset to the
565 * listing module.
566 */
567 list->output(offset, NULL, OUT_RAWDATA, 0);
568 list->uplevel(LIST_TIMES);
569 }
570 }
571 if (instruction->times > 1)
572 list->downlevel(LIST_TIMES);
573 return offset - start;
574 } else if (m > 0 && m > size_prob) {
575 size_prob = m;
576 }
577 // temp++;
578 }
579
580 if (temp->opcode == -1) { /* didn't match any instruction */
581 switch (size_prob) {
582 case 1:
583 error(ERR_NONFATAL, "operation size not specified");
584 break;
585 case 2:
586 error(ERR_NONFATAL, "mismatch in operand sizes");
587 break;
588 case 3:
589 error(ERR_NONFATAL, "no instruction for this cpu level");
590 break;
591 case 4:
592 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
593 break;
594 default:
595 error(ERR_NONFATAL,
596 "invalid combination of opcode and operands");
597 break;
598 }
599 }
600 return 0;
601 }
602
603 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
604 insn * instruction, efunc error)
605 {
606 const struct itemplate *temp;
607
608 errfunc = error; /* to pass to other functions */
609 cpu = cp;
610
611 if (instruction->opcode == -1)
612 return 0;
613
614 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
615 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
616 instruction->opcode == I_DT || instruction->opcode == I_DO) {
617 extop *e;
618 int32_t isize, osize, wsize = 0; /* placate gcc */
619
620 isize = 0;
621 switch (instruction->opcode) {
622 case I_DB:
623 wsize = 1;
624 break;
625 case I_DW:
626 wsize = 2;
627 break;
628 case I_DD:
629 wsize = 4;
630 break;
631 case I_DQ:
632 wsize = 8;
633 break;
634 case I_DT:
635 wsize = 10;
636 break;
637 case I_DO:
638 wsize = 16;
639 break;
640 default:
641 break;
642 }
643
644 for (e = instruction->eops; e; e = e->next) {
645 int32_t align;
646
647 osize = 0;
648 if (e->type == EOT_DB_NUMBER)
649 osize = 1;
650 else if (e->type == EOT_DB_STRING)
651 osize = e->stringlen;
652
653 align = (-osize) % wsize;
654 if (align < 0)
655 align += wsize;
656 isize += osize + align;
657 }
658 return isize * instruction->times;
659 }
660
661 if (instruction->opcode == I_INCBIN) {
662 char fname[FILENAME_MAX];
663 FILE *fp;
664 int32_t len;
665 char *prefix = "", *combine;
666 char **pPrevPath = NULL;
667
668 len = FILENAME_MAX - 1;
669 if (len > instruction->eops->stringlen)
670 len = instruction->eops->stringlen;
671 strncpy(fname, instruction->eops->stringval, len);
672 fname[len] = '\0';
673
674 /* added by alexfru: 'incbin' uses include paths */
675 while (1) {
676 combine = nasm_malloc(strlen(prefix) + len + 1);
677 strcpy(combine, prefix);
678 strcat(combine, fname);
679
680 if ((fp = fopen(combine, "rb")) != NULL) {
681 nasm_free(combine);
682 break;
683 }
684
685 nasm_free(combine);
686 pPrevPath = pp_get_include_path_ptr(pPrevPath);
687 if (pPrevPath == NULL)
688 break;
689 prefix = *pPrevPath;
690 }
691
692 if (fp == NULL)
693 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
694 fname);
695 else if (fseek(fp, 0L, SEEK_END) < 0)
696 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
697 fname);
698 else {
699 len = ftell(fp);
700 fclose(fp);
701 if (instruction->eops->next) {
702 len -= instruction->eops->next->offset;
703 if (instruction->eops->next->next &&
704 len > instruction->eops->next->next->offset) {
705 len = instruction->eops->next->next->offset;
706 }
707 }
708 return instruction->times * len;
709 }
710 return 0; /* if we're here, there's an error */
711 }
712
713 /* Check to see if we need an address-size prefix */
714 add_asp(instruction, bits);
715
716 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
717 int m = matches(temp, instruction, bits);
718 if (m == 99)
719 m += jmp_match(segment, offset, bits, instruction, temp->code);
720
721 if (m == 100) {
722 /* we've matched an instruction. */
723 int64_t isize;
724 const char *codes = temp->code;
725 int j;
726
727 isize = calcsize(segment, offset, bits, instruction, codes);
728 if (isize < 0)
729 return -1;
730 for (j = 0; j < MAXPREFIX; j++) {
731 switch (instruction->prefixes[j]) {
732 case P_A16:
733 if (bits != 16)
734 isize++;
735 break;
736 case P_A32:
737 if (bits != 32)
738 isize++;
739 break;
740 case P_O16:
741 if (bits != 16)
742 isize++;
743 break;
744 case P_O32:
745 if (bits == 16)
746 isize++;
747 break;
748 case P_A64:
749 case P_O64:
750 case P_none:
751 break;
752 default:
753 isize++;
754 break;
755 }
756 }
757 return isize * instruction->times;
758 }
759 }
760 return -1; /* didn't match any instruction */
761 }
762
763 /* check that opn[op] is a signed byte of size 16 or 32,
764 and return the signed value*/
765 static int is_sbyte(insn * ins, int op, int size)
766 {
767 int32_t v;
768 int ret;
769
770 ret = !(ins->forw_ref && ins->oprs[op].opflags) && /* dead in the water on forward reference or External */
771 optimizing >= 0 &&
772 !(ins->oprs[op].type & STRICT) &&
773 ins->oprs[op].wrt == NO_SEG && ins->oprs[op].segment == NO_SEG;
774
775 v = ins->oprs[op].offset;
776 if (size == 16)
777 v = (int16_t)v; /* sign extend if 16 bits */
778
779 return ret && v >= -128L && v <= 127L;
780 }
781
782 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
783 insn * ins, const char *codes)
784 {
785 int64_t length = 0;
786 uint8_t c;
787 int rex_mask = ~0;
788 struct operand *opx;
789
790 ins->rex = 0; /* Ensure REX is reset */
791
792 if (ins->prefixes[PPS_OSIZE] == P_O64)
793 ins->rex |= REX_W;
794
795 (void)segment; /* Don't warn that this parameter is unused */
796 (void)offset; /* Don't warn that this parameter is unused */
797
798 while (*codes) {
799 c = *codes++;
800 opx = &ins->oprs[c & 3];
801 switch (c) {
802 case 01:
803 case 02:
804 case 03:
805 codes += c, length += c;
806 break;
807 case 04:
808 case 05:
809 case 06:
810 case 07:
811 length++;
812 break;
813 case 010:
814 case 011:
815 case 012:
816 case 013:
817 ins->rex |=
818 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
819 codes++, length++;
820 break;
821 case 014:
822 case 015:
823 case 016:
824 case 017:
825 length++;
826 break;
827 case 020:
828 case 021:
829 case 022:
830 case 023:
831 length++;
832 break;
833 case 024:
834 case 025:
835 case 026:
836 case 027:
837 length++;
838 break;
839 case 030:
840 case 031:
841 case 032:
842 case 033:
843 length += 2;
844 break;
845 case 034:
846 case 035:
847 case 036:
848 case 037:
849 if (opx->type & (BITS16 | BITS32 | BITS64))
850 length += (opx->type & BITS16) ? 2 : 4;
851 else
852 length += (bits == 16) ? 2 : 4;
853 break;
854 case 040:
855 case 041:
856 case 042:
857 case 043:
858 length += 4;
859 break;
860 case 044:
861 case 045:
862 case 046:
863 case 047:
864 length += ins->addr_size >> 3;
865 break;
866 case 050:
867 case 051:
868 case 052:
869 case 053:
870 length++;
871 break;
872 case 054:
873 case 055:
874 case 056:
875 case 057:
876 length += 8; /* MOV reg64/imm */
877 break;
878 case 060:
879 case 061:
880 case 062:
881 case 063:
882 length += 2;
883 break;
884 case 064:
885 case 065:
886 case 066:
887 case 067:
888 if (opx->type & (BITS16 | BITS32 | BITS64))
889 length += (opx->type & BITS16) ? 2 : 4;
890 else
891 length += (bits == 16) ? 2 : 4;
892 break;
893 case 070:
894 case 071:
895 case 072:
896 case 073:
897 length += 4;
898 break;
899 case 074:
900 case 075:
901 case 076:
902 case 077:
903 length += 2;
904 break;
905 case 0140:
906 case 0141:
907 case 0142:
908 case 0143:
909 length += is_sbyte(ins, c & 3, 16) ? 1 : 2;
910 break;
911 case 0144:
912 case 0145:
913 case 0146:
914 case 0147:
915 codes += 2;
916 length++;
917 break;
918 case 0150:
919 case 0151:
920 case 0152:
921 case 0153:
922 length += is_sbyte(ins, c & 3, 32) ? 1 : 4;
923 break;
924 case 0154:
925 case 0155:
926 case 0156:
927 case 0157:
928 codes += 2;
929 length++;
930 break;
931 case 0160:
932 case 0161:
933 case 0162:
934 case 0163:
935 length++;
936 ins->rex |= REX_D;
937 ins->drexdst = regval(&ins->oprs[c & 3]);
938 break;
939 case 0164:
940 case 0165:
941 case 0166:
942 case 0167:
943 length++;
944 ins->rex |= REX_D|REX_OC;
945 ins->drexdst = regval(&ins->oprs[c & 3]);
946 break;
947 case 0170:
948 length++;
949 break;
950 case 0171:
951 break;
952 case 0300:
953 case 0301:
954 case 0302:
955 case 0303:
956 break;
957 case 0310:
958 if (bits == 64)
959 return -1;
960 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
961 break;
962 case 0311:
963 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
964 break;
965 case 0312:
966 break;
967 case 0313:
968 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
969 has_prefix(ins, PPS_ASIZE, P_A32))
970 return -1;
971 break;
972 case 0314:
973 case 0315:
974 case 0316:
975 case 0317:
976 break;
977 case 0320:
978 length += (bits != 16);
979 break;
980 case 0321:
981 length += (bits == 16);
982 break;
983 case 0322:
984 break;
985 case 0323:
986 rex_mask &= ~REX_W;
987 break;
988 case 0324:
989 ins->rex |= REX_W;
990 break;
991 case 0330:
992 codes++, length++;
993 break;
994 case 0331:
995 break;
996 case 0332:
997 case 0333:
998 length++;
999 break;
1000 case 0334:
1001 ins->rex |= REX_L;
1002 break;
1003 case 0335:
1004 break;
1005 case 0340:
1006 case 0341:
1007 case 0342:
1008 if (ins->oprs[0].segment != NO_SEG)
1009 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1010 " quantity of BSS space");
1011 else
1012 length += ins->oprs[0].offset << (c & 3);
1013 break;
1014 case 0364:
1015 case 0365:
1016 break;
1017 case 0366:
1018 case 0367:
1019 length++;
1020 break;
1021 case 0370:
1022 case 0371:
1023 case 0372:
1024 break;
1025 case 0373:
1026 length++;
1027 break;
1028 default: /* can't do it by 'case' statements */
1029 if (c >= 0100 && c <= 0277) { /* it's an EA */
1030 ea ea_data;
1031 int rfield;
1032 int32_t rflags;
1033 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1034
1035 if (c <= 0177) {
1036 /* pick rfield from operand b */
1037 rflags = regflag(&ins->oprs[c & 7]);
1038 rfield = regvals[ins->oprs[c & 7].basereg];
1039 } else {
1040 rflags = 0;
1041 rfield = c & 7;
1042 }
1043
1044 if (!process_ea
1045 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1046 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1047 errfunc(ERR_NONFATAL, "invalid effective address");
1048 return -1;
1049 } else {
1050 ins->rex |= ea_data.rex;
1051 length += ea_data.size;
1052 }
1053 } else {
1054 errfunc(ERR_PANIC, "internal instruction table corrupt"
1055 ": instruction code 0x%02X given", c);
1056 }
1057 }
1058 }
1059
1060 ins->rex &= rex_mask;
1061
1062 if (ins->rex & REX_D) {
1063 if (ins->rex & REX_H) {
1064 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1065 return -1;
1066 }
1067 if (bits != 64 && ((ins->rex & (REX_W|REX_X|REX_B)) ||
1068 ins->drexdst > 7)) {
1069 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1070 return -1;
1071 }
1072 length++;
1073 } else if (ins->rex & REX_REAL) {
1074 if (ins->rex & REX_H) {
1075 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1076 return -1;
1077 } else if (bits == 64) {
1078 length++;
1079 } else if ((ins->rex & REX_L) &&
1080 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1081 cpu >= IF_X86_64) {
1082 /* LOCK-as-REX.R */
1083 assert_no_prefix(ins, PPS_LREP);
1084 length++;
1085 } else {
1086 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1087 return -1;
1088 }
1089 }
1090
1091 return length;
1092 }
1093
1094 #define EMIT_REX() \
1095 if (!(ins->rex & REX_D) && (ins->rex & REX_REAL) && (bits == 64)) { \
1096 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1097 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1098 ins->rex = 0; \
1099 offset += 1; \
1100 }
1101
1102 static void gencode(int32_t segment, int64_t offset, int bits,
1103 insn * ins, const char *codes, int64_t insn_end)
1104 {
1105 static char condval[] = { /* conditional opcodes */
1106 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1107 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1108 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1109 };
1110 uint8_t c;
1111 uint8_t bytes[4];
1112 int64_t size;
1113 int64_t data;
1114 struct operand *opx;
1115
1116 while (*codes) {
1117 c = *codes++;
1118 opx = &ins->oprs[c & 3];
1119 switch (c) {
1120 case 01:
1121 case 02:
1122 case 03:
1123 EMIT_REX();
1124 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1125 codes += c;
1126 offset += c;
1127 break;
1128
1129 case 04:
1130 case 06:
1131 switch (ins->oprs[0].basereg) {
1132 case R_CS:
1133 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1134 break;
1135 case R_DS:
1136 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1137 break;
1138 case R_ES:
1139 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1140 break;
1141 case R_SS:
1142 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1143 break;
1144 default:
1145 errfunc(ERR_PANIC,
1146 "bizarre 8086 segment register received");
1147 }
1148 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1149 offset++;
1150 break;
1151
1152 case 05:
1153 case 07:
1154 switch (ins->oprs[0].basereg) {
1155 case R_FS:
1156 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1157 break;
1158 case R_GS:
1159 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1160 break;
1161 default:
1162 errfunc(ERR_PANIC,
1163 "bizarre 386 segment register received");
1164 }
1165 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1166 offset++;
1167 break;
1168
1169 case 010:
1170 case 011:
1171 case 012:
1172 case 013:
1173 EMIT_REX();
1174 bytes[0] = *codes++ + ((regval(opx)) & 7);
1175 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1176 offset += 1;
1177 break;
1178
1179 case 014:
1180 case 015:
1181 case 016:
1182 case 017:
1183 if (opx->offset < -128 || opx->offset > 127) {
1184 errfunc(ERR_WARNING, "signed byte value exceeds bounds");
1185 }
1186
1187 if (opx->segment != NO_SEG) {
1188 data = opx->offset;
1189 out(offset, segment, &data, OUT_ADDRESS, 1,
1190 opx->segment, opx->wrt);
1191 } else {
1192 bytes[0] = opx->offset;
1193 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1194 NO_SEG);
1195 }
1196 offset += 1;
1197 break;
1198
1199 case 020:
1200 case 021:
1201 case 022:
1202 case 023:
1203 if (opx->offset < -256 || opx->offset > 255) {
1204 errfunc(ERR_WARNING, "byte value exceeds bounds");
1205 }
1206 if (opx->segment != NO_SEG) {
1207 data = opx->offset;
1208 out(offset, segment, &data, OUT_ADDRESS, 1,
1209 opx->segment, opx->wrt);
1210 } else {
1211 bytes[0] = opx->offset;
1212 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1213 NO_SEG);
1214 }
1215 offset += 1;
1216 break;
1217
1218 case 024:
1219 case 025:
1220 case 026:
1221 case 027:
1222 if (opx->offset < 0 || opx->offset > 255)
1223 errfunc(ERR_WARNING, "unsigned byte value exceeds bounds");
1224 if (opx->segment != NO_SEG) {
1225 data = opx->offset;
1226 out(offset, segment, &data, OUT_ADDRESS, 1,
1227 opx->segment, opx->wrt);
1228 } else {
1229 bytes[0] = opx->offset;
1230 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1231 NO_SEG);
1232 }
1233 offset += 1;
1234 break;
1235
1236 case 030:
1237 case 031:
1238 case 032:
1239 case 033:
1240 data = opx->offset;
1241 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1242 warn_overflow(2, data);
1243 out(offset, segment, &data, OUT_ADDRESS, 2,
1244 opx->segment, opx->wrt);
1245 offset += 2;
1246 break;
1247
1248 case 034:
1249 case 035:
1250 case 036:
1251 case 037:
1252 if (opx->type & (BITS16 | BITS32))
1253 size = (opx->type & BITS16) ? 2 : 4;
1254 else
1255 size = (bits == 16) ? 2 : 4;
1256 data = opx->offset;
1257 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1258 warn_overflow(size, data);
1259 out(offset, segment, &data, OUT_ADDRESS, size,
1260 opx->segment, opx->wrt);
1261 offset += size;
1262 break;
1263
1264 case 040:
1265 case 041:
1266 case 042:
1267 case 043:
1268 data = opx->offset;
1269 out(offset, segment, &data, OUT_ADDRESS, 4,
1270 opx->segment, opx->wrt);
1271 offset += 4;
1272 break;
1273
1274 case 044:
1275 case 045:
1276 case 046:
1277 case 047:
1278 data = opx->offset;
1279 size = ins->addr_size >> 3;
1280 if (opx->segment == NO_SEG &&
1281 opx->wrt == NO_SEG)
1282 warn_overflow(size, data);
1283 out(offset, segment, &data, OUT_ADDRESS, size,
1284 opx->segment, opx->wrt);
1285 offset += size;
1286 break;
1287
1288 case 050:
1289 case 051:
1290 case 052:
1291 case 053:
1292 if (opx->segment != segment)
1293 errfunc(ERR_NONFATAL,
1294 "short relative jump outside segment");
1295 data = opx->offset - insn_end;
1296 if (data > 127 || data < -128)
1297 errfunc(ERR_NONFATAL, "short jump is out of range");
1298 bytes[0] = data;
1299 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1300 offset += 1;
1301 break;
1302
1303 case 054:
1304 case 055:
1305 case 056:
1306 case 057:
1307 data = (int64_t)opx->offset;
1308 out(offset, segment, &data, OUT_ADDRESS, 8,
1309 opx->segment, opx->wrt);
1310 offset += 8;
1311 break;
1312
1313 case 060:
1314 case 061:
1315 case 062:
1316 case 063:
1317 if (opx->segment != segment) {
1318 data = opx->offset;
1319 out(offset, segment, &data,
1320 OUT_REL2ADR, insn_end - offset,
1321 opx->segment, opx->wrt);
1322 } else {
1323 data = opx->offset - insn_end;
1324 out(offset, segment, &data,
1325 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1326 }
1327 offset += 2;
1328 break;
1329
1330 case 064:
1331 case 065:
1332 case 066:
1333 case 067:
1334 if (opx->type & (BITS16 | BITS32 | BITS64))
1335 size = (opx->type & BITS16) ? 2 : 4;
1336 else
1337 size = (bits == 16) ? 2 : 4;
1338 if (opx->segment != segment) {
1339 data = opx->offset;
1340 out(offset, segment, &data,
1341 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1342 insn_end - offset, opx->segment, opx->wrt);
1343 } else {
1344 data = opx->offset - insn_end;
1345 out(offset, segment, &data,
1346 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1347 }
1348 offset += size;
1349 break;
1350
1351 case 070:
1352 case 071:
1353 case 072:
1354 case 073:
1355 if (opx->segment != segment) {
1356 data = opx->offset;
1357 out(offset, segment, &data,
1358 OUT_REL4ADR, insn_end - offset,
1359 opx->segment, opx->wrt);
1360 } else {
1361 data = opx->offset - insn_end;
1362 out(offset, segment, &data,
1363 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1364 }
1365 offset += 4;
1366 break;
1367
1368 case 074:
1369 case 075:
1370 case 076:
1371 case 077:
1372 if (opx->segment == NO_SEG)
1373 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1374 " relocatable");
1375 data = 0L;
1376 out(offset, segment, &data, OUT_ADDRESS, 2,
1377 outfmt->segbase(1 + opx->segment),
1378 opx->wrt);
1379 offset += 2;
1380 break;
1381
1382 case 0140:
1383 case 0141:
1384 case 0142:
1385 case 0143:
1386 data = opx->offset;
1387 if (is_sbyte(ins, c & 3, 16)) {
1388 bytes[0] = data;
1389 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1390 NO_SEG);
1391 offset++;
1392 } else {
1393 if (opx->segment == NO_SEG &&
1394 opx->wrt == NO_SEG)
1395 warn_overflow(2, data);
1396 out(offset, segment, &data, OUT_ADDRESS, 2,
1397 opx->segment, opx->wrt);
1398 offset += 2;
1399 }
1400 break;
1401
1402 case 0144:
1403 case 0145:
1404 case 0146:
1405 case 0147:
1406 EMIT_REX();
1407 codes++;
1408 bytes[0] = *codes++;
1409 if (is_sbyte(ins, c & 3, 16))
1410 bytes[0] |= 2; /* s-bit */
1411 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1412 offset++;
1413 break;
1414
1415 case 0150:
1416 case 0151:
1417 case 0152:
1418 case 0153:
1419 data = opx->offset;
1420 if (is_sbyte(ins, c & 3, 32)) {
1421 bytes[0] = data;
1422 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1423 NO_SEG);
1424 offset++;
1425 } else {
1426 out(offset, segment, &data, OUT_ADDRESS, 4,
1427 opx->segment, opx->wrt);
1428 offset += 4;
1429 }
1430 break;
1431
1432 case 0154:
1433 case 0155:
1434 case 0156:
1435 case 0157:
1436 EMIT_REX();
1437 codes++;
1438 bytes[0] = *codes++;
1439 if (is_sbyte(ins, c & 3, 32))
1440 bytes[0] |= 2; /* s-bit */
1441 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1442 offset++;
1443 break;
1444
1445 case 0160:
1446 case 0161:
1447 case 0162:
1448 case 0163:
1449 case 0164:
1450 case 0165:
1451 case 0166:
1452 case 0167:
1453 break;
1454
1455 case 0170:
1456 EMIT_REX();
1457 bytes[0] = 0;
1458 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1459 offset += 1;
1460 break;
1461
1462 case 0171:
1463 bytes[0] =
1464 (ins->drexdst << 4) |
1465 (ins->rex & REX_OC ? 0x08 : 0) |
1466 (ins->rex & (REX_R|REX_X|REX_B));
1467 ins->rex = 0;
1468 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1469 offset++;
1470 break;
1471
1472 case 0300:
1473 case 0301:
1474 case 0302:
1475 case 0303:
1476 break;
1477
1478 case 0310:
1479 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1480 *bytes = 0x67;
1481 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1482 offset += 1;
1483 } else
1484 offset += 0;
1485 break;
1486
1487 case 0311:
1488 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1489 *bytes = 0x67;
1490 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1491 offset += 1;
1492 } else
1493 offset += 0;
1494 break;
1495
1496 case 0312:
1497 break;
1498
1499 case 0313:
1500 ins->rex = 0;
1501 break;
1502
1503 case 0314:
1504 case 0315:
1505 case 0316:
1506 case 0317:
1507 break;
1508
1509 case 0320:
1510 if (bits != 16) {
1511 *bytes = 0x66;
1512 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1513 offset += 1;
1514 } else
1515 offset += 0;
1516 break;
1517
1518 case 0321:
1519 if (bits == 16) {
1520 *bytes = 0x66;
1521 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1522 offset += 1;
1523 } else
1524 offset += 0;
1525 break;
1526
1527 case 0322:
1528 case 0323:
1529 break;
1530
1531 case 0324:
1532 ins->rex |= REX_W;
1533 break;
1534
1535 case 0330:
1536 *bytes = *codes++ ^ condval[ins->condition];
1537 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1538 offset += 1;
1539 break;
1540
1541 case 0331:
1542 break;
1543
1544 case 0332:
1545 case 0333:
1546 *bytes = c - 0332 + 0xF2;
1547 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1548 offset += 1;
1549 break;
1550
1551 case 0334:
1552 if (ins->rex & REX_R) {
1553 *bytes = 0xF0;
1554 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1555 offset += 1;
1556 }
1557 ins->rex &= ~(REX_L|REX_R);
1558 break;
1559
1560 case 0335:
1561 break;
1562
1563 case 0340:
1564 case 0341:
1565 case 0342:
1566 if (ins->oprs[0].segment != NO_SEG)
1567 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1568 else {
1569 int64_t size = ins->oprs[0].offset << (c & 3);
1570 if (size > 0)
1571 out(offset, segment, NULL,
1572 OUT_RESERVE, size, NO_SEG, NO_SEG);
1573 offset += size;
1574 }
1575 break;
1576
1577 case 0364:
1578 case 0365:
1579 break;
1580
1581 case 0366:
1582 case 0367:
1583 *bytes = c - 0366 + 0x66;
1584 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1585 offset += 1;
1586 break;
1587
1588 case 0370:
1589 case 0371:
1590 case 0372:
1591 break;
1592
1593 case 0373:
1594 *bytes = bits == 16 ? 3 : 5;
1595 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1596 offset += 1;
1597 break;
1598
1599 default: /* can't do it by 'case' statements */
1600 if (c >= 0100 && c <= 0277) { /* it's an EA */
1601 ea ea_data;
1602 int rfield;
1603 int32_t rflags;
1604 uint8_t *p;
1605 int32_t s;
1606
1607 if (c <= 0177) {
1608 /* pick rfield from operand b */
1609 rflags = regflag(&ins->oprs[c & 7]);
1610 rfield = regvals[ins->oprs[c & 7].basereg];
1611 } else {
1612 /* rfield is constant */
1613 rflags = 0;
1614 rfield = c & 7;
1615 }
1616
1617 if (!process_ea
1618 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1619 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1620 errfunc(ERR_NONFATAL, "invalid effective address");
1621 }
1622
1623
1624 p = bytes;
1625 *p++ = ea_data.modrm;
1626 if (ea_data.sib_present)
1627 *p++ = ea_data.sib;
1628
1629 /* DREX suffixes come between the SIB and the displacement */
1630 if (ins->rex & REX_D) {
1631 *p++ =
1632 (ins->drexdst << 4) |
1633 (ins->rex & REX_OC ? 0x08 : 0) |
1634 (ins->rex & (REX_R|REX_X|REX_B));
1635 ins->rex = 0;
1636 }
1637
1638 s = p - bytes;
1639 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1640
1641 switch (ea_data.bytes) {
1642 case 0:
1643 break;
1644 case 1:
1645 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1646 data = ins->oprs[(c >> 3) & 7].offset;
1647 out(offset, segment, &data, OUT_ADDRESS, 1,
1648 ins->oprs[(c >> 3) & 7].segment,
1649 ins->oprs[(c >> 3) & 7].wrt);
1650 } else {
1651 *bytes = ins->oprs[(c >> 3) & 7].offset;
1652 out(offset, segment, bytes, OUT_RAWDATA, 1,
1653 NO_SEG, NO_SEG);
1654 }
1655 s++;
1656 break;
1657 case 8:
1658 case 2:
1659 case 4:
1660 data = ins->oprs[(c >> 3) & 7].offset;
1661 warn_overflow(ea_data.bytes, data);
1662 out(offset, segment, &data,
1663 ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS,
1664 ea_data.bytes,
1665 ins->oprs[(c >> 3) & 7].segment,
1666 ins->oprs[(c >> 3) & 7].wrt);
1667 s += ea_data.bytes;
1668 break;
1669 }
1670 offset += s;
1671 } else {
1672 errfunc(ERR_PANIC, "internal instruction table corrupt"
1673 ": instruction code 0x%02X given", c);
1674 }
1675 }
1676 }
1677 }
1678
1679 static int32_t regflag(const operand * o)
1680 {
1681 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1682 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1683 }
1684 return reg_flags[o->basereg];
1685 }
1686
1687 static int32_t regval(const operand * o)
1688 {
1689 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1690 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1691 }
1692 return regvals[o->basereg];
1693 }
1694
1695 static int op_rexflags(const operand * o, int mask)
1696 {
1697 int32_t flags;
1698 int val;
1699
1700 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1701 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1702 }
1703
1704 flags = reg_flags[o->basereg];
1705 val = regvals[o->basereg];
1706
1707 return rexflags(val, flags, mask);
1708 }
1709
1710 static int rexflags(int val, int32_t flags, int mask)
1711 {
1712 int rex = 0;
1713
1714 if (val >= 8)
1715 rex |= REX_B|REX_X|REX_R;
1716 if (flags & BITS64)
1717 rex |= REX_W;
1718 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1719 rex |= REX_H;
1720 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1721 rex |= REX_P;
1722
1723 return rex & mask;
1724 }
1725
1726 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1727 {
1728 int i, size[MAX_OPERANDS], asize, oprs, ret;
1729
1730 ret = 100;
1731
1732 /*
1733 * Check the opcode
1734 */
1735 if (itemp->opcode != instruction->opcode)
1736 return 0;
1737
1738 /*
1739 * Count the operands
1740 */
1741 if (itemp->operands != instruction->operands)
1742 return 0;
1743
1744 /*
1745 * Check that no spurious colons or TOs are present
1746 */
1747 for (i = 0; i < itemp->operands; i++)
1748 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1749 return 0;
1750
1751 /*
1752 * Check that the operand flags all match up
1753 */
1754 for (i = 0; i < itemp->operands; i++) {
1755 if (itemp->opd[i] & SAME_AS) {
1756 int j = itemp->opd[i] & ~SAME_AS;
1757 if (instruction->oprs[i].type != instruction->oprs[j].type ||
1758 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
1759 return 0;
1760 } else if (itemp->opd[i] & ~instruction->oprs[i].type ||
1761 ((itemp->opd[i] & SIZE_MASK) &&
1762 ((itemp->opd[i] ^ instruction->oprs[i].type) & SIZE_MASK))) {
1763 if ((itemp->opd[i] & ~instruction->oprs[i].type & ~SIZE_MASK) ||
1764 (instruction->oprs[i].type & SIZE_MASK))
1765 return 0;
1766 else
1767 return 1;
1768 }
1769 }
1770
1771 /*
1772 * Check operand sizes
1773 */
1774 if (itemp->flags & IF_ARMASK) {
1775 memset(size, 0, sizeof size);
1776
1777 switch (itemp->flags & IF_ARMASK) {
1778 case IF_AR0:
1779 i = 0;
1780 break;
1781 case IF_AR1:
1782 i = 1;
1783 break;
1784 case IF_AR2:
1785 i = 2;
1786 break;
1787 case IF_AR3:
1788 i = 3;
1789 break;
1790 default:
1791 break; /* Shouldn't happen */
1792 }
1793 switch (itemp->flags & IF_SMASK) {
1794 case IF_SB:
1795 size[i] = BITS8;
1796 break;
1797 case IF_SW:
1798 size[i] = BITS16;
1799 break;
1800 case IF_SD:
1801 size[i] = BITS32;
1802 break;
1803 case IF_SQ:
1804 size[i] = BITS64;
1805 break;
1806 case IF_SO:
1807 size[i] = BITS128;
1808 break;
1809 default:
1810 break;
1811 }
1812 } else {
1813 asize = 0;
1814 switch (itemp->flags & IF_SMASK) {
1815 case IF_SB:
1816 asize = BITS8;
1817 oprs = itemp->operands;
1818 break;
1819 case IF_SW:
1820 asize = BITS16;
1821 oprs = itemp->operands;
1822 break;
1823 case IF_SD:
1824 asize = BITS32;
1825 oprs = itemp->operands;
1826 break;
1827 case IF_SQ:
1828 asize = BITS64;
1829 oprs = itemp->operands;
1830 break;
1831 case IF_SO:
1832 asize = BITS128;
1833 oprs = itemp->operands;
1834 break;
1835 default:
1836 break;
1837 }
1838 for (i = 0; i < MAX_OPERANDS; i++)
1839 size[i] = asize;
1840 }
1841
1842 if (itemp->flags & (IF_SM | IF_SM2)) {
1843 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
1844 asize = 0;
1845 for (i = 0; i < oprs; i++) {
1846 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
1847 int j;
1848 for (j = 0; j < oprs; j++)
1849 size[j] = asize;
1850 break;
1851 }
1852 }
1853 } else {
1854 oprs = itemp->operands;
1855 }
1856
1857 for (i = 0; i < itemp->operands; i++) {
1858 if (!(itemp->opd[i] & SIZE_MASK) &&
1859 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
1860 return 2;
1861 }
1862
1863 /*
1864 * Check template is okay at the set cpu level
1865 */
1866 if (((itemp->flags & IF_PLEVEL) > cpu))
1867 return 3;
1868
1869 /*
1870 * Check if instruction is available in long mode
1871 */
1872 if ((itemp->flags & IF_NOLONG) && (bits == 64))
1873 return 4;
1874
1875 /*
1876 * Check if special handling needed for Jumps
1877 */
1878 if ((uint8_t)(itemp->code[0]) >= 0370)
1879 return 99;
1880
1881 return ret;
1882 }
1883
1884 static ea *process_ea(operand * input, ea * output, int bits,
1885 int addrbits, int rfield, int32_t rflags, int forw_ref)
1886 {
1887 output->rip = false;
1888
1889 /* REX flags for the rfield operand */
1890 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
1891
1892 if (!(REGISTER & ~input->type)) { /* register direct */
1893 int i;
1894 int32_t f;
1895
1896 if (input->basereg < EXPR_REG_START /* Verify as Register */
1897 || input->basereg >= REG_ENUM_LIMIT)
1898 return NULL;
1899 f = regflag(input);
1900 i = regvals[input->basereg];
1901
1902 if (REG_EA & ~f)
1903 return NULL; /* Invalid EA register */
1904
1905 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
1906
1907 output->sib_present = false; /* no SIB necessary */
1908 output->bytes = 0; /* no offset necessary either */
1909 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
1910 } else { /* it's a memory reference */
1911 if (input->basereg == -1
1912 && (input->indexreg == -1 || input->scale == 0)) {
1913 /* it's a pure offset */
1914 if (bits == 64 && (~input->type & IP_REL)) {
1915 int scale, index, base;
1916 output->sib_present = true;
1917 scale = 0;
1918 index = 4;
1919 base = 5;
1920 output->sib = (scale << 6) | (index << 3) | base;
1921 output->bytes = 4;
1922 output->modrm = 4 | ((rfield & 7) << 3);
1923 output->rip = false;
1924 } else {
1925 output->sib_present = false;
1926 output->bytes = (addrbits != 16 ? 4 : 2);
1927 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
1928 output->rip = bits == 64;
1929 }
1930 } else { /* it's an indirection */
1931 int i = input->indexreg, b = input->basereg, s = input->scale;
1932 int32_t o = input->offset, seg = input->segment;
1933 int hb = input->hintbase, ht = input->hinttype;
1934 int t;
1935 int it, bt;
1936 int32_t ix, bx; /* register flags */
1937
1938 if (s == 0)
1939 i = -1; /* make this easy, at least */
1940
1941 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
1942 it = regvals[i];
1943 ix = reg_flags[i];
1944 } else {
1945 it = -1;
1946 ix = 0;
1947 }
1948
1949 if (b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
1950 bt = regvals[b];
1951 bx = reg_flags[b];
1952 } else {
1953 bt = -1;
1954 bx = 0;
1955 }
1956
1957 /* check for a 32/64-bit memory reference... */
1958 if ((ix|bx) & (BITS32|BITS64)) {
1959 /* it must be a 32/64-bit memory reference. Firstly we have
1960 * to check that all registers involved are type E/Rxx. */
1961 int32_t sok = BITS32|BITS64;
1962
1963 if (it != -1) {
1964 if (!(REG64 & ~ix) || !(REG32 & ~ix))
1965 sok &= ix;
1966 else
1967 return NULL;
1968 }
1969
1970 if (bt != -1) {
1971 if (REG_GPR & ~bx)
1972 return NULL; /* Invalid register */
1973 if (~sok & bx & SIZE_MASK)
1974 return NULL; /* Invalid size */
1975 sok &= bx;
1976 }
1977
1978 /* While we're here, ensure the user didn't specify
1979 WORD or QWORD. */
1980 if (input->disp_size == 16 || input->disp_size == 64)
1981 return NULL;
1982
1983 if (addrbits == 16 ||
1984 (addrbits == 32 && !(sok & BITS32)) ||
1985 (addrbits == 64 && !(sok & BITS64)))
1986 return NULL;
1987
1988 /* now reorganize base/index */
1989 if (s == 1 && bt != it && bt != -1 && it != -1 &&
1990 ((hb == b && ht == EAH_NOTBASE)
1991 || (hb == i && ht == EAH_MAKEBASE))) {
1992 /* swap if hints say so */
1993 t = bt, bt = it, it = t;
1994 t = bx, bx = ix, ix = t;
1995 }
1996 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
1997 bt = -1, bx = 0, s++;
1998 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
1999 /* make single reg base, unless hint */
2000 bt = it, bx = ix, it = -1, ix = 0;
2001 }
2002 if (((s == 2 && it != REG_NUM_ESP
2003 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
2004 || s == 5 || s == 9) && bt == -1)
2005 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2006 if (it == -1 && (bt & 7) != REG_NUM_ESP
2007 && (input->eaflags & EAF_TIMESTWO))
2008 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2009 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2010 if (s == 1 && it == REG_NUM_ESP) {
2011 /* swap ESP into base if scale is 1 */
2012 t = it, it = bt, bt = t;
2013 t = ix, ix = bx, bx = t;
2014 }
2015 if (it == REG_NUM_ESP
2016 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2017 return NULL; /* wrong, for various reasons */
2018
2019 output->rex |= rexflags(it, ix, REX_X);
2020 output->rex |= rexflags(bt, bx, REX_B);
2021
2022 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2023 /* no SIB needed */
2024 int mod, rm;
2025
2026 if (bt == -1) {
2027 rm = 5;
2028 mod = 0;
2029 } else {
2030 rm = (bt & 7);
2031 if (rm != REG_NUM_EBP && o == 0 &&
2032 seg == NO_SEG && !forw_ref &&
2033 !(input->eaflags &
2034 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2035 mod = 0;
2036 else if (input->eaflags & EAF_BYTEOFFS ||
2037 (o >= -128 && o <= 127 && seg == NO_SEG
2038 && !forw_ref
2039 && !(input->eaflags & EAF_WORDOFFS)))
2040 mod = 1;
2041 else
2042 mod = 2;
2043 }
2044
2045 output->sib_present = false;
2046 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2047 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2048 } else {
2049 /* we need a SIB */
2050 int mod, scale, index, base;
2051
2052 if (it == -1)
2053 index = 4, s = 1;
2054 else
2055 index = (it & 7);
2056
2057 switch (s) {
2058 case 1:
2059 scale = 0;
2060 break;
2061 case 2:
2062 scale = 1;
2063 break;
2064 case 4:
2065 scale = 2;
2066 break;
2067 case 8:
2068 scale = 3;
2069 break;
2070 default: /* then what the smeg is it? */
2071 return NULL; /* panic */
2072 }
2073
2074 if (bt == -1) {
2075 base = 5;
2076 mod = 0;
2077 } else {
2078 base = (bt & 7);
2079 if (base != REG_NUM_EBP && o == 0 &&
2080 seg == NO_SEG && !forw_ref &&
2081 !(input->eaflags &
2082 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2083 mod = 0;
2084 else if (input->eaflags & EAF_BYTEOFFS ||
2085 (o >= -128 && o <= 127 && seg == NO_SEG
2086 && !forw_ref
2087 && !(input->eaflags & EAF_WORDOFFS)))
2088 mod = 1;
2089 else
2090 mod = 2;
2091 }
2092
2093 output->sib_present = true;
2094 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2095 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2096 output->sib = (scale << 6) | (index << 3) | base;
2097 }
2098 } else { /* it's 16-bit */
2099 int mod, rm;
2100
2101 /* check for 64-bit long mode */
2102 if (addrbits == 64)
2103 return NULL;
2104
2105 /* check all registers are BX, BP, SI or DI */
2106 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2107 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2108 && i != R_SI && i != R_DI))
2109 return NULL;
2110
2111 /* ensure the user didn't specify DWORD/QWORD */
2112 if (input->disp_size == 32 || input->disp_size == 64)
2113 return NULL;
2114
2115 if (s != 1 && i != -1)
2116 return NULL; /* no can do, in 16-bit EA */
2117 if (b == -1 && i != -1) {
2118 int tmp = b;
2119 b = i;
2120 i = tmp;
2121 } /* swap */
2122 if ((b == R_SI || b == R_DI) && i != -1) {
2123 int tmp = b;
2124 b = i;
2125 i = tmp;
2126 }
2127 /* have BX/BP as base, SI/DI index */
2128 if (b == i)
2129 return NULL; /* shouldn't ever happen, in theory */
2130 if (i != -1 && b != -1 &&
2131 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2132 return NULL; /* invalid combinations */
2133 if (b == -1) /* pure offset: handled above */
2134 return NULL; /* so if it gets to here, panic! */
2135
2136 rm = -1;
2137 if (i != -1)
2138 switch (i * 256 + b) {
2139 case R_SI * 256 + R_BX:
2140 rm = 0;
2141 break;
2142 case R_DI * 256 + R_BX:
2143 rm = 1;
2144 break;
2145 case R_SI * 256 + R_BP:
2146 rm = 2;
2147 break;
2148 case R_DI * 256 + R_BP:
2149 rm = 3;
2150 break;
2151 } else
2152 switch (b) {
2153 case R_SI:
2154 rm = 4;
2155 break;
2156 case R_DI:
2157 rm = 5;
2158 break;
2159 case R_BP:
2160 rm = 6;
2161 break;
2162 case R_BX:
2163 rm = 7;
2164 break;
2165 }
2166 if (rm == -1) /* can't happen, in theory */
2167 return NULL; /* so panic if it does */
2168
2169 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2170 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2171 mod = 0;
2172 else if (input->eaflags & EAF_BYTEOFFS ||
2173 (o >= -128 && o <= 127 && seg == NO_SEG
2174 && !forw_ref
2175 && !(input->eaflags & EAF_WORDOFFS)))
2176 mod = 1;
2177 else
2178 mod = 2;
2179
2180 output->sib_present = false; /* no SIB - it's 16-bit */
2181 output->bytes = mod; /* bytes of offset needed */
2182 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2183 }
2184 }
2185 }
2186
2187 output->size = 1 + output->sib_present + output->bytes;
2188 return output;
2189 }
2190
2191 static void add_asp(insn *ins, int addrbits)
2192 {
2193 int j, valid;
2194 int defdisp;
2195
2196 valid = (addrbits == 64) ? 64|32 : 32|16;
2197
2198 switch (ins->prefixes[PPS_ASIZE]) {
2199 case P_A16:
2200 valid &= 16;
2201 break;
2202 case P_A32:
2203 valid &= 32;
2204 break;
2205 case P_A64:
2206 valid &= 64;
2207 break;
2208 case P_ASP:
2209 valid &= (addrbits == 32) ? 16 : 32;
2210 break;
2211 default:
2212 break;
2213 }
2214
2215 for (j = 0; j < ins->operands; j++) {
2216 if (!(MEMORY & ~ins->oprs[j].type)) {
2217 int32_t i, b;
2218
2219 /* Verify as Register */
2220 if (ins->oprs[j].indexreg < EXPR_REG_START
2221 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2222 i = 0;
2223 else
2224 i = reg_flags[ins->oprs[j].indexreg];
2225
2226 /* Verify as Register */
2227 if (ins->oprs[j].basereg < EXPR_REG_START
2228 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2229 b = 0;
2230 else
2231 b = reg_flags[ins->oprs[j].basereg];
2232
2233 if (ins->oprs[j].scale == 0)
2234 i = 0;
2235
2236 if (!i && !b) {
2237 int ds = ins->oprs[j].disp_size;
2238 if ((addrbits != 64 && ds > 8) ||
2239 (addrbits == 64 && ds == 16))
2240 valid &= ds;
2241 } else {
2242 if (!(REG16 & ~b))
2243 valid &= 16;
2244 if (!(REG32 & ~b))
2245 valid &= 32;
2246 if (!(REG64 & ~b))
2247 valid &= 64;
2248
2249 if (!(REG16 & ~i))
2250 valid &= 16;
2251 if (!(REG32 & ~i))
2252 valid &= 32;
2253 if (!(REG64 & ~i))
2254 valid &= 64;
2255 }
2256 }
2257 }
2258
2259 if (valid & addrbits) {
2260 ins->addr_size = addrbits;
2261 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2262 /* Add an address size prefix */
2263 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2264 ins->prefixes[PPS_ASIZE] = pref;
2265 ins->addr_size = (addrbits == 32) ? 16 : 32;
2266 } else {
2267 /* Impossible... */
2268 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2269 ins->addr_size = addrbits; /* Error recovery */
2270 }
2271
2272 defdisp = ins->addr_size == 16 ? 16 : 32;
2273
2274 for (j = 0; j < ins->operands; j++) {
2275 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2276 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2277 != ins->addr_size) {
2278 /* mem_offs sizes must match the address size; if not,
2279 strip the MEM_OFFS bit and match only EA instructions */
2280 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2281 }
2282 }
2283 }
Automatic testing