| commit | d85a6101d731083fa3faae901426e731881f52d4 | |
| author | H. Peter Anvin (Intel) <hpa@zytor.com> | |
| Mon, 22 Jun 2020 20:44:54 +0000 (22 13:44 -0700) | ||
| committer | H. Peter Anvin (Intel) <hpa@zytor.com> | |
| Mon, 22 Jun 2020 20:52:02 +0000 (22 13:52 -0700) | ||
| tree | 13b7b70e699b681abea591647f87a2c0efc200a9 | treesnapshot (tar.gz zip) |
| parent | 6e9554f0677752fd41674a0e20623d83b381d6da | commitdiff |
BR 3392681: handle a64 instruction patters correctly
The a64 instruction patterns would incorrectly force REX to zero at a
point where REX prefixes have already been assigned. This is not only
incorrect in case of instructions which can use high registers, but it
causes an assertion failure. It happened to work for J*CXZ and LOOP*.
Reported-by: Philip Lantz <philip.lantz@intel.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The a64 instruction patterns would incorrectly force REX to zero at a
point where REX prefixes have already been assigned. This is not only
incorrect in case of instructions which can use high registers, but it
causes an assertion failure. It happened to work for J*CXZ and LOOP*.
Reported-by: Philip Lantz <philip.lantz@intel.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
| asm/assemble.c | diffblobblamehistory | |
| test/a64.asm | [new file with mode: 0644] | blob |
| x86/insns.dat | diffblobblamehistory |