| commit | 7812644665f652830fe618716eab4d7e8993af87 | |
| author | H. Peter Anvin <hpa@zytor.com> | |
| Thu, 15 Nov 2007 22:38:19 +0000 (15 14:38 -0800) | ||
| committer | H. Peter Anvin <hpa@zytor.com> | |
| Thu, 15 Nov 2007 22:38:19 +0000 (15 14:38 -0800) | ||
| tree | d05f4043ef6289f9e6c79d966df9b0ba474d8575 | treesnapshot (tar.gz zip) |
| parent | 428fd671ec9d10095ce3a52c7b50276a63f377ae | commitdiff |
BR 993895: Support zero-operand floating-point insn
Support the zero-operand form of floating-point instructions. Note
that in most cases, the form generated is actually the "popping" form,
e.g. "FADD" becomes "FADDP st0,st1". This is in accordance with the
Intel documentation. "FADDP" is also supported.
Support the zero-operand form of floating-point instructions. Note
that in most cases, the form generated is actually the "popping" form,
e.g. "FADD" becomes "FADDP st0,st1". This is in accordance with the
Intel documentation. "FADDP" is also supported.
| insns.dat | diffblobblamehistory | |
| test/fpu.asm | [new file with mode: 0644] | blob |