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added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / lib / cimarron / cim / cim_vip.c
blob6a741b7d9fdb56de18e0ac0754936aead17fafa8
1 /*
2 * <LIC_AMD_STD>
3 * Copyright (C) 2005 Advanced Micro Devices, Inc. All Rights Reserved.
4 * </LIC_AMD_STD>
5 *
6 * <CTL_AMD_STD>
7 * </CTL_AMD_STD>
8 *
9 * <DOC_AMD_STD>
10 * Cimarron VIP configuration routines.
11 * </DOC_AMD_STD>
12 *
13 */
14
15 /*---------------------------------------------------------------------------
16 * vip_initialize
17 *
18 * This routine initializes the internal module state and prepares the
19 * module for subsequent VIP orientated activities.
20 *---------------------------------------------------------------------------*/
21
22 int vip_initialize(VIPSETMODEBUFFER *buffer)
23 {
24 unsigned long vip_control1, vip_control2, vip_control3;
25
26 if (!buffer)
27 return CIM_STATUS_INVALIDPARAMS;
28
29 vip_control1 = 0;
30 vip_control2 = 0;
31 vip_control3 = 0;
32
33 /* CONFIGURE CONTROL WORDS BASED ON MODE STRUCTURE */
34 /* Note that some of the input parameters match the register fields */
35 /* they represent. */
36
37 /* STREAM ENABLES */
38
39 vip_control1 |= buffer->stream_enables;
40
41 /* VIP CAPTURE MODE */
42
43 vip_control1 |= buffer->operating_mode;
44
45 /* HANDLE PLANAR CAPTURE */
46
47 if (buffer->flags & VIP_MODEFLAG_PLANARCAPTURE)
48 {
49 vip_control1 |= VIP_CONTROL1_PLANAR;
50
51 if (buffer->planar_capture == VIP_420CAPTURE_EVERYLINE)
52 {
53 vip_control1 |= VIP_CONTROL1_DISABLE_DECIMATION;
54 }
55 else if (buffer->planar_capture == VIP_420CAPTURE_ALTERNATINGFIELDS)
56 {
57 if (buffer->flags & VIP_MODEFLAG_PROGRESSIVE)
58 return CIM_STATUS_INVALIDPARAMS;
59
60 vip_control1 |= VIP_CONTROL1_DISABLE_DECIMATION;
61 vip_control3 |= VIP_CONTROL3_DECIMATE_EVEN;
62 }
63 else if (buffer->planar_capture != VIP_420CAPTURE_ALTERNATINGLINES)
64 return CIM_STATUS_INVALIDPARAMS;
65
66 /* CONFIGURE THE VIDEO FIFO THRESHOLD BASED ON THE FIFO DEPTH */
67
68 vip_control2 |= VIP_CONTROL2_DEFAULT_VIDTH_420 << VIP_CONTROL2_VIDTH_SHIFT;
69
70 }
71 else
72 {
73 vip_control2 |= VIP_CONTROL2_DEFAULT_VIDTH_422 << VIP_CONTROL2_VIDTH_SHIFT;
74 }
75
76 /* CONFIGURE DEFAULT ANCILARRY THRESHOLD AND VIDEO FLUSH VALUES */
77
78 vip_control2 |= VIP_CONTROL2_DEFAULT_ANCTH << VIP_CONTROL2_ANCTH_SHIFT;
79 vip_control1 |= VIP_CONTROL1_DEFAULT_ANC_FF << VIP_CONTROL1_ANC_FF_SHIFT;
80 vip_control1 |= VIP_CONTROL1_DEFAULT_VID_FF << VIP_CONTROL1_VID_FF_SHIFT;
81
82 /* PROGRAM VIP OPTIONS */
83 /* The options are sanitized based on the current configuration. */
84
85 if (buffer->flags & VIP_MODEFLAG_PROGRESSIVE)
86 vip_control1 |= VIP_CONTROL1_NON_INTERLACED;
87 else
88 {
89 if (buffer->flags & VIP_MODEFLAG_TOGGLEEACHFIELD)
90 vip_control3 |= VIP_CONTROL3_BASE_UPDATE;
91 if (buffer->flags & VIP_MODEFLAG_INVERTPOLARITY)
92 vip_control2 |= VIP_CONTROL2_INVERT_POLARITY;
93 }
94
95 if ((buffer->operating_mode == VIP_MODE_MSG ||
96 buffer->operating_mode == VIP_MODE_DATA) &&
97 (buffer->flags & VIP_MODEFLAG_FLIPMESSAGEWHENFULL))
98 {
99 vip_control1 |= VIP_CONTROL1_MSG_STRM_CTRL;
100 }
101
102 else if (buffer->operating_mode == VIP_MODE_VIP2_8BIT ||
103 buffer->operating_mode == VIP_MODE_VIP2_16BIT)
104 {
105 if (buffer->flags & VIP_MODEFLAG_ENABLEREPEATFLAG)
106 vip_control2 |= VIP_CONTROL2_REPEAT_ENABLE;
107 if (buffer->flags & VIP_MODEFLAG_INVERTTASKPOLARITY)
108 vip_control3 |= VIP_CONTROL3_TASK_POLARITY;
109 }
110
111 if (buffer->flags & VIP_MODEFLAG_DISABLEZERODETECT)
112 vip_control1 |= VIP_CONTROL1_DISABLE_ZERO_DETECT;
113 if (buffer->flags & VIP_MODEFLAG_10BITANCILLARY)
114 vip_control2 |= VIP_CONTROL2_ANC10;
115
116 /* WRITE THE CONTROL REGISTERS */
117 /* The control registers are kept 'live' to allow separate instances of */
118 /* Cimarron to control the VIP hardware. */
119
120 WRITE_VIP32 (VIP_CONTROL1, vip_control1);
121 WRITE_VIP32 (VIP_CONTROL2, vip_control2);
122 WRITE_VIP32 (VIP_CONTROL3, vip_control3);
123
124 /* CONFIGURE 601 PARAMETERS */
125
126 if (buffer->operating_mode == VIP_MODE_8BIT601 ||
127 buffer->operating_mode == VIP_MODE_16BIT601)
128 {
129 vip_update_601_params (&buffer->vip601_settings);
130 }
131
132 return CIM_STATUS_OK;
133 }
134
135 /*---------------------------------------------------------------------------
136 * vip_update_601_params
137 *
138 * This routine configures all aspects of 601 VIP data capture, including
139 * start and stop timings and input polarities.
140 *---------------------------------------------------------------------------*/
141
142 int vip_update_601_params (VIP_601PARAMS *buffer)
143 {
144 unsigned long vip_control3, vip_control1;
145
146 if (!buffer)
147 return CIM_STATUS_INVALIDPARAMS;
148
149 vip_control1 = READ_VIP32 (VIP_CONTROL3);
150 vip_control3 = READ_VIP32 (VIP_CONTROL3);
151
152 if (buffer->flags & VIP_MODEFLAG_VSYNCACTIVEHIGH) vip_control3 |= VIP_CONTROL3_VSYNC_POLARITY;
153 else vip_control3 &= ~VIP_CONTROL3_VSYNC_POLARITY;
154 if (buffer->flags & VIP_MODEFLAG_HSYNCACTIVEHIGH) vip_control3 |= VIP_CONTROL3_HSYNC_POLARITY;
155 else vip_control3 &= ~VIP_CONTROL3_HSYNC_POLARITY;
156
157 WRITE_VIP32 (VIP_CONTROL3, vip_control3);
158 WRITE_VIP32 (VIP_601_HORZ_START, buffer->horz_start);
159 WRITE_VIP32 (VIP_601_VBI_START, buffer->vbi_start);
160 WRITE_VIP32 (VIP_601_VBI_END, buffer->vbi_start + buffer->vbi_height - 1);
161 WRITE_VIP32 (VIP_601_EVEN_START_STOP,
162 buffer->vert_start_even | ((buffer->vert_start_even + buffer->even_height - 1) << 16));
163 WRITE_VIP32 (VIP_601_ODD_START_STOP,
164 buffer->vert_start_odd | ((buffer->vert_start_odd + buffer->odd_height - 1) << 16));
165 WRITE_VIP32 (VIP_ODD_FIELD_DETECT,
166 buffer->odd_detect_start | (buffer->odd_detect_end << 16));
167
168 /* SPECIAL CASE FOR HORIZONTAL DATA */
169 /* 601 horizontal parameters are based on the number of clocks and not the */
170 /* number of pixels. */
171
172 if ((vip_control1 & VIP_CONTROL1_MODE_MASK) == VIP_MODE_16BIT601)
173 WRITE_VIP32 (VIP_601_HORZ_END, buffer->horz_start + (buffer->width << 1) + 3);
174 else
175 WRITE_VIP32 (VIP_601_HORZ_END, buffer->horz_start + buffer->width + 3);
176
177 return CIM_STATUS_OK;
178 }
179
180 /*---------------------------------------------------------------------------
181 * vip_configure_capture_buffers
182 *
183 * This routine configures the base offsets for video, ancillary or message
184 * mode capture. The input structure can also contain multiple offsets, such
185 * that the calling application can avoid updating the structure for each flip.
186 *
187 * The new buffer addresses are written to the hardware registers although
188 * they may not be latched immediately. Calling vip_is_buffer_update_latched
189 * allows the determination of whether the update has occured.
190 *
191 * Review the Cimarron VIP API documentation to determine which buffer addresses are
192 * latched immediately.
193 *---------------------------------------------------------------------------*/
194
195 int vip_configure_capture_buffers (int buffer_type, VIPINPUTBUFFER *buffer)
196 {
197 VIPINPUTBUFFER_ADDR *offsets;
198 unsigned long cur_buffer = buffer->current_buffer;
199
200 if (!buffer)
201 return CIM_STATUS_INVALIDPARAMS;
202
203 if (buffer_type == VIP_BUFFER_A || buffer_type == VIP_BUFFER_601)
204 {
205 offsets = &buffer->offsets[VIP_BUFFER_TASK_A];
206
207 /* SET VIDEO PITCH */
208
209 WRITE_VIP32 (VIP_TASKA_VID_PITCH, offsets->y_pitch | (offsets->uv_pitch << 16));
210
211 /* SET BASE OFFSETS */
212
213 if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY)
214 {
215 WRITE_VIP32 (VIP_TASKA_VID_ODD_BASE, offsets->even_base[cur_buffer]);
216 WRITE_VIP32 (VIP_TASKA_VID_EVEN_BASE, offsets->odd_base[cur_buffer]);
217 if (buffer->flags & VIP_INPUTFLAG_VBI)
218 {
219 WRITE_VIP32 (VIP_TASKA_VBI_ODD_BASE, offsets->vbi_even_base);
220 WRITE_VIP32 (VIP_TASKA_VBI_EVEN_BASE, offsets->vbi_odd_base);
221 }
222 }
223 else
224 {
225 WRITE_VIP32 (VIP_TASKA_VID_ODD_BASE, offsets->odd_base[cur_buffer]);
226 WRITE_VIP32 (VIP_TASKA_VID_EVEN_BASE, offsets->even_base[cur_buffer]);
227 if (buffer->flags & VIP_INPUTFLAG_VBI)
228 {
229 WRITE_VIP32 (VIP_TASKA_VBI_ODD_BASE, offsets->vbi_odd_base);
230 WRITE_VIP32 (VIP_TASKA_VBI_EVEN_BASE, offsets->vbi_even_base);
231 }
232 }
233
234 /* SET 4:2:0 OFFSETS */
235
236 if (buffer->flags & VIP_INPUTFLAG_PLANAR)
237 {
238 WRITE_VIP32 (VIP_TASKA_U_OFFSET, offsets->odd_uoffset);
239 WRITE_VIP32 (VIP_TASKA_V_OFFSET, offsets->odd_voffset);
240 WRITE_VIP32 (VIP_TASKA_U_EVEN_OFFSET, offsets->even_uoffset);
241 WRITE_VIP32 (VIP_TASKA_V_EVEN_OFFSET, offsets->even_voffset);
242 }
243 }
244 else if (buffer_type == VIP_BUFFER_B)
245 {
246 offsets = &buffer->offsets[VIP_BUFFER_TASK_B];
247
248 /* SET VIDEO PITCH */
249
250 WRITE_VIP32 (VIP_TASKB_VID_PITCH, offsets->y_pitch | (offsets->uv_pitch << 16));
251
252 /* SET BASE OFFSETS */
253
254 if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY)
255 {
256 WRITE_VIP32 (VIP_TASKB_VID_ODD_BASE, offsets->even_base[cur_buffer]);
257 WRITE_VIP32 (VIP_TASKB_VID_EVEN_BASE, offsets->odd_base[cur_buffer]);
258 if (buffer->flags & VIP_INPUTFLAG_VBI)
259 {
260 WRITE_VIP32 (VIP_TASKB_VBI_ODD_BASE, offsets->vbi_even_base);
261 WRITE_VIP32 (VIP_TASKB_VBI_EVEN_BASE, offsets->vbi_odd_base);
262 }
263 }
264 else
265 {
266 WRITE_VIP32 (VIP_TASKB_VID_ODD_BASE, offsets->odd_base[cur_buffer]);
267 WRITE_VIP32 (VIP_TASKB_VID_EVEN_BASE, offsets->even_base[cur_buffer]);
268 if (buffer->flags & VIP_INPUTFLAG_VBI)
269 {
270 WRITE_VIP32 (VIP_TASKB_VBI_ODD_BASE, offsets->vbi_odd_base);
271 WRITE_VIP32 (VIP_TASKB_VBI_EVEN_BASE, offsets->vbi_even_base);
272 }
273 }
274
275 /* SET 4:2:0 OFFSETS */
276
277 if (buffer->flags & VIP_INPUTFLAG_PLANAR)
278 {
279 WRITE_VIP32 (VIP_TASKB_U_OFFSET, offsets->odd_uoffset);
280 WRITE_VIP32 (VIP_TASKB_V_OFFSET, offsets->odd_voffset);
281 }
282 }
283 else if (buffer_type == VIP_BUFFER_ANC || buffer_type == VIP_BUFFER_MSG)
284 {
285 WRITE_VIP32(VIP_ANC_MSG1_BASE, buffer->ancillaryData.msg1_base);
286 WRITE_VIP32(VIP_ANC_MSG2_BASE, buffer->ancillaryData.msg2_base);
287 WRITE_VIP32(VIP_ANC_MSG_SIZE, buffer->ancillaryData.msg_size);
288 }
289 else
290 {
291 return CIM_STATUS_INVALIDPARAMS;
292 }
293
294 return CIM_STATUS_OK;
295 }
296
297 /*---------------------------------------------------------------------------
298 * vip_toggle_vip_video_offsets
299 *
300 * This routine updates the offsets for video capture. It is a simplified
301 * version of vip_configure_capture_buffers that is designed to be called from
302 * interrupt service routines or other buffer flipping applications that
303 * require low latency.
304 *---------------------------------------------------------------------------*/
305
306 int vip_toggle_video_offsets (int buffer_type, VIPINPUTBUFFER *buffer)
307 {
308 unsigned long cur_buffer = buffer->current_buffer;
309 VIPINPUTBUFFER_ADDR *offsets;
310
311 if (buffer_type == VIP_BUFFER_A)
312 {
313 offsets = &buffer->offsets[VIP_BUFFER_TASK_A];
314
315 /* SET BASE OFFSETS */
316
317 if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY)
318 {
319 WRITE_VIP32 (VIP_TASKA_VID_ODD_BASE, offsets->even_base[cur_buffer]);
320 WRITE_VIP32 (VIP_TASKA_VID_EVEN_BASE, offsets->odd_base[cur_buffer]);
321 }
322 else
323 {
324 WRITE_VIP32 (VIP_TASKA_VID_ODD_BASE, offsets->odd_base[cur_buffer]);
325 WRITE_VIP32 (VIP_TASKA_VID_EVEN_BASE, offsets->even_base[cur_buffer]);
326 }
327 }
328 else if (buffer_type == VIP_BUFFER_B)
329 {
330 offsets = &buffer->offsets[VIP_BUFFER_TASK_B];
331
332 /* SET BASE OFFSETS */
333
334 if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY)
335 {
336 WRITE_VIP32 (VIP_TASKB_VID_ODD_BASE, offsets->even_base[cur_buffer]);
337 WRITE_VIP32 (VIP_TASKB_VID_EVEN_BASE, offsets->odd_base[cur_buffer]);
338 }
339 else
340 {
341 WRITE_VIP32 (VIP_TASKB_VID_ODD_BASE, offsets->odd_base[cur_buffer]);
342 WRITE_VIP32 (VIP_TASKB_VID_EVEN_BASE, offsets->even_base[cur_buffer]);
343 }
344 }
345 else if (buffer_type == VIP_BUFFER_A_ODD)
346 {
347 offsets = &buffer->offsets[VIP_BUFFER_TASK_A];
348
349 /* SET BASE OFFSETS */
350
351 if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY)
352 WRITE_VIP32 (VIP_TASKA_VID_ODD_BASE, offsets->even_base[cur_buffer]);
353 else
354 WRITE_VIP32 (VIP_TASKA_VID_ODD_BASE, offsets->odd_base[cur_buffer]);
355 }
356 else if (buffer_type == VIP_BUFFER_A_EVEN)
357 {
358 offsets = &buffer->offsets[VIP_BUFFER_TASK_A];
359
360 /* SET BASE OFFSETS */
361
362 if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY)
363 WRITE_VIP32 (VIP_TASKA_VID_EVEN_BASE, offsets->odd_base[cur_buffer]);
364 else
365 WRITE_VIP32 (VIP_TASKA_VID_EVEN_BASE, offsets->even_base[cur_buffer]);
366 }
367 else if (buffer_type == VIP_BUFFER_B_ODD)
368 {
369 offsets = &buffer->offsets[VIP_BUFFER_TASK_B];
370
371 /* SET BASE OFFSETS */
372
373 if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY)
374 WRITE_VIP32 (VIP_TASKB_VID_ODD_BASE, offsets->even_base[cur_buffer]);
375 else
376 WRITE_VIP32 (VIP_TASKB_VID_ODD_BASE, offsets->odd_base[cur_buffer]);
377 }
378 else if (buffer_type == VIP_BUFFER_B_EVEN)
379 {
380 offsets = &buffer->offsets[VIP_BUFFER_TASK_B];
381
382 /* SET BASE OFFSETS */
383
384 if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY)
385 WRITE_VIP32 (VIP_TASKB_VID_EVEN_BASE, offsets->odd_base[cur_buffer]);
386 else
387 WRITE_VIP32 (VIP_TASKB_VID_EVEN_BASE, offsets->even_base[cur_buffer]);
388 }
389 else
390 return CIM_STATUS_INVALIDPARAMS;
391
392 return CIM_STATUS_OK;
393 }
394
395 /*---------------------------------------------------------------------------
396 * vip_set_capture_state
397 *
398 * This routine takes the current control word definition ( stored in locals )
399 * adds in the specified state, and writes the control word.
400 *---------------------------------------------------------------------------*/
401
402 int vip_set_capture_state (unsigned long state)
403 {
404 unsigned long vip_control1, vip_control3;
405
406 /* UPDATE THE CURRENT CAPTURE MODE */
407
408 vip_control1 = READ_VIP32 (VIP_CONTROL1);
409 vip_control3 = READ_VIP32 (VIP_CONTROL3);
410 vip_control1 &= ~VIP_CONTROL1_RUNMODE_MASK;
411 vip_control1 |= (state << VIP_CONTROL1_RUNMODE_SHIFT);
412
413 WRITE_VIP32 (VIP_CONTROL1, vip_control1);
414
415 if (state >= VIP_STARTCAPTUREATNEXTLINE)
416 {
417 /* WHACK VIP RESET */
418 /* The VIP can get confused when switching between capture settings, such as */
419 /* between linear and planar. We will thus whack VIP reset when enabling */
420 /* capture to ensure a pristine VIP state. */
421
422 WRITE_VIP32 (VIP_CONTROL1, vip_control1 | VIP_CONTROL1_RESET);
423 WRITE_VIP32 (VIP_CONTROL1, vip_control1 & ~VIP_CONTROL1_RESET);
424 WRITE_VIP32 (VIP_CONTROL3, vip_control3 | VIP_CONTROL3_FIFO_RESET);
425 }
426
427 return CIM_STATUS_OK;
428 }
429
430 /*---------------------------------------------------------------------------
431 * vip_terminate
432 *
433 * This routine stops VIP capture and resets the VIP internal state.
434 *---------------------------------------------------------------------------*/
435
436 int vip_terminate (void)
437 {
438 unsigned long timeout = 50000;
439
440 /* DISABLE AND CLEAR ALL VIP INTERRUPTS */
441
442 WRITE_VIP32 (VIP_INTERRUPT, VIP_ALL_INTERRUPTS | (VIP_ALL_INTERRUPTS >> 16));
443
444 /* DISABLE VIP CAPTURE */
445 /* We will try to let the VIP FIFO flush before shutting it down. */
446
447 WRITE_VIP32 (VIP_CONTROL1, 0);
448 while (timeout)
449 {
450 timeout--;
451 if (READ_VIP32 (VIP_STATUS) & VIP_STATUS_WRITES_COMPLETE)
452 break;
453 }
454
455 /* RESET THE HARDWARE REGISTERS */
456 /* Note that we enable VIP reset to allow clock gating to lower VIP */
457 /* power consumption. */
458
459 WRITE_VIP32 (VIP_CONTROL1, VIP_CONTROL1_RESET);
460 WRITE_VIP32 (VIP_CONTROL3, VIP_CONTROL3_FIFO_RESET);
461 WRITE_VIP32 (VIP_CONTROL2, 0);
462
463 return CIM_STATUS_OK;
464 }
465
466 /*---------------------------------------------------------------------------
467 * vip_configure_fifo
468 *
469 * This routine sets the desired threshold or flush for the specified fifo.
470 *---------------------------------------------------------------------------*/
471
472 int vip_configure_fifo (unsigned long fifo_type, unsigned long fifo_size)
473 {
474 unsigned long vip_control1, vip_control2;
475
476 vip_control1 = READ_VIP32 (VIP_CONTROL1);
477 vip_control2 = READ_VIP32 (VIP_CONTROL2);
478
479 switch (fifo_type)
480 {
481 case VIP_VIDEOTHRESHOLD:
482 vip_control2 &= ~VIP_CONTROL2_VIDTH_MASK;
483 vip_control2 |= (fifo_size << VIP_CONTROL2_VIDTH_SHIFT) & VIP_CONTROL2_VIDTH_MASK;
484 break;
485
486 case VIP_ANCILLARYTHRESHOLD:
487 vip_control2 &= ~VIP_CONTROL2_ANCTH_MASK;
488 vip_control2 |= (fifo_size << VIP_CONTROL2_ANCTH_SHIFT) & VIP_CONTROL2_ANCTH_MASK;
489 break;
490
491 case VIP_VIDEOFLUSH:
492 vip_control1 &= ~VIP_CONTROL1_VID_FF_MASK;
493 vip_control1 |= ((fifo_size >> 2) << VIP_CONTROL1_VID_FF_SHIFT) & VIP_CONTROL1_VID_FF_MASK;
494 break;
495
496 case VIP_ANCILLARYFLUSH:
497 vip_control1 &= ~VIP_CONTROL1_ANC_FF_MASK;
498 vip_control1 |= ((fifo_size >> 2) << VIP_CONTROL1_ANC_FF_SHIFT) & VIP_CONTROL1_ANC_FF_MASK;
499 break;
500
501 default:
502 return CIM_STATUS_INVALIDPARAMS;
503 }
504
505 WRITE_VIP32 (VIP_CONTROL1, vip_control1);
506 WRITE_VIP32 (VIP_CONTROL2, vip_control2);
507
508 return CIM_STATUS_OK;
509 }
510
511 /*---------------------------------------------------------------------------
512 * vip_set_interrupt_enable
513 *
514 * This routine accepts a mask of interrupts to be enabled/disabled and
515 * an enable flag.
516 *
517 * For each mask match, the interrupt will be enabled or disabled based on
518 * enable
519 *---------------------------------------------------------------------------*/
520
521 int vip_set_interrupt_enable (unsigned long mask, int enable)
522 {
523 /* CHECK IF ANY VALID INTERRUPTS ARE BEING CHANGED */
524
525 if (mask & VIP_ALL_INTERRUPTS)
526 {
527 unsigned long int_enable = READ_VIP32(VIP_INTERRUPT) & 0xFFFF;
528
529 /* SET OR CLEAR THE MASK BITS */
530 /* Note that the upper 16-bits of the register are 0 after this */
531 /* operation. This prevents us from indadvertently clearing a */
532 /* pending interrupt by enabling/disabling another one. */
533
534 if (enable) int_enable &= ~(mask >> 16);
535 else int_enable |= (mask >> 16);
536
537 WRITE_VIP32 (VIP_INTERRUPT, int_enable);
538 }
539
540 return CIM_STATUS_OK;
541 }
542
543 /*---------------------------------------------------------------------------
544 * vip_set_vsync_error
545 *
546 * This routine defines a region that is used to determine if the vsync is
547 * within an acceptable range. This definition is accomplished using
548 * a count and a vertical window. The count specifies the exact number
549 * of clocks expected for one field. The window parameters specify the number
550 * of clocks variation allowed before and after the expected vsync. For
551 * example, if vertical_count is 1000, window_before is 5 and window_after
552 * is 12, VSync will be considered valid if it occurs between 995 and 1012
553 * clocks after the last VSync. The total window size (window_before + window_after)
554 * cannot exceed 255.
555 *---------------------------------------------------------------------------*/
556
557 int vip_set_vsync_error (unsigned long vertical_count, unsigned long window_before,
558 unsigned long window_after, int enable)
559 {
560 unsigned long vip_control2 = READ_VIP32 (VIP_CONTROL2);
561 unsigned long temp;
562
563 if (enable)
564 {
565 /* CREATE THE VERTICAL WINDOW */
566 /* The VIP uses two counters. The first counter defines the minimum clock count */
567 /* before a valid VSync can occur. The second counter starts after the first */
568 /* completes and defines the acceptable region of variation. */
569
570 temp = ((window_before + window_after) << VIP_VSYNC_ERR_WINDOW_SHIFT) & VIP_VSYNC_ERR_WINDOW_MASK;
571 temp |= (vertical_count - window_before) & VIP_VSYNC_ERR_COUNT_MASK;
572
573 vip_control2 |= VIP_CONTROL2_VERTERROR_ENABLE;
574
575 WRITE_VIP32(VIP_VSYNC_ERR_COUNT, temp);
576 }
577 else
578 {
579 vip_control2 &= ~VIP_CONTROL2_VERTERROR_ENABLE;
580 }
581 WRITE_VIP32 (VIP_CONTROL2, vip_control2);
582
583 return CIM_STATUS_OK;
584 }
585
586 /*---------------------------------------------------------------------------
587 * vip_max_address_enable
588 *
589 * This routine specifies the maximum address to which the the hardware should
590 * write during data storage. If this value is exceeded an error is generated,
591 * (this may be monitored using the appropriate interrupt flags - see
592 * vip_set_interrupt_enable)
593 *---------------------------------------------------------------------------*/
594
595 int vip_max_address_enable (unsigned long max_address, int enable)
596 {
597 unsigned long vip_control2 = READ_VIP32 (VIP_CONTROL2);
598
599 if (enable)
600 {
601 /* ENABLE THE CONTROL BIT */
602
603 vip_control2 |= VIP_CONTROL2_ADD_ERROR_ENABLE;
604
605 WRITE_VIP32(VIP_MAX_ADDRESS, max_address & VIP_MAXADDR_MASK);
606 }
607 else
608 {
609 /* DISABLE DETECTION */
610
611 vip_control2 &= ~VIP_CONTROL2_ADD_ERROR_ENABLE;
612 }
613 WRITE_VIP32 (VIP_CONTROL2, vip_control2);
614
615 return CIM_STATUS_OK;
616 }
617
618 /*---------------------------------------------------------------------------
619 * vip_set_loopback_enable
620 *
621 * This routine enables/disables internal loopback functionality. When
622 * loopback is enabled, the VOP outputs are rerouted to the VIP inputs
623 * internal to the chip. No loopback connector is required.
624 *---------------------------------------------------------------------------*/
625
626 int vip_set_loopback_enable(int enable)
627 {
628 unsigned long vip_control2 = READ_VIP32 (VIP_CONTROL2);
629
630 if (enable) vip_control2 |= VIP_CONTROL2_LOOPBACK_ENABLE;
631 else vip_control2 &= ~VIP_CONTROL2_LOOPBACK_ENABLE;
632
633 WRITE_VIP32 (VIP_CONTROL2, vip_control2);
634
635 return CIM_STATUS_OK;
636 }
637
638 /*---------------------------------------------------------------------------
639 * vip_configure_genlock
640 *
641 * This routine configures genlock functionality.
642 *---------------------------------------------------------------------------*/
643
644 int vip_configure_genlock (VIPGENLOCKBUFFER *buffer)
645 {
646 unsigned long vip_control1, vip_control2;
647 unsigned long unlock, genlk_ctl;
648
649 if (!buffer)
650 return CIM_STATUS_INVALIDPARAMS;
651
652 unlock = READ_REG32 (DC3_UNLOCK);
653 genlk_ctl = READ_REG32 (DC3_GENLK_CTL);
654 vip_control1 = READ_VIP32 (VIP_CONTROL1);
655 vip_control2 = READ_VIP32 (VIP_CONTROL2);
656
657 /* UPDATE VIDEO DETECTION */
658 /* These flags are used to indicate the ways in which the VIP signal can */
659 /* be considered 'lost'. */
660
661 vip_control1 &= ~VIP_CONTROL1_VDE_FF_MASK;
662 vip_control2 &= ~(VIP_CONTROL2_FIELD2VG_MASK | VIP_CONTROL2_SYNC2VG_MASK);
663 vip_control1 |= buffer->vip_signal_loss;
664
665 /* UPDATE FIELD AND VSYNC INFORMATION */
666 /* These flags control how and when the even/odd field and Vsync */
667 /* information is communicated to the VG. */
668
669 vip_control2 |= buffer->field_to_vg;
670 vip_control2 |= buffer->vsync_to_vg;
671
672 /* ENABLE OR DISABLE GENLOCK TIMEOUT */
673 /* Enabling genlock timeout allows the VG to revert to its own sync */
674 /* timings when the VIP input is lost. Note that the VIP will not */
675 /* know the signal is lost unless the appropriate error detection */
676 /* flags have been enabled inside vip_initialize. */
677
678 if (buffer->enable_timeout) genlk_ctl |= DC3_GC_GENLOCK_TO_ENABLE;
679 else genlk_ctl &= ~DC3_GC_GENLOCK_TO_ENABLE;
680
681 genlk_ctl &= ~DC3_GC_GENLOCK_SKEW_MASK;
682 genlk_ctl |= buffer->genlock_skew & DC3_GC_GENLOCK_SKEW_MASK;
683
684 WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE);
685 WRITE_REG32 (DC3_GENLK_CTL, genlk_ctl);
686 WRITE_VIP32 (VIP_CONTROL1, vip_control1);
687 WRITE_VIP32 (VIP_CONTROL2, vip_control2);
688 WRITE_REG32 (DC3_UNLOCK, unlock);
689
690 return CIM_STATUS_OK;
691 }
692
693 /*---------------------------------------------------------------------------
694 * vip_set_genlock_enable
695 *
696 * This routine enables/disables genlock inside the VG.
697 *---------------------------------------------------------------------------*/
698
699 int vip_set_genlock_enable (int enable)
700 {
701 unsigned long unlock, temp;
702
703 unlock = READ_REG32 (DC3_UNLOCK);
704 temp = READ_REG32 (DC3_GENLK_CTL);
705
706 if (enable) temp |= DC3_GC_GENLOCK_ENABLE;
707 else temp &= ~DC3_GC_GENLOCK_ENABLE;
708
709 WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE);
710 WRITE_REG32 (DC3_GENLK_CTL, temp);
711 WRITE_REG32 (DC3_UNLOCK, unlock);
712
713 return CIM_STATUS_OK;
714 }
715
716 /*---------------------------------------------------------------------------
717 * vip_set_power_characteristics
718 *
719 * This routine takes a VIPPOWERBUFFER structure, and selectively sets the
720 * GeodeLink power and/or Vip clock power states.
721 *---------------------------------------------------------------------------*/
722
723 int vip_set_power_characteristics (VIPPOWERBUFFER *buffer)
724 {
725 Q_WORD q_word;
726
727 if (!buffer)
728 return CIM_STATUS_INVALIDPARAMS;
729
730 q_word.low = q_word.high = 0;
731
732 /* ENABLE GEODELINK CLOCK GATING */
733
734 if (buffer->glink_clock_mode)
735 q_word.low |= VIP_MSR_POWER_GLINK;
736
737 /* ENABLE VIP CLOCK GATING */
738
739 if (buffer->vip_clock_mode)
740 q_word.low |= VIP_MSR_POWER_CLOCK;
741
742 /* WRITE THE NEW VALUE */
743
744 msr_write64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_PM, &q_word);
745
746 return CIM_STATUS_OK;
747 }
748
749 /*---------------------------------------------------------------------------
750 * vip_set_priority_characteristics
751 *
752 * This routine programs the VIP GeodeLink priority characteristics
753 *---------------------------------------------------------------------------*/
754
755 int vip_set_priority_characteristics (VIPPRIORITYBUFFER *buffer)
756 {
757 Q_WORD q_word;
758
759 if (!buffer)
760 return CIM_STATUS_INVALIDPARAMS;
761
762 q_word.low = q_word.high = 0;
763
764 q_word.low |= (buffer->secondary << VIP_MSR_MCR_SECOND_PRIORITY_SHIFT) & VIP_MSR_MCR_SECOND_PRIORITY_MASK;
765 q_word.low |= (buffer->primary << VIP_MSR_MCR_PRIMARY_PRIORITY_SHIFT) & VIP_MSR_MCR_PRIMARY_PRIORITY_MASK;
766 q_word.low |= (buffer->pid << VIP_MSR_MCR_PID_SHIFT) & VIP_MSR_MCR_PID_MASK;
767
768 msr_write64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_CONFIG, &q_word);
769
770 return CIM_STATUS_OK;
771 }
772
773 /*---------------------------------------------------------------------------
774 * vip_set_debug_characteristics
775 *
776 * This routine configures the debug data that is exposed over the diag bus.
777 *---------------------------------------------------------------------------*/
778
779 int vip_set_debug_characteristics (VIPDEBUGBUFFER *buffer)
780 {
781 Q_WORD q_word;
782
783 if (!buffer)
784 return CIM_STATUS_INVALIDPARAMS;
785
786 q_word.low = q_word.high = 0;
787
788 q_word.high |= (buffer->bist << VIP_MSR_DIAG_BIST_SHIFT) & VIP_MSR_DIAG_BIST_WMASK;
789 q_word.low |= (buffer->enable_upper ? VIP_MSR_DIAG_MSB_ENABLE : 0x00000000);
790 q_word.low |= (buffer->select_upper << VIP_MSR_DIAG_SEL_UPPER_SHIFT) & VIP_MSR_DIAG_SEL_UPPER_MASK;
791 q_word.low |= (buffer->enable_lower ? VIP_MSR_DIAG_LSB_ENABLE : 0x00000000 );
792 q_word.low |= (buffer->select_lower << VIP_MSR_DIAG_SEL_LOWER_SHIFT) & VIP_MSR_DIAG_SEL_LOWER_MASK;
793
794 msr_write64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_DIAG, &q_word);
795
796 return CIM_STATUS_OK;
797 }
798
799 /*---------------------------------------------------------------------------
800 * vip_configure_pages
801 *
802 * This routine sets the number of pages, and their offset from each other.
803 *---------------------------------------------------------------------------*/
804
805 int vip_configure_pages (int page_count, unsigned long page_offset)
806 {
807 unsigned long vip_control2 = READ_VIP32 (VIP_CONTROL2);
808
809 /* SET THE NEW PAGE COUNT */
810
811 vip_control2 &= ~VIP_CONTROL2_PAGECNT_MASK;
812 vip_control2 |= (page_count << VIP_CONTROL2_PAGECNT_SHIFT) & VIP_CONTROL2_PAGECNT_MASK;
813
814 /* WRITE THE PAGE OFFSET */
815
816 WRITE_VIP32 (VIP_CONTROL2, vip_control2);
817 WRITE_VIP32 (VIP_PAGE_OFFSET, page_offset);
818
819 return CIM_STATUS_OK;
820 }
821
822 /*---------------------------------------------------------------------------
823 * vip_set_interrupt_line
824 *
825 * This routine sets the line at which a line interrupt should be generated.
826 *---------------------------------------------------------------------------*/
827
828 int vip_set_interrupt_line (int line)
829 {
830 WRITE_VIP32 (VIP_CURRENT_TARGET, (line << VIP_CTARGET_TLINE_SHIFT) & VIP_CTARGET_TLINE_MASK);
831
832 return CIM_STATUS_OK;
833 }
834
835 /*---------------------------------------------------------------------------
836 * vip_reset
837 *
838 * This routine does a one-shot enable of the VIP hardware. It is useful
839 * for handling unrecoverable VIP errors.
840 *---------------------------------------------------------------------------*/
841
842 int vip_reset (void)
843 {
844 unsigned long vip_control1, vip_control3;
845
846 /* INVERT THE PAUSE BIT */
847
848 vip_control1 = READ_VIP32 (VIP_CONTROL1);
849 vip_control3 = READ_VIP32 (VIP_CONTROL3);
850
851 WRITE_VIP32 (VIP_CONTROL1, vip_control1 | VIP_CONTROL1_RESET);
852 WRITE_VIP32 (VIP_CONTROL1, vip_control1 & ~VIP_CONTROL1_RESET);
853 WRITE_VIP32 (VIP_CONTROL3, vip_control3 | VIP_CONTROL3_FIFO_RESET);
854
855 return CIM_STATUS_OK;
856 }
857
858 /*---------------------------------------------------------------------------
859 * vip_set_subwindow_enable
860 *
861 * This routine turns on SubWindow capture, that is a portion of the incoming
862 * signal is captured rather than the entire frame. The window always has
863 * the same width as the frame, only the vertical component can be
864 * modified.
865 *---------------------------------------------------------------------------*/
866
867 int vip_set_subwindow_enable (VIPSUBWINDOWBUFFER *buffer)
868 {
869 unsigned long vip_control2;
870
871 if (!buffer)
872 return CIM_STATUS_INVALIDPARAMS;
873
874 vip_control2 = READ_VIP32 (VIP_CONTROL2);
875 if (buffer->enable)
876 {
877 /* WRITE THE WINDOW VALUE */
878
879 WRITE_VIP32(VIP_VERTICAL_START_STOP,
880 ((buffer->stop << VIP_VSTART_VERTEND_SHIFT) & VIP_VSTART_VERTEND_MASK) |
881 ((buffer->start << VIP_VSTART_VERTSTART_SHIFT) & VIP_VSTART_VERTSTART_MASK));
882
883 /* ENABLE IN THE CONTROL REGISTER */
884
885 vip_control2 |= VIP_CONTROL2_SWC_ENABLE;
886 }
887 else
888 {
889 /* DISABLE SUBWINDOW CAPTURE IN THE CONTROL REGISTER */
890
891 vip_control2 &= ~VIP_CONTROL2_SWC_ENABLE;
892 }
893 WRITE_VIP32 (VIP_CONTROL2, vip_control2);
894
895 return CIM_STATUS_OK;
896 }
897
898 /*---------------------------------------------------------------------------
899 * vip_reset_interrupt_state
900 *
901 * This routine resets the state of one or more interrupts.
902 *---------------------------------------------------------------------------*/
903
904 int vip_reset_interrupt_state(unsigned long interrupt_mask)
905 {
906 unsigned long temp;
907
908 temp = READ_VIP32(VIP_INTERRUPT);
909 WRITE_VIP32 (VIP_INTERRUPT, temp | (interrupt_mask & VIP_ALL_INTERRUPTS));
910
911 return CIM_STATUS_OK;
912 }
913
914 /*---------------------------------------------------------------------------
915 * vip_save_state
916 *
917 * This routine saves the necessary register contents in order to restore
918 * at a later point to the same state.
919 *
920 * NOTE: Capture state is forced to OFF in this routine
921 *---------------------------------------------------------------------------*/
922
923 int vip_save_state(VIPSTATEBUFFER *save_buffer)
924 {
925 if (!save_buffer)
926 return CIM_STATUS_INVALIDPARAMS;
927
928 /* FORCE CAPTURE TO BE DISABLED */
929
930 vip_set_capture_state (VIP_STOPCAPTURE);
931
932 /* READ AND SAVE THE REGISTER CONTENTS */
933
934 save_buffer->control1 = READ_VIP32(VIP_CONTROL1);
935 save_buffer->control2 = READ_VIP32(VIP_CONTROL2);
936 save_buffer->vip_int = READ_VIP32(VIP_INTERRUPT);
937 save_buffer->current_target = READ_VIP32(VIP_CURRENT_TARGET);
938 save_buffer->max_address = READ_VIP32(VIP_MAX_ADDRESS);
939 save_buffer->taska_evenbase = READ_VIP32(VIP_TASKA_VID_EVEN_BASE);
940 save_buffer->taska_oddbase = READ_VIP32(VIP_TASKA_VID_ODD_BASE);
941 save_buffer->taska_vbi_evenbase = READ_VIP32(VIP_TASKA_VBI_EVEN_BASE);
942 save_buffer->taska_vbi_oddbase = READ_VIP32(VIP_TASKA_VBI_ODD_BASE);
943 save_buffer->taska_data_pitch = READ_VIP32(VIP_TASKA_VID_PITCH);
944 save_buffer->control3 = READ_VIP32(VIP_CONTROL3);
945 save_buffer->taska_v_oddoffset = READ_VIP32(VIP_TASKA_U_OFFSET);
946 save_buffer->taska_u_oddoffset = READ_VIP32(VIP_TASKA_V_OFFSET);
947 save_buffer->taskb_evenbase = READ_VIP32(VIP_TASKB_VID_EVEN_BASE);
948 save_buffer->taskb_oddbase = READ_VIP32(VIP_TASKB_VID_ODD_BASE);
949 save_buffer->taskb_vbi_evenbase = READ_VIP32(VIP_TASKB_VBI_EVEN_BASE);
950 save_buffer->taskb_vbi_oddbase = READ_VIP32(VIP_TASKB_VBI_ODD_BASE);
951 save_buffer->taskb_pitch = READ_VIP32(VIP_TASKB_VID_PITCH);
952 save_buffer->taskb_voffset = READ_VIP32(VIP_TASKB_U_OFFSET);
953 save_buffer->taskb_uoffset = READ_VIP32(VIP_TASKB_V_OFFSET);
954 save_buffer->msg1_base = READ_VIP32(VIP_ANC_MSG1_BASE);
955 save_buffer->msg2_base = READ_VIP32(VIP_ANC_MSG2_BASE);
956 save_buffer->msg_size = READ_VIP32(VIP_ANC_MSG_SIZE);
957 save_buffer->page_offset = READ_VIP32(VIP_PAGE_OFFSET);
958 save_buffer->vert_start_stop = READ_VIP32(VIP_VERTICAL_START_STOP);
959 save_buffer->vsync_err_count = READ_VIP32(VIP_VSYNC_ERR_COUNT);
960 save_buffer->taska_u_evenoffset = READ_VIP32(VIP_TASKA_U_EVEN_OFFSET);
961 save_buffer->taska_v_evenoffset = READ_VIP32(VIP_TASKA_V_EVEN_OFFSET);
962
963 /* READ ALL VIP MSRS */
964
965 msr_read64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_CONFIG, &(save_buffer->msr_config));
966 msr_read64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_SMI, &(save_buffer->msr_smi));
967 msr_read64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_PM, &(save_buffer->msr_pm));
968 msr_read64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_DIAG, &(save_buffer->msr_diag));
969
970 return CIM_STATUS_OK;
971 }
972
973 /*---------------------------------------------------------------------------
974 * vip_restore_state
975 *
976 * This routine restores the state of the vip registers - which were
977 * previously saved using vip_save_state.
978 *---------------------------------------------------------------------------*/
979
980 int vip_restore_state (VIPSTATEBUFFER *restore_buffer)
981 {
982 if (!restore_buffer)
983 return CIM_STATUS_OK;
984
985 /* RESTORE THE REGISTERS */
986
987 WRITE_VIP32(VIP_CURRENT_TARGET, restore_buffer->current_target);
988 WRITE_VIP32(VIP_MAX_ADDRESS, restore_buffer->max_address);
989 WRITE_VIP32(VIP_TASKA_VID_EVEN_BASE, restore_buffer->taska_evenbase);
990 WRITE_VIP32(VIP_TASKA_VID_ODD_BASE, restore_buffer->taska_oddbase);
991 WRITE_VIP32(VIP_TASKA_VBI_EVEN_BASE, restore_buffer->taska_vbi_evenbase);
992 WRITE_VIP32(VIP_TASKA_VBI_ODD_BASE, restore_buffer->taska_vbi_oddbase);
993 WRITE_VIP32(VIP_TASKA_VID_PITCH, restore_buffer->taska_data_pitch);
994 WRITE_VIP32(VIP_CONTROL3, restore_buffer->control3);
995 WRITE_VIP32(VIP_TASKA_U_OFFSET, restore_buffer->taska_v_oddoffset);
996 WRITE_VIP32(VIP_TASKA_V_OFFSET, restore_buffer->taska_u_oddoffset);
997 WRITE_VIP32(VIP_TASKB_VID_EVEN_BASE, restore_buffer->taskb_evenbase);
998 WRITE_VIP32(VIP_TASKB_VID_ODD_BASE, restore_buffer->taskb_oddbase);
999 WRITE_VIP32(VIP_TASKB_VBI_EVEN_BASE, restore_buffer->taskb_vbi_evenbase);
1000 WRITE_VIP32(VIP_TASKB_VBI_ODD_BASE, restore_buffer->taskb_vbi_oddbase);
1001 WRITE_VIP32(VIP_TASKB_VID_PITCH, restore_buffer->taskb_pitch);
1002 WRITE_VIP32(VIP_TASKB_U_OFFSET, restore_buffer->taskb_voffset);
1003 WRITE_VIP32(VIP_TASKB_V_OFFSET, restore_buffer->taskb_uoffset);
1004 WRITE_VIP32(VIP_ANC_MSG1_BASE, restore_buffer->msg1_base);
1005 WRITE_VIP32(VIP_ANC_MSG2_BASE, restore_buffer->msg2_base);
1006 WRITE_VIP32(VIP_ANC_MSG_SIZE, restore_buffer->msg_size);
1007 WRITE_VIP32(VIP_PAGE_OFFSET, restore_buffer->page_offset);
1008 WRITE_VIP32(VIP_VERTICAL_START_STOP, restore_buffer->vert_start_stop);
1009 WRITE_VIP32(VIP_VSYNC_ERR_COUNT, restore_buffer->vsync_err_count);
1010 WRITE_VIP32(VIP_TASKA_U_EVEN_OFFSET, restore_buffer->taska_u_evenoffset);
1011 WRITE_VIP32(VIP_TASKA_V_EVEN_OFFSET, restore_buffer->taska_v_evenoffset);
1012
1013 /* RESTORE THE VIP MSRS */
1014
1015 msr_write64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_CONFIG, &(restore_buffer->msr_config));
1016 msr_write64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_SMI, &(restore_buffer->msr_smi));
1017 msr_write64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_PM, &(restore_buffer->msr_pm));
1018 msr_write64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_DIAG, &(restore_buffer->msr_diag));
1019
1020 /* RESTORE THE CONTROL WORDS LAST */
1021
1022 WRITE_VIP32(VIP_CONTROL1, restore_buffer->control1);
1023 WRITE_VIP32(VIP_CONTROL2, restore_buffer->control2);
1024 WRITE_VIP32(VIP_CONTROL3, restore_buffer->control3);
1025
1026 return CIM_STATUS_OK;
1027 }
1028
1029 /*---------------------------------------------------------------------------
1030 * vip_get_interrupt_state
1031 *
1032 * This routine returns the current interrupt state of the system. The
1033 * rv can be tested with the following flags to determine if the appropriate
1034 * event has occured.
1035 *---------------------------------------------------------------------------*/
1036
1037 unsigned long vip_get_interrupt_state(void)
1038 {
1039 unsigned long interrupt_mask = READ_VIP32(VIP_INTERRUPT);
1040
1041 return (~(interrupt_mask << 16) & interrupt_mask & VIP_ALL_INTERRUPTS);
1042 }
1043
1044 /*---------------------------------------------------------------------------
1045 * vip_test_genlock_active
1046 *
1047 * This routine reads the live status of the genlock connection between the VIP
1048 * and VG blocks.
1049 *---------------------------------------------------------------------------*/
1050
1051 int vip_test_genlock_active (void)
1052 {
1053 if (READ_REG32 (DC3_GENLK_CTL) & DC3_GC_GENLK_ACTIVE)
1054 return 1;
1055
1056 return 0;
1057 }
1058
1059 /*---------------------------------------------------------------------------
1060 * vip_test_signal_status
1061 *
1062 * This routine reads the live signal status coming into the VIP block.
1063 *---------------------------------------------------------------------------*/
1064
1065 int vip_test_signal_status (void)
1066 {
1067 if (READ_REG32 (DC3_GENLK_CTL) & DC3_GC_VIP_VID_OK)
1068 return 1;
1069
1070 return 0;
1071 }
1072
1073 /*---------------------------------------------------------------------------
1074 * vip_get_current_field
1075 *
1076 * This routine returns the current field being received.
1077 *---------------------------------------------------------------------------*/
1078
1079 unsigned long vip_get_current_field (void)
1080 {
1081 if (READ_VIP32(VIP_STATUS) & VIP_STATUS_FIELD)
1082 return VIP_EVEN_FIELD;
1083
1084 return VIP_ODD_FIELD;
1085 }
1086
1087 /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1088 * CIMARRON VIP READ ROUTINES
1089 * These routines are included for use in diagnostics or when debugging. They
1090 * can be optionally excluded from a project.
1091 *+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
1092
1093 #if CIMARRON_INCLUDE_VIP_READ_ROUTINES
1094
1095 /*---------------------------------------------------------------------------
1096 * vip_get_current_mode
1097 *
1098 * This routine reads the current VIP operating mode.
1099 *---------------------------------------------------------------------------*/
1100
1101 int vip_get_current_mode (VIPSETMODEBUFFER *buffer)
1102 {
1103 unsigned long vip_control1, vip_control2, vip_control3;
1104
1105 if (!buffer)
1106 return CIM_STATUS_INVALIDPARAMS;
1107
1108 vip_control1 = READ_VIP32 (VIP_CONTROL1);
1109 vip_control2 = READ_VIP32 (VIP_CONTROL2);
1110 vip_control3 = READ_VIP32 (VIP_CONTROL3);
1111
1112 /* READ CURRENT OPERATING MODE AND ENABLES */
1113
1114 buffer->stream_enables = vip_control1 & VIP_ENABLE_ALL;
1115 buffer->operating_mode = vip_control1 & VIP_CONTROL1_MODE_MASK;
1116
1117 /* READ CURRENT PLANAR CAPTURE SETTINGS */
1118
1119 buffer->flags = 0;
1120 buffer->planar_capture = 0;
1121 if (vip_control1 & VIP_CONTROL1_PLANAR)
1122 {
1123 buffer->flags |= VIP_MODEFLAG_PLANARCAPTURE;
1124 if (vip_control1 & VIP_CONTROL1_DISABLE_DECIMATION)
1125 {
1126 if (vip_control3 & VIP_CONTROL3_DECIMATE_EVEN)
1127 buffer->planar_capture = VIP_420CAPTURE_ALTERNATINGFIELDS;
1128 else
1129 buffer->planar_capture = VIP_420CAPTURE_EVERYLINE;
1130 }
1131 else
1132 buffer->planar_capture = VIP_420CAPTURE_ALTERNATINGLINES;
1133 }
1134
1135 /* READ MISCELLANEOUS FLAGS */
1136
1137 if (vip_control1 & VIP_CONTROL1_NON_INTERLACED)
1138 buffer->flags |= VIP_MODEFLAG_PROGRESSIVE;
1139 if (vip_control3 & VIP_CONTROL3_BASE_UPDATE)
1140 buffer->flags |= VIP_MODEFLAG_TOGGLEEACHFIELD;
1141 if (vip_control2 & VIP_CONTROL2_INVERT_POLARITY)
1142 buffer->flags |= VIP_MODEFLAG_INVERTPOLARITY;
1143 if (vip_control1 & VIP_CONTROL1_MSG_STRM_CTRL)
1144 buffer->flags |= VIP_MODEFLAG_FLIPMESSAGEWHENFULL;
1145 if (vip_control2 & VIP_CONTROL2_REPEAT_ENABLE)
1146 buffer->flags |= VIP_MODEFLAG_ENABLEREPEATFLAG;
1147 if (vip_control3 & VIP_CONTROL3_TASK_POLARITY)
1148 buffer->flags |= VIP_MODEFLAG_INVERTTASKPOLARITY;
1149 if (vip_control1 & VIP_CONTROL1_DISABLE_ZERO_DETECT)
1150 buffer->flags |= VIP_MODEFLAG_DISABLEZERODETECT;
1151 if (vip_control2 & VIP_CONTROL2_ANC10)
1152 buffer->flags |= VIP_MODEFLAG_10BITANCILLARY;
1153
1154 /* READ THE CURRENT VIP 601 SETTINGS */
1155
1156 vip_get_601_configuration (&buffer->vip601_settings);
1157
1158 return CIM_STATUS_OK;
1159 }
1160
1161 /*---------------------------------------------------------------------------
1162 * vip_get_601_configuration
1163 *
1164 * This routine returns the current 601 configuration information.
1165 *---------------------------------------------------------------------------*/
1166
1167 int vip_get_601_configuration (VIP_601PARAMS *buffer)
1168 {
1169 unsigned long vip_control3, vip_control1;
1170
1171 if (!buffer)
1172 return CIM_STATUS_INVALIDPARAMS;
1173
1174 vip_control1 = READ_VIP32 (VIP_CONTROL3);
1175 vip_control3 = READ_VIP32 (VIP_CONTROL3);
1176
1177 buffer->flags = 0;
1178 if (vip_control3 & VIP_CONTROL3_VSYNC_POLARITY) buffer->flags |= VIP_MODEFLAG_VSYNCACTIVEHIGH;
1179 if (vip_control3 & VIP_CONTROL3_HSYNC_POLARITY) buffer->flags |= VIP_MODEFLAG_HSYNCACTIVEHIGH;
1180
1181 buffer->horz_start = READ_VIP32 (VIP_601_HORZ_START);
1182 buffer->vbi_start = READ_VIP32 (VIP_601_VBI_START);
1183 buffer->vbi_height = READ_VIP32 (VIP_601_VBI_END) - buffer->vbi_start + 1;
1184 buffer->vert_start_even = READ_VIP32 (VIP_601_EVEN_START_STOP) & 0xFFFF;
1185 buffer->even_height = (READ_VIP32 (VIP_601_EVEN_START_STOP) >> 16) - buffer->vert_start_even + 1;
1186 buffer->vert_start_odd = READ_VIP32 (VIP_601_ODD_START_STOP) & 0xFFFF;
1187 buffer->odd_height = (READ_VIP32 (VIP_601_ODD_START_STOP) >> 16) - buffer->vert_start_odd + 1;
1188 buffer->odd_detect_start = READ_VIP32 (VIP_ODD_FIELD_DETECT) & 0xFFFF;
1189 buffer->odd_detect_end = READ_VIP32 (VIP_ODD_FIELD_DETECT) >> 16;
1190
1191 /* SPECIAL CASE FOR HORIZONTAL DATA */
1192 /* 601 horizontal parameters are based on the number of clocks and not the */
1193 /* number of pixels. */
1194
1195 if ((vip_control1 & VIP_CONTROL1_MODE_MASK) == VIP_MODE_16BIT601)
1196 buffer->width = (READ_VIP32 (VIP_601_HORZ_END) - buffer->horz_start - 3) >> 1;
1197 else
1198 buffer->width = (READ_VIP32 (VIP_601_HORZ_END) - buffer->horz_start - 3);
1199
1200 return CIM_STATUS_OK;
1201 }
1202
1203 /*---------------------------------------------------------------------------
1204 * vip_get_buffer_configuration
1205 *
1206 * This routine reads the current buffer configuration for Task A, Task B,
1207 * ancillary or message data. The current_buffer member indicates which
1208 * array index should hold the new values for Task A or Task B data.
1209 *---------------------------------------------------------------------------*/
1210
1211 int vip_get_buffer_configuration (int buffer_type, VIPINPUTBUFFER *buffer)
1212 {
1213 unsigned long cur_buffer = buffer->current_buffer;
1214 VIPINPUTBUFFER_ADDR *offsets;
1215
1216 if (!buffer)
1217 return CIM_STATUS_INVALIDPARAMS;
1218
1219 if (buffer_type == VIP_BUFFER_A)
1220 {
1221 offsets = &buffer->offsets[VIP_BUFFER_TASK_A];
1222
1223 /* READ VIDEO PITCH */
1224
1225 offsets->y_pitch = READ_VIP32 (VIP_TASKA_VID_PITCH) & 0xFFFF;
1226 offsets->uv_pitch = READ_VIP32 (VIP_TASKA_VID_PITCH) >> 16;
1227
1228 /* READ BASE OFFSETS */
1229
1230 if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY)
1231 {
1232 offsets->even_base[cur_buffer] = READ_VIP32 (VIP_TASKA_VID_ODD_BASE);
1233 offsets->odd_base[cur_buffer] = READ_VIP32 (VIP_TASKA_VID_EVEN_BASE);
1234
1235 if (buffer->flags & VIP_INPUTFLAG_VBI)
1236 {
1237 offsets->vbi_even_base = READ_VIP32 (VIP_TASKA_VBI_ODD_BASE);
1238 offsets->vbi_odd_base = READ_VIP32 (VIP_TASKA_VBI_EVEN_BASE);
1239 }
1240 }
1241 else
1242 {
1243 offsets->even_base[cur_buffer] = READ_VIP32 (VIP_TASKA_VID_EVEN_BASE);
1244 offsets->odd_base[cur_buffer] = READ_VIP32 (VIP_TASKA_VID_ODD_BASE);
1245
1246 if (buffer->flags & VIP_INPUTFLAG_VBI)
1247 {
1248 offsets->vbi_even_base = READ_VIP32 (VIP_TASKA_VBI_EVEN_BASE);
1249 offsets->vbi_odd_base = READ_VIP32 (VIP_TASKA_VBI_ODD_BASE);
1250 }
1251 }
1252
1253 /* READ 4:2:0 OFFSETS */
1254
1255 if (buffer->flags & VIP_INPUTFLAG_PLANAR)
1256 {
1257 offsets->odd_uoffset = READ_VIP32 (VIP_TASKA_U_OFFSET);
1258 offsets->odd_voffset = READ_VIP32 (VIP_TASKA_V_OFFSET);
1259 offsets->even_uoffset = READ_VIP32 (VIP_TASKA_U_EVEN_OFFSET);
1260 offsets->even_voffset = READ_VIP32 (VIP_TASKA_V_EVEN_OFFSET);
1261 }
1262 }
1263 else if (buffer_type == VIP_BUFFER_B)
1264 {
1265 offsets = &buffer->offsets[VIP_BUFFER_TASK_B];
1266
1267 /* READ VIDEO PITCH */
1268
1269 offsets->y_pitch = READ_VIP32 (VIP_TASKB_VID_PITCH) & 0xFFFF;
1270 offsets->uv_pitch = READ_VIP32 (VIP_TASKB_VID_PITCH) >> 16;
1271
1272 /* READ BASE OFFSETS */
1273
1274 if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY)
1275 {
1276 offsets->even_base[cur_buffer] = READ_VIP32 (VIP_TASKB_VID_ODD_BASE);
1277 offsets->odd_base[cur_buffer] = READ_VIP32 (VIP_TASKB_VID_EVEN_BASE);
1278
1279 if (buffer->flags & VIP_INPUTFLAG_VBI)
1280 {
1281 offsets->vbi_even_base = READ_VIP32 (VIP_TASKB_VBI_ODD_BASE);
1282 offsets->vbi_odd_base = READ_VIP32 (VIP_TASKB_VBI_EVEN_BASE);
1283 }
1284 }
1285 else
1286 {
1287 offsets->even_base[cur_buffer] = READ_VIP32 (VIP_TASKB_VID_EVEN_BASE);
1288 offsets->odd_base[cur_buffer] = READ_VIP32 (VIP_TASKB_VID_ODD_BASE);
1289
1290 if (buffer->flags & VIP_INPUTFLAG_VBI)
1291 {
1292 offsets->vbi_even_base = READ_VIP32 (VIP_TASKB_VBI_EVEN_BASE);
1293 offsets->vbi_odd_base = READ_VIP32 (VIP_TASKB_VBI_ODD_BASE);
1294 }
1295 }
1296
1297 /* READ 4:2:0 OFFSETS */
1298
1299 if (buffer->flags & VIP_INPUTFLAG_PLANAR)
1300 {
1301 offsets->odd_uoffset = READ_VIP32 (VIP_TASKB_U_OFFSET);
1302 offsets->odd_voffset = READ_VIP32 (VIP_TASKB_V_OFFSET);
1303 }
1304 }
1305 else if (buffer_type == VIP_BUFFER_ANC || buffer_type == VIP_BUFFER_MSG)
1306 {
1307 buffer->ancillaryData.msg1_base = READ_VIP32(VIP_ANC_MSG1_BASE);
1308 buffer->ancillaryData.msg2_base = READ_VIP32(VIP_ANC_MSG2_BASE);
1309 buffer->ancillaryData.msg_size = READ_VIP32(VIP_ANC_MSG_SIZE);
1310 }
1311 else
1312 {
1313 return CIM_STATUS_INVALIDPARAMS;
1314 }
1315
1316 return CIM_STATUS_OK;
1317 }
1318
1319 /*---------------------------------------------------------------------------
1320 * vip_get_genlock_configuration
1321 *
1322 * This routine reads the current genlock configuration.
1323 *---------------------------------------------------------------------------*/
1324
1325 int vip_get_genlock_configuration (VIPGENLOCKBUFFER *buffer)
1326 {
1327 unsigned long vip_control1, vip_control2;
1328 unsigned long genlk_ctl;
1329
1330 if (!buffer)
1331 return CIM_STATUS_INVALIDPARAMS;
1332
1333 genlk_ctl = READ_REG32 (DC3_GENLK_CTL);
1334 vip_control1 = READ_VIP32 (VIP_CONTROL1);
1335 vip_control2 = READ_VIP32 (VIP_CONTROL2);
1336
1337 /* READ ERROR DETECTION, CURRENT FIELD AND CURRENT VSYNC */
1338 /* These flags are used to indicate the ways in which the VIP signal can */
1339 /* be considered 'lost'. */
1340
1341 buffer->vip_signal_loss = vip_control1 & VIP_CONTROL1_VDE_FF_MASK;
1342 buffer->field_to_vg = vip_control2 & VIP_CONTROL2_FIELD2VG_MASK;
1343 buffer->vsync_to_vg = vip_control2 & VIP_CONTROL2_SYNC2VG_MASK;
1344
1345 /* GENLOCK TIMEOUT ENABLE */
1346
1347 buffer->enable_timeout = 0;
1348 if (genlk_ctl & DC3_GC_GENLOCK_TO_ENABLE)
1349 buffer->enable_timeout = 1;
1350
1351 /* GENLOCK SKEW */
1352
1353 buffer->genlock_skew = genlk_ctl & DC3_GC_GENLOCK_SKEW_MASK;
1354
1355 return CIM_STATUS_OK;
1356 }
1357
1358 /*---------------------------------------------------------------------------
1359 * vip_get_genlock_enable
1360 *
1361 * This routine returns the current enable status of genlock in the VG.
1362 *---------------------------------------------------------------------------*/
1363
1364 int vip_get_genlock_enable (void)
1365 {
1366 if (READ_REG32 (DC3_GENLK_CTL) & DC3_GC_GENLOCK_ENABLE)
1367 return 1;
1368
1369 return 0;
1370 }
1371
1372 /*---------------------------------------------------------------------------
1373 * vip_is_buffer_update_latched
1374 *
1375 * This routine indicates whether changes to the VIP offsets have been latched by
1376 * the hardware.
1377 *---------------------------------------------------------------------------*/
1378
1379 int vip_is_buffer_update_latched (void)
1380 {
1381 return (!(READ_VIP32(VIP_STATUS) & VIP_STATUS_BASEREG_NOTUPDT));
1382 }
1383
1384 /*---------------------------------------------------------------------------
1385 * vip_get_capture_state
1386 *
1387 * This routine reads the current capture status of the VIP hardware.
1388 *---------------------------------------------------------------------------*/
1389
1390 unsigned long vip_get_capture_state (void)
1391 {
1392 return ((READ_VIP32(VIP_CONTROL1) & VIP_CONTROL1_RUNMODE_MASK) >> VIP_CONTROL1_RUNMODE_SHIFT);
1393 }
1394
1395 /*---------------------------------------------------------------------------
1396 * vip_get_current_line
1397 *
1398 * This routine returns the current line that is being processed.
1399 *---------------------------------------------------------------------------*/
1400
1401 unsigned long vip_get_current_line (void)
1402 {
1403 return (READ_VIP32(VIP_CURRENT_TARGET) & VIP_CTARGET_CLINE_MASK);
1404 }
1405
1406 /*---------------------------------------------------------------------------
1407 * vip_read_fifo
1408 *
1409 * This routine reads from the specified fifo address. As the fifo access
1410 * enable should be disabled when running in normal vip mode, this routine
1411 * enables and disables access around the read.
1412 * DIAGNOSTIC USE ONLY
1413 *---------------------------------------------------------------------------*/
1414
1415 unsigned long vip_read_fifo(unsigned long dwFifoAddress)
1416 {
1417 unsigned long fifo_data;
1418
1419 /* ENABLE FIFO ACCESS */
1420
1421 vip_enable_fifo_access (1);
1422
1423 /* NOW READ THE DATA */
1424
1425 WRITE_VIP32(VIP_FIFO_ADDRESS, dwFifoAddress);
1426 fifo_data = READ_VIP32(VIP_FIFO_DATA);
1427
1428 /* DISABLE FIFO ACCESS */
1429
1430 vip_enable_fifo_access (0);
1431
1432 return fifo_data;
1433 }
1434
1435 /*---------------------------------------------------------------------------
1436 * vip_write_fifo
1437 *
1438 * SYNOPSIS:
1439 * This routine writes to the specified fifo address. As the fifo access
1440 * enable should be disabled when running in normal vip mode, this routine
1441 * enables and disables access around the write.
1442 * DIAGNOSTIC USE ONLY
1443 *---------------------------------------------------------------------------*/
1444
1445 int vip_write_fifo (unsigned long dwFifoAddress, unsigned long dwFifoData)
1446 {
1447 /* ENABLE FIFO ACCESS */
1448
1449 vip_enable_fifo_access(1);
1450
1451 /* WRITE THE FIFO DATA */
1452
1453 WRITE_VIP32(VIP_FIFO_ADDRESS, dwFifoAddress);
1454 WRITE_VIP32(VIP_FIFO_DATA, dwFifoData);
1455
1456 /* DISABLE FIFO ACCESS */
1457
1458 vip_enable_fifo_access(0);
1459
1460 return CIM_STATUS_OK;
1461 }
1462
1463 /*---------------------------------------------------------------------------
1464 * vip_enable_fifo_access
1465 *
1466 * This routine enables/disables access to the vip fifo.
1467 * DIAGNOSTIC USE ONLY
1468 *---------------------------------------------------------------------------*/
1469
1470 int vip_enable_fifo_access (int enable)
1471 {
1472 unsigned long cw2;
1473
1474 cw2 = READ_VIP32(VIP_CONTROL2);
1475
1476 if (enable) cw2 |= VIP_CONTROL2_FIFO_ACCESS;
1477 else cw2 &= ~VIP_CONTROL2_FIFO_ACCESS;
1478
1479 WRITE_VIP32(VIP_CONTROL2, cw2);
1480
1481 return CIM_STATUS_OK;
1482 }
1483
1484 /*---------------------------------------------------------------------------
1485 * vip_get_power_characteristics
1486 *
1487 * This routine returns the current VIP clock gating state in a VIPPOWERBUFFER.
1488 *---------------------------------------------------------------------------*/
1489
1490 int vip_get_power_characteristics(VIPPOWERBUFFER *buffer)
1491 {
1492 Q_WORD q_word;
1493
1494 if (!buffer)
1495 return CIM_STATUS_INVALIDPARAMS;
1496
1497 /* READ THE EXISTING STATE */
1498
1499 msr_read64(MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_PM, &q_word);
1500
1501 /* DECODE THE CLOCK GATING BITS */
1502
1503 buffer->glink_clock_mode = (int)(q_word.low & VIP_MSR_POWER_GLINK);
1504 buffer->vip_clock_mode = (int)(q_word.low & VIP_MSR_POWER_CLOCK);
1505
1506 return CIM_STATUS_OK;
1507 }
1508
1509 /*---------------------------------------------------------------------------
1510 * vip_get_priority_characteristics
1511 *
1512 * This routine returns the priority characteristics in the supplied
1513 * VIPPRIORITYBUFFER.
1514 *---------------------------------------------------------------------------*/
1515
1516 int vip_get_priority_characteristics(VIPPRIORITYBUFFER *buffer)
1517 {
1518 Q_WORD q_word;
1519
1520 if (!buffer)
1521 return CIM_STATUS_INVALIDPARAMS;
1522
1523 /* READ THE CURRENT STATE */
1524
1525 msr_read64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_CONFIG, &q_word);
1526
1527 /* DECODE THE PRIORITIES */
1528
1529 buffer->secondary = (q_word.low & VIP_MSR_MCR_SECOND_PRIORITY_MASK) >> VIP_MSR_MCR_SECOND_PRIORITY_SHIFT;
1530 buffer->primary = (q_word.low & VIP_MSR_MCR_PRIMARY_PRIORITY_MASK) >> VIP_MSR_MCR_PRIMARY_PRIORITY_SHIFT;
1531 buffer->pid = q_word.low & VIP_MSR_MCR_PID_MASK;
1532
1533 return CIM_STATUS_OK;
1534 }
1535
1536 /*---------------------------------------------------------------------------
1537 * vip_get_capability_characteristics
1538 *
1539 * This routine returns revision information for the device.
1540 *---------------------------------------------------------------------------*/
1541
1542 int vip_get_capability_characteristics(VIPCAPABILITIESBUFFER *buffer)
1543 {
1544 Q_WORD q_word ;
1545
1546 if (!buffer)
1547 return CIM_STATUS_INVALIDPARAMS;
1548
1549 /* READ THE CURRENT MSR CONTENTS */
1550
1551 msr_read64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_CAP, &q_word);
1552
1553 /* DECODE THE REVISIONS */
1554
1555 buffer->revision_id = (q_word.low & VIP_MSR_CAP_REVID_MASK) >> VIP_MSR_CAP_REVID_SHIFT;
1556 buffer->device_id = (q_word.low & VIP_MSR_CAP_DEVID_MASK) >> VIP_MSR_CAP_DEVID_SHIFT;
1557 buffer->n_clock_domains = (q_word.low & VIP_MSR_CAP_NCLK_MASK) >> VIP_MSR_CAP_NCLK_SHIFT;
1558 buffer->n_smi_registers = (q_word.low & VIP_MSR_CAP_NSMI_MASK) >> VIP_MSR_CAP_NSMI_SHIFT;
1559
1560 return CIM_STATUS_OK;
1561 }
1562
1563
1564
1565 #endif
Nao low-level kernelspace/userspace library that runs on our robots, Nao-Team HTWK