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added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / drivers / video / tridentfb.c
blob479b2e79ad68ea569882bf7ce7df7645d648a02d
1 /*
2 * Frame buffer driver for Trident TGUI, Blade and Image series
3 *
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
5 *
6 *
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
13 * code, suggestions
14 * TODO:
15 * timing value tweaking so it looks good on every monitor in every mode
16 */
17
18 #include <linux/module.h>
19 #include <linux/fb.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
22
23 #include <linux/delay.h>
24 #include <video/vga.h>
25 #include <video/trident.h>
26
27 struct tridentfb_par {
28 void __iomem *io_virt; /* iospace virtual memory address */
29 u32 pseudo_pal[16];
30 int chip_id;
31 int flatpanel;
32 void (*init_accel) (struct tridentfb_par *, int, int);
33 void (*wait_engine) (struct tridentfb_par *);
34 void (*fill_rect)
35 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
36 void (*copy_rect)
37 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
38 void (*image_blit)
39 (struct tridentfb_par *par, const char*,
40 u32, u32, u32, u32, u32, u32);
41 unsigned char eng_oper; /* engine operation... */
42 };
43
44 static struct fb_fix_screeninfo tridentfb_fix = {
45 .id = "Trident",
46 .type = FB_TYPE_PACKED_PIXELS,
47 .ypanstep = 1,
48 .visual = FB_VISUAL_PSEUDOCOLOR,
49 .accel = FB_ACCEL_NONE,
50 };
51
52 /* defaults which are normally overriden by user values */
53
54 /* video mode */
55 static char *mode_option __devinitdata = "640x480-8@60";
56 static int bpp __devinitdata = 8;
57
58 static int noaccel __devinitdata;
59
60 static int center;
61 static int stretch;
62
63 static int fp __devinitdata;
64 static int crt __devinitdata;
65
66 static int memsize __devinitdata;
67 static int memdiff __devinitdata;
68 static int nativex;
69
70 module_param(mode_option, charp, 0);
71 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
72 module_param_named(mode, mode_option, charp, 0);
73 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
74 module_param(bpp, int, 0);
75 module_param(center, int, 0);
76 module_param(stretch, int, 0);
77 module_param(noaccel, int, 0);
78 module_param(memsize, int, 0);
79 module_param(memdiff, int, 0);
80 module_param(nativex, int, 0);
81 module_param(fp, int, 0);
82 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
83 module_param(crt, int, 0);
84 MODULE_PARM_DESC(crt, "Define if CRT is connected");
85
86 static inline int is_oldclock(int id)
87 {
88 return (id == TGUI9440) ||
89 (id == TGUI9660) ||
90 (id == CYBER9320);
91 }
92
93 static inline int is_oldprotect(int id)
94 {
95 return is_oldclock(id) ||
96 (id == PROVIDIA9685) ||
97 (id == CYBER9382) ||
98 (id == CYBER9385);
99 }
100
101 static inline int is_blade(int id)
102 {
103 return (id == BLADE3D) ||
104 (id == CYBERBLADEE4) ||
105 (id == CYBERBLADEi7) ||
106 (id == CYBERBLADEi7D) ||
107 (id == CYBERBLADEi1) ||
108 (id == CYBERBLADEi1D) ||
109 (id == CYBERBLADEAi1) ||
110 (id == CYBERBLADEAi1D);
111 }
112
113 static inline int is_xp(int id)
114 {
115 return (id == CYBERBLADEXPAi1) ||
116 (id == CYBERBLADEXPm8) ||
117 (id == CYBERBLADEXPm16);
118 }
119
120 static inline int is3Dchip(int id)
121 {
122 return is_blade(id) || is_xp(id) ||
123 (id == CYBER9397) || (id == CYBER9397DVD) ||
124 (id == CYBER9520) || (id == CYBER9525DVD) ||
125 (id == IMAGE975) || (id == IMAGE985);
126 }
127
128 static inline int iscyber(int id)
129 {
130 switch (id) {
131 case CYBER9388:
132 case CYBER9382:
133 case CYBER9385:
134 case CYBER9397:
135 case CYBER9397DVD:
136 case CYBER9520:
137 case CYBER9525DVD:
138 case CYBERBLADEE4:
139 case CYBERBLADEi7D:
140 case CYBERBLADEi1:
141 case CYBERBLADEi1D:
142 case CYBERBLADEAi1:
143 case CYBERBLADEAi1D:
144 case CYBERBLADEXPAi1:
145 return 1;
146
147 case CYBER9320:
148 case CYBERBLADEi7: /* VIA MPV4 integrated version */
149 default:
150 /* case CYBERBLDAEXPm8: Strange */
151 /* case CYBERBLDAEXPm16: Strange */
152 return 0;
153 }
154 }
155
156 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
157 {
158 fb_writeb(val, p->io_virt + reg);
159 }
160
161 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
162 {
163 return fb_readb(p->io_virt + reg);
164 }
165
166 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
167 {
168 fb_writel(v, par->io_virt + r);
169 }
170
171 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
172 {
173 return fb_readl(par->io_virt + r);
174 }
175
176 /*
177 * Blade specific acceleration.
178 */
179
180 #define point(x, y) ((y) << 16 | (x))
181
182 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
183 {
184 int v1 = (pitch >> 3) << 20;
185 int tmp = bpp == 24 ? 2 : (bpp >> 4);
186 int v2 = v1 | (tmp << 29);
187
188 writemmr(par, 0x21C0, v2);
189 writemmr(par, 0x21C4, v2);
190 writemmr(par, 0x21B8, v2);
191 writemmr(par, 0x21BC, v2);
192 writemmr(par, 0x21D0, v1);
193 writemmr(par, 0x21D4, v1);
194 writemmr(par, 0x21C8, v1);
195 writemmr(par, 0x21CC, v1);
196 writemmr(par, 0x216C, 0);
197 }
198
199 static void blade_wait_engine(struct tridentfb_par *par)
200 {
201 while (readmmr(par, STATUS) & 0xFA800000)
202 cpu_relax();
203 }
204
205 static void blade_fill_rect(struct tridentfb_par *par,
206 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
207 {
208 writemmr(par, COLOR, c);
209 writemmr(par, ROP, rop ? ROP_X : ROP_S);
210 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
211
212 writemmr(par, DST1, point(x, y));
213 writemmr(par, DST2, point(x + w - 1, y + h - 1));
214 }
215
216 static void blade_image_blit(struct tridentfb_par *par, const char *data,
217 u32 x, u32 y, u32 w, u32 h, u32 c, u32 b)
218 {
219 unsigned size = ((w + 31) >> 5) * h;
220
221 writemmr(par, COLOR, c);
222 writemmr(par, BGCOLOR, b);
223 writemmr(par, CMD, 0xa0000000 | 3 << 19);
224
225 writemmr(par, DST1, point(x, y));
226 writemmr(par, DST2, point(x + w - 1, y + h - 1));
227
228 memcpy(par->io_virt + 0x10000, data, 4 * size);
229 }
230
231 static void blade_copy_rect(struct tridentfb_par *par,
232 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
233 {
234 int direction = 2;
235 u32 s1 = point(x1, y1);
236 u32 s2 = point(x1 + w - 1, y1 + h - 1);
237 u32 d1 = point(x2, y2);
238 u32 d2 = point(x2 + w - 1, y2 + h - 1);
239
240 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
241 direction = 0;
242
243 writemmr(par, ROP, ROP_S);
244 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
245
246 writemmr(par, SRC1, direction ? s2 : s1);
247 writemmr(par, SRC2, direction ? s1 : s2);
248 writemmr(par, DST1, direction ? d2 : d1);
249 writemmr(par, DST2, direction ? d1 : d2);
250 }
251
252 /*
253 * BladeXP specific acceleration functions
254 */
255
256 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
257 {
258 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
259 int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
260
261 switch (pitch << (bpp >> 3)) {
262 case 8192:
263 case 512:
264 x |= 0x00;
265 break;
266 case 1024:
267 x |= 0x04;
268 break;
269 case 2048:
270 x |= 0x08;
271 break;
272 case 4096:
273 x |= 0x0C;
274 break;
275 }
276
277 t_outb(par, x, 0x2125);
278
279 par->eng_oper = x | 0x40;
280
281 writemmr(par, 0x2154, v1);
282 writemmr(par, 0x2150, v1);
283 t_outb(par, 3, 0x2126);
284 }
285
286 static void xp_wait_engine(struct tridentfb_par *par)
287 {
288 int count = 0;
289 int timeout = 0;
290
291 while (t_inb(par, STATUS) & 0x80) {
292 count++;
293 if (count == 10000000) {
294 /* Timeout */
295 count = 9990000;
296 timeout++;
297 if (timeout == 8) {
298 /* Reset engine */
299 t_outb(par, 0x00, STATUS);
300 return;
301 }
302 }
303 cpu_relax();
304 }
305 }
306
307 static void xp_fill_rect(struct tridentfb_par *par,
308 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
309 {
310 writemmr(par, 0x2127, ROP_P);
311 writemmr(par, 0x2158, c);
312 writemmr(par, DRAWFL, 0x4000);
313 writemmr(par, OLDDIM, point(h, w));
314 writemmr(par, OLDDST, point(y, x));
315 t_outb(par, 0x01, OLDCMD);
316 t_outb(par, par->eng_oper, 0x2125);
317 }
318
319 static void xp_copy_rect(struct tridentfb_par *par,
320 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
321 {
322 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
323 int direction = 0x0004;
324
325 if ((x1 < x2) && (y1 == y2)) {
326 direction |= 0x0200;
327 x1_tmp = x1 + w - 1;
328 x2_tmp = x2 + w - 1;
329 } else {
330 x1_tmp = x1;
331 x2_tmp = x2;
332 }
333
334 if (y1 < y2) {
335 direction |= 0x0100;
336 y1_tmp = y1 + h - 1;
337 y2_tmp = y2 + h - 1;
338 } else {
339 y1_tmp = y1;
340 y2_tmp = y2;
341 }
342
343 writemmr(par, DRAWFL, direction);
344 t_outb(par, ROP_S, 0x2127);
345 writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
346 writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
347 writemmr(par, OLDDIM, point(h, w));
348 t_outb(par, 0x01, OLDCMD);
349 }
350
351 /*
352 * Image specific acceleration functions
353 */
354 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
355 {
356 int tmp = bpp == 24 ? 2: (bpp >> 4);
357
358 writemmr(par, 0x2120, 0xF0000000);
359 writemmr(par, 0x2120, 0x40000000 | tmp);
360 writemmr(par, 0x2120, 0x80000000);
361 writemmr(par, 0x2144, 0x00000000);
362 writemmr(par, 0x2148, 0x00000000);
363 writemmr(par, 0x2150, 0x00000000);
364 writemmr(par, 0x2154, 0x00000000);
365 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
366 writemmr(par, 0x216C, 0x00000000);
367 writemmr(par, 0x2170, 0x00000000);
368 writemmr(par, 0x217C, 0x00000000);
369 writemmr(par, 0x2120, 0x10000000);
370 writemmr(par, 0x2130, (2047 << 16) | 2047);
371 }
372
373 static void image_wait_engine(struct tridentfb_par *par)
374 {
375 while (readmmr(par, 0x2164) & 0xF0000000)
376 cpu_relax();
377 }
378
379 static void image_fill_rect(struct tridentfb_par *par,
380 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
381 {
382 writemmr(par, 0x2120, 0x80000000);
383 writemmr(par, 0x2120, 0x90000000 | ROP_S);
384
385 writemmr(par, 0x2144, c);
386
387 writemmr(par, DST1, point(x, y));
388 writemmr(par, DST2, point(x + w - 1, y + h - 1));
389
390 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
391 }
392
393 static void image_copy_rect(struct tridentfb_par *par,
394 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
395 {
396 int direction = 0x4;
397 u32 s1 = point(x1, y1);
398 u32 s2 = point(x1 + w - 1, y1 + h - 1);
399 u32 d1 = point(x2, y2);
400 u32 d2 = point(x2 + w - 1, y2 + h - 1);
401
402 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
403 direction = 0;
404
405 writemmr(par, 0x2120, 0x80000000);
406 writemmr(par, 0x2120, 0x90000000 | ROP_S);
407
408 writemmr(par, SRC1, direction ? s2 : s1);
409 writemmr(par, SRC2, direction ? s1 : s2);
410 writemmr(par, DST1, direction ? d2 : d1);
411 writemmr(par, DST2, direction ? d1 : d2);
412 writemmr(par, 0x2124,
413 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
414 }
415
416 /*
417 * TGUI 9440/96XX acceleration
418 */
419
420 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
421 {
422 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
423
424 /* disable clipping */
425 writemmr(par, 0x2148, 0);
426 writemmr(par, 0x214C, point(4095, 2047));
427
428 switch ((pitch * bpp) / 8) {
429 case 8192:
430 case 512:
431 x |= 0x00;
432 break;
433 case 1024:
434 x |= 0x04;
435 break;
436 case 2048:
437 x |= 0x08;
438 break;
439 case 4096:
440 x |= 0x0C;
441 break;
442 }
443
444 fb_writew(x, par->io_virt + 0x2122);
445 }
446
447 static void tgui_fill_rect(struct tridentfb_par *par,
448 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
449 {
450 t_outb(par, ROP_P, 0x2127);
451 writemmr(par, OLDCLR, c);
452 writemmr(par, DRAWFL, 0x4020);
453 writemmr(par, OLDDIM, point(w - 1, h - 1));
454 writemmr(par, OLDDST, point(x, y));
455 t_outb(par, 1, OLDCMD);
456 }
457
458 static void tgui_copy_rect(struct tridentfb_par *par,
459 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
460 {
461 int flags = 0;
462 u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
463
464 if ((x1 < x2) && (y1 == y2)) {
465 flags |= 0x0200;
466 x1_tmp = x1 + w - 1;
467 x2_tmp = x2 + w - 1;
468 } else {
469 x1_tmp = x1;
470 x2_tmp = x2;
471 }
472
473 if (y1 < y2) {
474 flags |= 0x0100;
475 y1_tmp = y1 + h - 1;
476 y2_tmp = y2 + h - 1;
477 } else {
478 y1_tmp = y1;
479 y2_tmp = y2;
480 }
481
482 writemmr(par, DRAWFL, 0x4 | flags);
483 t_outb(par, ROP_S, 0x2127);
484 writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
485 writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
486 writemmr(par, OLDDIM, point(w - 1, h - 1));
487 t_outb(par, 1, OLDCMD);
488 }
489
490 /*
491 * Accel functions called by the upper layers
492 */
493 #ifdef CONFIG_FB_TRIDENT_ACCEL
494 static void tridentfb_fillrect(struct fb_info *info,
495 const struct fb_fillrect *fr)
496 {
497 struct tridentfb_par *par = info->par;
498 int col;
499
500 if (info->flags & FBINFO_HWACCEL_DISABLED) {
501 cfb_fillrect(info, fr);
502 return;
503 }
504 if (info->var.bits_per_pixel == 8) {
505 col = fr->color;
506 col |= col << 8;
507 col |= col << 16;
508 } else
509 col = ((u32 *)(info->pseudo_palette))[fr->color];
510
511 par->wait_engine(par);
512 par->fill_rect(par, fr->dx, fr->dy, fr->width,
513 fr->height, col, fr->rop);
514 }
515
516 static void tridentfb_imageblit(struct fb_info *info,
517 const struct fb_image *img)
518 {
519 struct tridentfb_par *par = info->par;
520 int col, bgcol;
521
522 if ((info->flags & FBINFO_HWACCEL_DISABLED) || img->depth != 1) {
523 cfb_imageblit(info, img);
524 return;
525 }
526 if (info->var.bits_per_pixel == 8) {
527 col = img->fg_color;
528 col |= col << 8;
529 col |= col << 16;
530 bgcol = img->bg_color;
531 bgcol |= bgcol << 8;
532 bgcol |= bgcol << 16;
533 } else {
534 col = ((u32 *)(info->pseudo_palette))[img->fg_color];
535 bgcol = ((u32 *)(info->pseudo_palette))[img->bg_color];
536 }
537
538 par->wait_engine(par);
539 if (par->image_blit)
540 par->image_blit(par, img->data, img->dx, img->dy,
541 img->width, img->height, col, bgcol);
542 else
543 cfb_imageblit(info, img);
544 }
545
546 static void tridentfb_copyarea(struct fb_info *info,
547 const struct fb_copyarea *ca)
548 {
549 struct tridentfb_par *par = info->par;
550
551 if (info->flags & FBINFO_HWACCEL_DISABLED) {
552 cfb_copyarea(info, ca);
553 return;
554 }
555 par->wait_engine(par);
556 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
557 ca->width, ca->height);
558 }
559
560 static int tridentfb_sync(struct fb_info *info)
561 {
562 struct tridentfb_par *par = info->par;
563
564 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
565 par->wait_engine(par);
566 return 0;
567 }
568 #else
569 #define tridentfb_fillrect cfb_fillrect
570 #define tridentfb_copyarea cfb_copyarea
571 #define tridentfb_imageblit cfb_imageblit
572 #endif /* CONFIG_FB_TRIDENT_ACCEL */
573
574 /*
575 * Hardware access functions
576 */
577
578 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
579 {
580 return vga_mm_rcrt(par->io_virt, reg);
581 }
582
583 static inline void write3X4(struct tridentfb_par *par, int reg,
584 unsigned char val)
585 {
586 vga_mm_wcrt(par->io_virt, reg, val);
587 }
588
589 static inline unsigned char read3CE(struct tridentfb_par *par,
590 unsigned char reg)
591 {
592 return vga_mm_rgfx(par->io_virt, reg);
593 }
594
595 static inline void writeAttr(struct tridentfb_par *par, int reg,
596 unsigned char val)
597 {
598 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
599 vga_mm_wattr(par->io_virt, reg, val);
600 }
601
602 static inline void write3CE(struct tridentfb_par *par, int reg,
603 unsigned char val)
604 {
605 vga_mm_wgfx(par->io_virt, reg, val);
606 }
607
608 static void enable_mmio(struct tridentfb_par *par)
609 {
610 /* Goto New Mode */
611 vga_io_rseq(0x0B);
612
613 /* Unprotect registers */
614 vga_io_wseq(NewMode1, 0x80);
615 if (!is_oldprotect(par->chip_id))
616 vga_io_wseq(Protection, 0x92);
617
618 /* Enable MMIO */
619 outb(PCIReg, 0x3D4);
620 outb(inb(0x3D5) | 0x01, 0x3D5);
621 }
622
623 static void disable_mmio(struct tridentfb_par *par)
624 {
625 /* Goto New Mode */
626 vga_mm_rseq(par->io_virt, 0x0B);
627
628 /* Unprotect registers */
629 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
630 if (!is_oldprotect(par->chip_id))
631 vga_mm_wseq(par->io_virt, Protection, 0x92);
632
633 /* Disable MMIO */
634 t_outb(par, PCIReg, 0x3D4);
635 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
636 }
637
638 static inline void crtc_unlock(struct tridentfb_par *par)
639 {
640 write3X4(par, VGA_CRTC_V_SYNC_END,
641 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
642 }
643
644 /* Return flat panel's maximum x resolution */
645 static int __devinit get_nativex(struct tridentfb_par *par)
646 {
647 int x, y, tmp;
648
649 if (nativex)
650 return nativex;
651
652 tmp = (read3CE(par, VertStretch) >> 4) & 3;
653
654 switch (tmp) {
655 case 0:
656 x = 1280; y = 1024;
657 break;
658 case 2:
659 x = 1024; y = 768;
660 break;
661 case 3:
662 x = 800; y = 600;
663 break;
664 case 4:
665 x = 1400; y = 1050;
666 break;
667 case 1:
668 default:
669 x = 640; y = 480;
670 break;
671 }
672
673 output("%dx%d flat panel found\n", x, y);
674 return x;
675 }
676
677 /* Set pitch */
678 static inline void set_lwidth(struct tridentfb_par *par, int width)
679 {
680 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
681 write3X4(par, AddColReg,
682 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
683 }
684
685 /* For resolutions smaller than FP resolution stretch */
686 static void screen_stretch(struct tridentfb_par *par)
687 {
688 if (par->chip_id != CYBERBLADEXPAi1)
689 write3CE(par, BiosReg, 0);
690 else
691 write3CE(par, BiosReg, 8);
692 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
693 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
694 }
695
696 /* For resolutions smaller than FP resolution center */
697 static inline void screen_center(struct tridentfb_par *par)
698 {
699 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
700 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
701 }
702
703 /* Address of first shown pixel in display memory */
704 static void set_screen_start(struct tridentfb_par *par, int base)
705 {
706 u8 tmp;
707 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
708 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
709 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
710 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
711 tmp = read3X4(par, CRTHiOrd) & 0xF8;
712 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
713 }
714
715 /* Set dotclock frequency */
716 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
717 {
718 int m, n, k;
719 unsigned long fi, d, di;
720 unsigned char best_m = 0, best_n = 0, best_k = 0;
721 unsigned char hi, lo;
722 unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1;
723
724 d = 20000;
725 for (k = shift; k >= 0; k--)
726 for (m = 1; m < 32; m++) {
727 n = ((m + 2) << shift) - 8;
728 for (n = (n < 0 ? 0 : n); n < 122; n++) {
729 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
730 di = abs(fi - freq);
731 if (di < d || (di == d && k == best_k)) {
732 d = di;
733 best_n = n;
734 best_m = m;
735 best_k = k;
736 }
737 if (fi > freq)
738 break;
739 }
740 }
741
742 if (is_oldclock(par->chip_id)) {
743 lo = best_n | (best_m << 7);
744 hi = (best_m >> 1) | (best_k << 4);
745 } else {
746 lo = best_n;
747 hi = best_m | (best_k << 6);
748 }
749
750 if (is3Dchip(par->chip_id)) {
751 vga_mm_wseq(par->io_virt, ClockHigh, hi);
752 vga_mm_wseq(par->io_virt, ClockLow, lo);
753 } else {
754 t_outb(par, lo, 0x43C8);
755 t_outb(par, hi, 0x43C9);
756 }
757 debug("VCLK = %X %X\n", hi, lo);
758 }
759
760 /* Set number of lines for flat panels*/
761 static void set_number_of_lines(struct tridentfb_par *par, int lines)
762 {
763 int tmp = read3CE(par, CyberEnhance) & 0x8F;
764 if (lines > 1024)
765 tmp |= 0x50;
766 else if (lines > 768)
767 tmp |= 0x30;
768 else if (lines > 600)
769 tmp |= 0x20;
770 else if (lines > 480)
771 tmp |= 0x10;
772 write3CE(par, CyberEnhance, tmp);
773 }
774
775 /*
776 * If we see that FP is active we assume we have one.
777 * Otherwise we have a CRT display. User can override.
778 */
779 static int __devinit is_flatpanel(struct tridentfb_par *par)
780 {
781 if (fp)
782 return 1;
783 if (crt || !iscyber(par->chip_id))
784 return 0;
785 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
786 }
787
788 /* Try detecting the video memory size */
789 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
790 {
791 unsigned char tmp, tmp2;
792 unsigned int k;
793
794 /* If memory size provided by user */
795 if (memsize)
796 k = memsize * Kb;
797 else
798 switch (par->chip_id) {
799 case CYBER9525DVD:
800 k = 2560 * Kb;
801 break;
802 default:
803 tmp = read3X4(par, SPR) & 0x0F;
804 switch (tmp) {
805
806 case 0x01:
807 k = 512 * Kb;
808 break;
809 case 0x02:
810 k = 6 * Mb; /* XP */
811 break;
812 case 0x03:
813 k = 1 * Mb;
814 break;
815 case 0x04:
816 k = 8 * Mb;
817 break;
818 case 0x06:
819 k = 10 * Mb; /* XP */
820 break;
821 case 0x07:
822 k = 2 * Mb;
823 break;
824 case 0x08:
825 k = 12 * Mb; /* XP */
826 break;
827 case 0x0A:
828 k = 14 * Mb; /* XP */
829 break;
830 case 0x0C:
831 k = 16 * Mb; /* XP */
832 break;
833 case 0x0E: /* XP */
834
835 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
836 switch (tmp2) {
837 case 0x00:
838 k = 20 * Mb;
839 break;
840 case 0x01:
841 k = 24 * Mb;
842 break;
843 case 0x10:
844 k = 28 * Mb;
845 break;
846 case 0x11:
847 k = 32 * Mb;
848 break;
849 default:
850 k = 1 * Mb;
851 break;
852 }
853 break;
854
855 case 0x0F:
856 k = 4 * Mb;
857 break;
858 default:
859 k = 1 * Mb;
860 break;
861 }
862 }
863
864 k -= memdiff * Kb;
865 output("framebuffer size = %d Kb\n", k / Kb);
866 return k;
867 }
868
869 /* See if we can handle the video mode described in var */
870 static int tridentfb_check_var(struct fb_var_screeninfo *var,
871 struct fb_info *info)
872 {
873 struct tridentfb_par *par = info->par;
874 int bpp = var->bits_per_pixel;
875 int line_length;
876 int ramdac = 230000; /* 230MHz for most 3D chips */
877 debug("enter\n");
878
879 /* check color depth */
880 if (bpp == 24)
881 bpp = var->bits_per_pixel = 32;
882 if (bpp != 8 && bpp != 16 && bpp != 32)
883 return -EINVAL;
884 if (par->chip_id == TGUI9440 && bpp == 32)
885 return -EINVAL;
886 /* check whether resolution fits on panel and in memory */
887 if (par->flatpanel && nativex && var->xres > nativex)
888 return -EINVAL;
889 /* various resolution checks */
890 var->xres = (var->xres + 7) & ~0x7;
891 if (var->xres > var->xres_virtual)
892 var->xres_virtual = var->xres;
893 if (var->yres > var->yres_virtual)
894 var->yres_virtual = var->yres;
895 if (var->xres_virtual > 4095 || var->yres > 2048)
896 return -EINVAL;
897 /* prevent from position overflow for acceleration */
898 if (var->yres_virtual > 0xffff)
899 return -EINVAL;
900 line_length = var->xres_virtual * bpp / 8;
901
902 if (!is3Dchip(par->chip_id) &&
903 !(info->flags & FBINFO_HWACCEL_DISABLED)) {
904 /* acceleration requires line length to be power of 2 */
905 if (line_length <= 512)
906 var->xres_virtual = 512 * 8 / bpp;
907 else if (line_length <= 1024)
908 var->xres_virtual = 1024 * 8 / bpp;
909 else if (line_length <= 2048)
910 var->xres_virtual = 2048 * 8 / bpp;
911 else if (line_length <= 4096)
912 var->xres_virtual = 4096 * 8 / bpp;
913 else if (line_length <= 8192)
914 var->xres_virtual = 8192 * 8 / bpp;
915 else
916 return -EINVAL;
917
918 line_length = var->xres_virtual * bpp / 8;
919 }
920
921 /* datasheet specifies how to set panning only up to 4 MB */
922 if (line_length * (var->yres_virtual - var->yres) > (4 << 20))
923 var->yres_virtual = ((4 << 20) / line_length) + var->yres;
924
925 if (line_length * var->yres_virtual > info->fix.smem_len)
926 return -EINVAL;
927
928 switch (bpp) {
929 case 8:
930 var->red.offset = 0;
931 var->red.length = 8;
932 var->green = var->red;
933 var->blue = var->red;
934 break;
935 case 16:
936 var->red.offset = 11;
937 var->green.offset = 5;
938 var->blue.offset = 0;
939 var->red.length = 5;
940 var->green.length = 6;
941 var->blue.length = 5;
942 break;
943 case 32:
944 var->red.offset = 16;
945 var->green.offset = 8;
946 var->blue.offset = 0;
947 var->red.length = 8;
948 var->green.length = 8;
949 var->blue.length = 8;
950 break;
951 default:
952 return -EINVAL;
953 }
954
955 if (is_xp(par->chip_id))
956 ramdac = 350000;
957
958 switch (par->chip_id) {
959 case TGUI9440:
960 ramdac = (bpp >= 16) ? 45000 : 90000;
961 break;
962 case CYBER9320:
963 case TGUI9660:
964 ramdac = 135000;
965 break;
966 case PROVIDIA9685:
967 case CYBER9388:
968 case CYBER9382:
969 case CYBER9385:
970 ramdac = 170000;
971 break;
972 }
973
974 /* The clock is doubled for 32 bpp */
975 if (bpp == 32)
976 ramdac /= 2;
977
978 if (PICOS2KHZ(var->pixclock) > ramdac)
979 return -EINVAL;
980
981 debug("exit\n");
982
983 return 0;
984
985 }
986
987 /* Pan the display */
988 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
989 struct fb_info *info)
990 {
991 struct tridentfb_par *par = info->par;
992 unsigned int offset;
993
994 debug("enter\n");
995 offset = (var->xoffset + (var->yoffset * var->xres_virtual))
996 * var->bits_per_pixel / 32;
997 set_screen_start(par, offset);
998 debug("exit\n");
999 return 0;
1000 }
1001
1002 static inline void shadowmode_on(struct tridentfb_par *par)
1003 {
1004 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
1005 }
1006
1007 static inline void shadowmode_off(struct tridentfb_par *par)
1008 {
1009 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
1010 }
1011
1012 /* Set the hardware to the requested video mode */
1013 static int tridentfb_set_par(struct fb_info *info)
1014 {
1015 struct tridentfb_par *par = info->par;
1016 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
1017 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
1018 struct fb_var_screeninfo *var = &info->var;
1019 int bpp = var->bits_per_pixel;
1020 unsigned char tmp;
1021 unsigned long vclk;
1022
1023 debug("enter\n");
1024 hdispend = var->xres / 8 - 1;
1025 hsyncstart = (var->xres + var->right_margin) / 8;
1026 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
1027 htotal = (var->xres + var->left_margin + var->right_margin +
1028 var->hsync_len) / 8 - 5;
1029 hblankstart = hdispend + 1;
1030 hblankend = htotal + 3;
1031
1032 vdispend = var->yres - 1;
1033 vsyncstart = var->yres + var->lower_margin;
1034 vsyncend = vsyncstart + var->vsync_len;
1035 vtotal = var->upper_margin + vsyncend - 2;
1036 vblankstart = vdispend + 1;
1037 vblankend = vtotal;
1038
1039 if (info->var.vmode & FB_VMODE_INTERLACED) {
1040 vtotal /= 2;
1041 vdispend /= 2;
1042 vsyncstart /= 2;
1043 vsyncend /= 2;
1044 vblankstart /= 2;
1045 vblankend /= 2;
1046 }
1047
1048 enable_mmio(par);
1049 crtc_unlock(par);
1050 write3CE(par, CyberControl, 8);
1051 tmp = 0xEB;
1052 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1053 tmp &= ~0x40;
1054 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1055 tmp &= ~0x80;
1056
1057 if (par->flatpanel && var->xres < nativex) {
1058 /*
1059 * on flat panels with native size larger
1060 * than requested resolution decide whether
1061 * we stretch or center
1062 */
1063 t_outb(par, tmp | 0xC0, VGA_MIS_W);
1064
1065 shadowmode_on(par);
1066
1067 if (center)
1068 screen_center(par);
1069 else if (stretch)
1070 screen_stretch(par);
1071
1072 } else {
1073 t_outb(par, tmp, VGA_MIS_W);
1074 write3CE(par, CyberControl, 8);
1075 }
1076
1077 /* vertical timing values */
1078 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1079 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1080 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1081 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1082 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1083 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1084
1085 /* horizontal timing values */
1086 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1087 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1088 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1089 write3X4(par, VGA_CRTC_H_SYNC_END,
1090 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1091 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1092 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1093
1094 /* higher bits of vertical timing values */
1095 tmp = 0x10;
1096 if (vtotal & 0x100) tmp |= 0x01;
1097 if (vdispend & 0x100) tmp |= 0x02;
1098 if (vsyncstart & 0x100) tmp |= 0x04;
1099 if (vblankstart & 0x100) tmp |= 0x08;
1100
1101 if (vtotal & 0x200) tmp |= 0x20;
1102 if (vdispend & 0x200) tmp |= 0x40;
1103 if (vsyncstart & 0x200) tmp |= 0x80;
1104 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1105
1106 tmp = read3X4(par, CRTHiOrd) & 0x07;
1107 tmp |= 0x08; /* line compare bit 10 */
1108 if (vtotal & 0x400) tmp |= 0x80;
1109 if (vblankstart & 0x400) tmp |= 0x40;
1110 if (vsyncstart & 0x400) tmp |= 0x20;
1111 if (vdispend & 0x400) tmp |= 0x10;
1112 write3X4(par, CRTHiOrd, tmp);
1113
1114 tmp = (htotal >> 8) & 0x01;
1115 tmp |= (hdispend >> 7) & 0x02;
1116 tmp |= (hsyncstart >> 5) & 0x08;
1117 tmp |= (hblankstart >> 4) & 0x10;
1118 write3X4(par, HorizOverflow, tmp);
1119
1120 tmp = 0x40;
1121 if (vblankstart & 0x200) tmp |= 0x20;
1122 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1123 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1124
1125 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1126 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1127 write3X4(par, VGA_CRTC_MODE, 0xC3);
1128
1129 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1130
1131 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1132 /* enable access extended memory */
1133 write3X4(par, CRTCModuleTest, tmp);
1134 tmp = read3CE(par, MiscIntContReg) & ~0x4;
1135 if (info->var.vmode & FB_VMODE_INTERLACED)
1136 tmp |= 0x4;
1137 write3CE(par, MiscIntContReg, tmp);
1138
1139 /* enable GE for text acceleration */
1140 write3X4(par, GraphEngReg, 0x80);
1141
1142 switch (bpp) {
1143 case 8:
1144 tmp = 0x00;
1145 break;
1146 case 16:
1147 tmp = 0x05;
1148 break;
1149 case 24:
1150 tmp = 0x29;
1151 break;
1152 case 32:
1153 tmp = 0x09;
1154 break;
1155 }
1156
1157 write3X4(par, PixelBusReg, tmp);
1158
1159 tmp = read3X4(par, DRAMControl);
1160 if (!is_oldprotect(par->chip_id))
1161 tmp |= 0x10;
1162 if (iscyber(par->chip_id))
1163 tmp |= 0x20;
1164 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1165
1166 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1167 if (!is_xp(par->chip_id))
1168 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1169 /* MMIO & PCI read and write burst enable */
1170 if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975)
1171 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1172
1173 vga_mm_wseq(par->io_virt, 0, 3);
1174 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1175 /* enable 4 maps because needed in chain4 mode */
1176 vga_mm_wseq(par->io_virt, 2, 0x0F);
1177 vga_mm_wseq(par->io_virt, 3, 0);
1178 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1179
1180 /* convert from picoseconds to kHz */
1181 vclk = PICOS2KHZ(info->var.pixclock);
1182
1183 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1184 tmp = read3CE(par, MiscExtFunc) & 0xF0;
1185 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1186 tmp |= 8;
1187 vclk *= 2;
1188 }
1189 set_vclk(par, vclk);
1190 write3CE(par, MiscExtFunc, tmp | 0x12);
1191 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1192 write3CE(par, 0x6, 0x05); /* graphics mode */
1193 write3CE(par, 0x7, 0x0F); /* planes? */
1194
1195 /* graphics mode and support 256 color modes */
1196 writeAttr(par, 0x10, 0x41);
1197 writeAttr(par, 0x12, 0x0F); /* planes */
1198 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1199
1200 /* colors */
1201 for (tmp = 0; tmp < 0x10; tmp++)
1202 writeAttr(par, tmp, tmp);
1203 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1204 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1205
1206 switch (bpp) {
1207 case 8:
1208 tmp = 0;
1209 break;
1210 case 16:
1211 tmp = 0x30;
1212 break;
1213 case 24:
1214 case 32:
1215 tmp = 0xD0;
1216 break;
1217 }
1218
1219 t_inb(par, VGA_PEL_IW);
1220 t_inb(par, VGA_PEL_MSK);
1221 t_inb(par, VGA_PEL_MSK);
1222 t_inb(par, VGA_PEL_MSK);
1223 t_inb(par, VGA_PEL_MSK);
1224 t_outb(par, tmp, VGA_PEL_MSK);
1225 t_inb(par, VGA_PEL_IW);
1226
1227 if (par->flatpanel)
1228 set_number_of_lines(par, info->var.yres);
1229 info->fix.line_length = info->var.xres_virtual * bpp / 8;
1230 set_lwidth(par, info->fix.line_length / 8);
1231
1232 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1233 par->init_accel(par, info->var.xres_virtual, bpp);
1234
1235 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1236 info->cmap.len = (bpp == 8) ? 256 : 16;
1237 debug("exit\n");
1238 return 0;
1239 }
1240
1241 /* Set one color register */
1242 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1243 unsigned blue, unsigned transp,
1244 struct fb_info *info)
1245 {
1246 int bpp = info->var.bits_per_pixel;
1247 struct tridentfb_par *par = info->par;
1248
1249 if (regno >= info->cmap.len)
1250 return 1;
1251
1252 if (bpp == 8) {
1253 t_outb(par, 0xFF, VGA_PEL_MSK);
1254 t_outb(par, regno, VGA_PEL_IW);
1255
1256 t_outb(par, red >> 10, VGA_PEL_D);
1257 t_outb(par, green >> 10, VGA_PEL_D);
1258 t_outb(par, blue >> 10, VGA_PEL_D);
1259
1260 } else if (regno < 16) {
1261 if (bpp == 16) { /* RGB 565 */
1262 u32 col;
1263
1264 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1265 ((blue & 0xF800) >> 11);
1266 col |= col << 16;
1267 ((u32 *)(info->pseudo_palette))[regno] = col;
1268 } else if (bpp == 32) /* ARGB 8888 */
1269 ((u32 *)info->pseudo_palette)[regno] =
1270 ((transp & 0xFF00) << 16) |
1271 ((red & 0xFF00) << 8) |
1272 ((green & 0xFF00)) |
1273 ((blue & 0xFF00) >> 8);
1274 }
1275
1276 return 0;
1277 }
1278
1279 /* Try blanking the screen. For flat panels it does nothing */
1280 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1281 {
1282 unsigned char PMCont, DPMSCont;
1283 struct tridentfb_par *par = info->par;
1284
1285 debug("enter\n");
1286 if (par->flatpanel)
1287 return 0;
1288 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1289 PMCont = t_inb(par, 0x83C6) & 0xFC;
1290 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1291 switch (blank_mode) {
1292 case FB_BLANK_UNBLANK:
1293 /* Screen: On, HSync: On, VSync: On */
1294 case FB_BLANK_NORMAL:
1295 /* Screen: Off, HSync: On, VSync: On */
1296 PMCont |= 0x03;
1297 DPMSCont |= 0x00;
1298 break;
1299 case FB_BLANK_HSYNC_SUSPEND:
1300 /* Screen: Off, HSync: Off, VSync: On */
1301 PMCont |= 0x02;
1302 DPMSCont |= 0x01;
1303 break;
1304 case FB_BLANK_VSYNC_SUSPEND:
1305 /* Screen: Off, HSync: On, VSync: Off */
1306 PMCont |= 0x02;
1307 DPMSCont |= 0x02;
1308 break;
1309 case FB_BLANK_POWERDOWN:
1310 /* Screen: Off, HSync: Off, VSync: Off */
1311 PMCont |= 0x00;
1312 DPMSCont |= 0x03;
1313 break;
1314 }
1315
1316 write3CE(par, PowerStatus, DPMSCont);
1317 t_outb(par, 4, 0x83C8);
1318 t_outb(par, PMCont, 0x83C6);
1319
1320 debug("exit\n");
1321
1322 /* let fbcon do a softblank for us */
1323 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1324 }
1325
1326 static struct fb_ops tridentfb_ops = {
1327 .owner = THIS_MODULE,
1328 .fb_setcolreg = tridentfb_setcolreg,
1329 .fb_pan_display = tridentfb_pan_display,
1330 .fb_blank = tridentfb_blank,
1331 .fb_check_var = tridentfb_check_var,
1332 .fb_set_par = tridentfb_set_par,
1333 .fb_fillrect = tridentfb_fillrect,
1334 .fb_copyarea = tridentfb_copyarea,
1335 .fb_imageblit = tridentfb_imageblit,
1336 #ifdef CONFIG_FB_TRIDENT_ACCEL
1337 .fb_sync = tridentfb_sync,
1338 #endif
1339 };
1340
1341 static int __devinit trident_pci_probe(struct pci_dev *dev,
1342 const struct pci_device_id *id)
1343 {
1344 int err;
1345 unsigned char revision;
1346 struct fb_info *info;
1347 struct tridentfb_par *default_par;
1348 int chip3D;
1349 int chip_id;
1350
1351 err = pci_enable_device(dev);
1352 if (err)
1353 return err;
1354
1355 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1356 if (!info)
1357 return -ENOMEM;
1358 default_par = info->par;
1359
1360 chip_id = id->device;
1361
1362 #ifndef CONFIG_FB_TRIDENT_ACCEL
1363 noaccel = 1;
1364 #endif
1365
1366 /* If PCI id is 0x9660 then further detect chip type */
1367
1368 if (chip_id == TGUI9660) {
1369 revision = vga_io_rseq(RevisionID);
1370
1371 switch (revision) {
1372 case 0x21:
1373 chip_id = PROVIDIA9685;
1374 break;
1375 case 0x22:
1376 case 0x23:
1377 chip_id = CYBER9397;
1378 break;
1379 case 0x2A:
1380 chip_id = CYBER9397DVD;
1381 break;
1382 case 0x30:
1383 case 0x33:
1384 case 0x34:
1385 case 0x35:
1386 case 0x38:
1387 case 0x3A:
1388 case 0xB3:
1389 chip_id = CYBER9385;
1390 break;
1391 case 0x40 ... 0x43:
1392 chip_id = CYBER9382;
1393 break;
1394 case 0x4A:
1395 chip_id = CYBER9388;
1396 break;
1397 default:
1398 break;
1399 }
1400 }
1401
1402 chip3D = is3Dchip(chip_id);
1403
1404 if (is_xp(chip_id)) {
1405 default_par->init_accel = xp_init_accel;
1406 default_par->wait_engine = xp_wait_engine;
1407 default_par->fill_rect = xp_fill_rect;
1408 default_par->copy_rect = xp_copy_rect;
1409 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP;
1410 } else if (is_blade(chip_id)) {
1411 default_par->init_accel = blade_init_accel;
1412 default_par->wait_engine = blade_wait_engine;
1413 default_par->fill_rect = blade_fill_rect;
1414 default_par->copy_rect = blade_copy_rect;
1415 default_par->image_blit = blade_image_blit;
1416 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D;
1417 } else if (chip3D) { /* 3DImage family left */
1418 default_par->init_accel = image_init_accel;
1419 default_par->wait_engine = image_wait_engine;
1420 default_par->fill_rect = image_fill_rect;
1421 default_par->copy_rect = image_copy_rect;
1422 tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE;
1423 } else { /* TGUI 9440/96XX family */
1424 default_par->init_accel = tgui_init_accel;
1425 default_par->wait_engine = xp_wait_engine;
1426 default_par->fill_rect = tgui_fill_rect;
1427 default_par->copy_rect = tgui_copy_rect;
1428 tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI;
1429 }
1430
1431 default_par->chip_id = chip_id;
1432
1433 /* setup MMIO region */
1434 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1435 tridentfb_fix.mmio_len = pci_resource_len(dev, 1);
1436
1437 if (!request_mem_region(tridentfb_fix.mmio_start,
1438 tridentfb_fix.mmio_len, "tridentfb")) {
1439 debug("request_region failed!\n");
1440 framebuffer_release(info);
1441 return -1;
1442 }
1443
1444 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1445 tridentfb_fix.mmio_len);
1446
1447 if (!default_par->io_virt) {
1448 debug("ioremap failed\n");
1449 err = -1;
1450 goto out_unmap1;
1451 }
1452
1453 enable_mmio(default_par);
1454
1455 /* setup framebuffer memory */
1456 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1457 tridentfb_fix.smem_len = get_memsize(default_par);
1458
1459 if (!request_mem_region(tridentfb_fix.smem_start,
1460 tridentfb_fix.smem_len, "tridentfb")) {
1461 debug("request_mem_region failed!\n");
1462 disable_mmio(info->par);
1463 err = -1;
1464 goto out_unmap1;
1465 }
1466
1467 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1468 tridentfb_fix.smem_len);
1469
1470 if (!info->screen_base) {
1471 debug("ioremap failed\n");
1472 err = -1;
1473 goto out_unmap2;
1474 }
1475
1476 default_par->flatpanel = is_flatpanel(default_par);
1477
1478 if (default_par->flatpanel)
1479 nativex = get_nativex(default_par);
1480
1481 info->fix = tridentfb_fix;
1482 info->fbops = &tridentfb_ops;
1483 info->pseudo_palette = default_par->pseudo_pal;
1484
1485 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1486 if (!noaccel && default_par->init_accel) {
1487 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1488 info->flags |= FBINFO_HWACCEL_COPYAREA;
1489 info->flags |= FBINFO_HWACCEL_FILLRECT;
1490 } else
1491 info->flags |= FBINFO_HWACCEL_DISABLED;
1492
1493 info->pixmap.addr = kmalloc(4096, GFP_KERNEL);
1494 if (!info->pixmap.addr) {
1495 err = -ENOMEM;
1496 goto out_unmap2;
1497 }
1498
1499 info->pixmap.size = 4096;
1500 info->pixmap.buf_align = 4;
1501 info->pixmap.scan_align = 1;
1502 info->pixmap.access_align = 32;
1503 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1504
1505 if (default_par->image_blit) {
1506 info->flags |= FBINFO_HWACCEL_IMAGEBLIT;
1507 info->pixmap.scan_align = 4;
1508 }
1509
1510 if (noaccel) {
1511 printk(KERN_DEBUG "disabling acceleration\n");
1512 info->flags |= FBINFO_HWACCEL_DISABLED;
1513 info->pixmap.scan_align = 1;
1514 }
1515
1516 if (!fb_find_mode(&info->var, info,
1517 mode_option, NULL, 0, NULL, bpp)) {
1518 err = -EINVAL;
1519 goto out_unmap2;
1520 }
1521 err = fb_alloc_cmap(&info->cmap, 256, 0);
1522 if (err < 0)
1523 goto out_unmap2;
1524
1525 info->var.activate |= FB_ACTIVATE_NOW;
1526 info->device = &dev->dev;
1527 if (register_framebuffer(info) < 0) {
1528 printk(KERN_ERR "tridentfb: could not register framebuffer\n");
1529 fb_dealloc_cmap(&info->cmap);
1530 err = -EINVAL;
1531 goto out_unmap2;
1532 }
1533 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1534 info->node, info->fix.id, info->var.xres,
1535 info->var.yres, info->var.bits_per_pixel);
1536
1537 pci_set_drvdata(dev, info);
1538 return 0;
1539
1540 out_unmap2:
1541 kfree(info->pixmap.addr);
1542 if (info->screen_base)
1543 iounmap(info->screen_base);
1544 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1545 disable_mmio(info->par);
1546 out_unmap1:
1547 if (default_par->io_virt)
1548 iounmap(default_par->io_virt);
1549 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1550 framebuffer_release(info);
1551 return err;
1552 }
1553
1554 static void __devexit trident_pci_remove(struct pci_dev *dev)
1555 {
1556 struct fb_info *info = pci_get_drvdata(dev);
1557 struct tridentfb_par *par = info->par;
1558
1559 unregister_framebuffer(info);
1560 iounmap(par->io_virt);
1561 iounmap(info->screen_base);
1562 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1563 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1564 pci_set_drvdata(dev, NULL);
1565 kfree(info->pixmap.addr);
1566 framebuffer_release(info);
1567 }
1568
1569 /* List of boards that we are trying to support */
1570 static struct pci_device_id trident_devices[] = {
1571 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1572 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1573 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1574 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1575 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1576 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1577 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1578 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1579 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1580 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1581 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1582 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1583 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1584 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1585 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1586 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1587 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1588 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1589 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1590 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1591 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1592 {0,}
1593 };
1594
1595 MODULE_DEVICE_TABLE(pci, trident_devices);
1596
1597 static struct pci_driver tridentfb_pci_driver = {
1598 .name = "tridentfb",
1599 .id_table = trident_devices,
1600 .probe = trident_pci_probe,
1601 .remove = __devexit_p(trident_pci_remove)
1602 };
1603
1604 /*
1605 * Parse user specified options (`video=trident:')
1606 * example:
1607 * video=trident:800x600,bpp=16,noaccel
1608 */
1609 #ifndef MODULE
1610 static int __init tridentfb_setup(char *options)
1611 {
1612 char *opt;
1613 if (!options || !*options)
1614 return 0;
1615 while ((opt = strsep(&options, ",")) != NULL) {
1616 if (!*opt)
1617 continue;
1618 if (!strncmp(opt, "noaccel", 7))
1619 noaccel = 1;
1620 else if (!strncmp(opt, "fp", 2))
1621 fp = 1;
1622 else if (!strncmp(opt, "crt", 3))
1623 fp = 0;
1624 else if (!strncmp(opt, "bpp=", 4))
1625 bpp = simple_strtoul(opt + 4, NULL, 0);
1626 else if (!strncmp(opt, "center", 6))
1627 center = 1;
1628 else if (!strncmp(opt, "stretch", 7))
1629 stretch = 1;
1630 else if (!strncmp(opt, "memsize=", 8))
1631 memsize = simple_strtoul(opt + 8, NULL, 0);
1632 else if (!strncmp(opt, "memdiff=", 8))
1633 memdiff = simple_strtoul(opt + 8, NULL, 0);
1634 else if (!strncmp(opt, "nativex=", 8))
1635 nativex = simple_strtoul(opt + 8, NULL, 0);
1636 else
1637 mode_option = opt;
1638 }
1639 return 0;
1640 }
1641 #endif
1642
1643 static int __init tridentfb_init(void)
1644 {
1645 #ifndef MODULE
1646 char *option = NULL;
1647
1648 if (fb_get_options("tridentfb", &option))
1649 return -ENODEV;
1650 tridentfb_setup(option);
1651 #endif
1652 return pci_register_driver(&tridentfb_pci_driver);
1653 }
1654
1655 static void __exit tridentfb_exit(void)
1656 {
1657 pci_unregister_driver(&tridentfb_pci_driver);
1658 }
1659
1660 module_init(tridentfb_init);
1661 module_exit(tridentfb_exit);
1662
1663 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1664 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1665 MODULE_LICENSE("GPL");
1666
Nao low-level kernelspace/userspace library that runs on our robots, Nao-Team HTWK