kernel/2.6.29.6-aldebaran-rt/drivers/net/wireless/iwlwifi/iwl-csr.h

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   4  * redistributing this file, you may do so under either license.
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   8  * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
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  23  *
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  25  * in the file called LICENSE.GPL.
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  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #ifndef __iwl_csr_h__
  64 #define __iwl_csr_h__
  65 /*=== CSR (control and status registers) ===*/
  66 #define CSR_BASE    (0x000)
  67
  68 #define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000) /* hardware interface config */
  69 #define CSR_INT_COALESCING     (CSR_BASE+0x004) /* accum ints, 32-usec units */
  70 #define CSR_INT                 (CSR_BASE+0x008) /* host interrupt status/ack */
  71 #define CSR_INT_MASK            (CSR_BASE+0x00c) /* host interrupt enable */
  72 #define CSR_FH_INT_STATUS       (CSR_BASE+0x010) /* busmaster int status/ack*/
  73 #define CSR_GPIO_IN             (CSR_BASE+0x018) /* read external chip pins */
  74 #define CSR_RESET               (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
  75 #define CSR_GP_CNTRL            (CSR_BASE+0x024)
  76
  77 /*
  78  * Hardware revision info
  79  * Bit fields:
  80  * 31-8:  Reserved
  81  *  7-4:  Type of device:  0x0 = 4965, 0xd = 3945
  82  *  3-2:  Revision step:  0 = A, 1 = B, 2 = C, 3 = D
  83  *  1-0:  "Dash" value, as in A-1, etc.
  84  *
  85  * NOTE:  Revision step affects calculation of CCK txpower for 4965.
  86  */
  87 #define CSR_HW_REV              (CSR_BASE+0x028)
  88
  89 /* EEPROM reads */
  90 #define CSR_EEPROM_REG          (CSR_BASE+0x02c)
  91 #define CSR_EEPROM_GP           (CSR_BASE+0x030)
  92 #define CSR_GIO_REG             (CSR_BASE+0x03C)
  93 #define CSR_GP_UCODE            (CSR_BASE+0x044)
  94 #define CSR_UCODE_DRV_GP1       (CSR_BASE+0x054)
  95 #define CSR_UCODE_DRV_GP1_SET   (CSR_BASE+0x058)
  96 #define CSR_UCODE_DRV_GP1_CLR   (CSR_BASE+0x05c)
  97 #define CSR_UCODE_DRV_GP2       (CSR_BASE+0x060)
  98 #define CSR_LED_REG             (CSR_BASE+0x094)
  99 #define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)
 100
 101 /* Analog phase-lock-loop configuration  */
 102 #define CSR_ANA_PLL_CFG         (CSR_BASE+0x20c)
 103 /*
 104  * Indicates hardware rev, to determine CCK backoff for txpower calculation.
 105  * Bit fields:
 106  *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
 107  */
 108 #define CSR_HW_REV_WA_REG       (CSR_BASE+0x22C)
 109 #define CSR_DBG_HPET_MEM_REG    (CSR_BASE+0x240)
 110
 111 /* Bits for CSR_HW_IF_CONFIG_REG */
 112 #define CSR49_HW_IF_CONFIG_REG_BIT_4965_R       (0x00000010)
 113 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER      (0x00000C00)
 114 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI         (0x00000100)
 115 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI       (0x00000200)
 116
 117 #define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB         (0x00000100)
 118 #define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM         (0x00000200)
 119 #define CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC            (0x00000400)
 120 #define CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE         (0x00000800)
 121 #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A    (0x00000000)
 122 #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B    (0x00001000)
 123
 124 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A           (0x00080000)
 125 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM         (0x00200000)
 126 #define CSR_HW_IF_CONFIG_REG_BIT_PCI_OWN_SEM            (0x00400000)
 127 #define CSR_HW_IF_CONFIG_REG_BIT_ME_OWN                 (0x02000000)
 128 #define CSR_HW_IF_CONFIG_REG_BIT_WAKE_ME                (0x08000000)
 129
 130
 131 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
 132  * acknowledged (reset) by host writing "1" to flagged bits. */
 133 #define CSR_INT_BIT_FH_RX        (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
 134 #define CSR_INT_BIT_HW_ERR       (1 << 29) /* DMA hardware error FH_INT[31] */
 135 #define CSR_INT_BIT_DNLD         (1 << 28) /* uCode Download */
 136 #define CSR_INT_BIT_FH_TX        (1 << 27) /* Tx DMA FH_INT[1:0] */
 137 #define CSR_INT_BIT_SCD          (1 << 26) /* TXQ pointer advanced */
 138 #define CSR_INT_BIT_SW_ERR       (1 << 25) /* uCode error */
 139 #define CSR_INT_BIT_RF_KILL      (1 << 7)  /* HW RFKILL switch GP_CNTRL[27] toggled */
 140 #define CSR_INT_BIT_CT_KILL      (1 << 6)  /* Critical temp (chip too hot) rfkill */
 141 #define CSR_INT_BIT_SW_RX        (1 << 3)  /* Rx, command responses, 3945 */
 142 #define CSR_INT_BIT_WAKEUP       (1 << 1)  /* NIC controller waking up (pwr mgmt) */
 143 #define CSR_INT_BIT_ALIVE        (1 << 0)  /* uCode interrupts once it initializes */
 144
 145 #define CSR_INI_SET_MASK        (CSR_INT_BIT_FH_RX   | \
 146                                  CSR_INT_BIT_HW_ERR  | \
 147                                  CSR_INT_BIT_FH_TX   | \
 148                                  CSR_INT_BIT_SW_ERR  | \
 149                                  CSR_INT_BIT_RF_KILL | \
 150                                  CSR_INT_BIT_SW_RX   | \
 151                                  CSR_INT_BIT_WAKEUP  | \
 152                                  CSR_INT_BIT_ALIVE)
 153
 154 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
 155 #define CSR_FH_INT_BIT_ERR       (1 << 31) /* Error */
 156 #define CSR_FH_INT_BIT_HI_PRIOR  (1 << 30) /* High priority Rx, bypass coalescing */
 157 #define CSR39_FH_INT_BIT_RX_CHNL2  (1 << 18) /* Rx channel 2 (3945 only) */
 158 #define CSR_FH_INT_BIT_RX_CHNL1  (1 << 17) /* Rx channel 1 */
 159 #define CSR_FH_INT_BIT_RX_CHNL0  (1 << 16) /* Rx channel 0 */
 160 #define CSR39_FH_INT_BIT_TX_CHNL6  (1 << 6)  /* Tx channel 6 (3945 only) */
 161 #define CSR_FH_INT_BIT_TX_CHNL1  (1 << 1)  /* Tx channel 1 */
 162 #define CSR_FH_INT_BIT_TX_CHNL0  (1 << 0)  /* Tx channel 0 */
 163
 164 #define CSR39_FH_INT_RX_MASK    (CSR_FH_INT_BIT_HI_PRIOR | \
 165                                  CSR39_FH_INT_BIT_RX_CHNL2 | \
 166                                  CSR_FH_INT_BIT_RX_CHNL1 | \
 167                                  CSR_FH_INT_BIT_RX_CHNL0)
 168
 169
 170 #define CSR39_FH_INT_TX_MASK    (CSR39_FH_INT_BIT_TX_CHNL6 | \
 171                                  CSR_FH_INT_BIT_TX_CHNL1 | \
 172                                  CSR_FH_INT_BIT_TX_CHNL0)
 173
 174 #define CSR49_FH_INT_RX_MASK    (CSR_FH_INT_BIT_HI_PRIOR | \
 175                                  CSR_FH_INT_BIT_RX_CHNL1 | \
 176                                  CSR_FH_INT_BIT_RX_CHNL0)
 177
 178 #define CSR49_FH_INT_TX_MASK    (CSR_FH_INT_BIT_TX_CHNL1 | \
 179                                  CSR_FH_INT_BIT_TX_CHNL0)
 180
 181 /* GPIO */
 182 #define CSR_GPIO_IN_BIT_AUX_POWER                   (0x00000200)
 183 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC                (0x00000000)
 184 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC               (0x00000200)
 185
 186 /* RESET */
 187 #define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
 188 #define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
 189 #define CSR_RESET_REG_FLAG_SW_RESET                  (0x00000080)
 190 #define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
 191 #define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)
 192
 193 /* GP (general purpose) CONTROL */
 194 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY        (0x00000001)
 195 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE              (0x00000004)
 196 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ         (0x00000008)
 197 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP         (0x00000010)
 198
 199 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN           (0x00000001)
 200
 201 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
 202 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE         (0x04000000)
 203 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)
 204
 205
 206 /* HW REV */
 207 #define CSR_HW_REV_TYPE_MSK            (0x00000F0)
 208 #define CSR_HW_REV_TYPE_3945           (0x00000D0)
 209 #define CSR_HW_REV_TYPE_4965           (0x0000000)
 210 #define CSR_HW_REV_TYPE_5300           (0x0000020)
 211 #define CSR_HW_REV_TYPE_5350           (0x0000030)
 212 #define CSR_HW_REV_TYPE_5100           (0x0000050)
 213 #define CSR_HW_REV_TYPE_5150           (0x0000040)
 214 #define CSR_HW_REV_TYPE_NONE           (0x00000F0)
 215
 216 /* EEPROM REG */
 217 #define CSR_EEPROM_REG_READ_VALID_MSK   (0x00000001)
 218 #define CSR_EEPROM_REG_BIT_CMD          (0x00000002)
 219 #define CSR_EEPROM_REG_MSK_ADDR         (0x0000FFFC)
 220 #define CSR_EEPROM_REG_MSK_DATA         (0xFFFF0000)
 221
 222 /* EEPROM GP */
 223 #define CSR_EEPROM_GP_VALID_MSK         (0x00000006)
 224 #define CSR_EEPROM_GP_BAD_SIGNATURE     (0x00000000)
 225 #define CSR_EEPROM_GP_IF_OWNER_MSK      (0x00000180)
 226
 227 /* CSR GIO */
 228 #define CSR_GIO_REG_VAL_L0S_ENABLED     (0x00000002)
 229
 230 /* UCODE DRV GP */
 231 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP             (0x00000001)
 232 #define CSR_UCODE_SW_BIT_RFKILL                     (0x00000002)
 233 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED           (0x00000004)
 234 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT      (0x00000008)
 235
 236 /* GI Chicken Bits */
 237 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (0x00800000)
 238 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER  (0x20000000)
 239
 240 /* LED */
 241 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
 242 #define CSR_LED_REG_TRUN_ON (0x78)
 243 #define CSR_LED_REG_TRUN_OFF (0x38)
 244
 245 /* ANA_PLL */
 246 #define CSR39_ANA_PLL_CFG_VAL        (0x01000000)
 247 #define CSR50_ANA_PLL_CFG_VAL        (0x00880300)
 248
 249 /* HPET MEM debug */
 250 #define CSR_DBG_HPET_MEM_REG_VAL        (0xFFFF0000)
 251 /*=== HBUS (Host-side Bus) ===*/
 252 #define HBUS_BASE       (0x400)
 253 /*
 254  * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
 255  * structures, error log, event log, verifying uCode load).
 256  * First write to address register, then read from or write to data register
 257  * to complete the job.  Once the address register is set up, accesses to
 258  * data registers auto-increment the address by one dword.
 259  * Bit usage for address registers (read or write):
 260  *  0-31:  memory address within device
 261  */
 262 #define HBUS_TARG_MEM_RADDR     (HBUS_BASE+0x00c)
 263 #define HBUS_TARG_MEM_WADDR     (HBUS_BASE+0x010)
 264 #define HBUS_TARG_MEM_WDAT      (HBUS_BASE+0x018)
 265 #define HBUS_TARG_MEM_RDAT      (HBUS_BASE+0x01c)
 266
 267 /*
 268  * Registers for accessing device's internal peripheral registers
 269  * (e.g. SCD, BSM, etc.).  First write to address register,
 270  * then read from or write to data register to complete the job.
 271  * Bit usage for address registers (read or write):
 272  *  0-15:  register address (offset) within device
 273  * 24-25:  (# bytes - 1) to read or write (e.g. 3 for dword)
 274  */
 275 #define HBUS_TARG_PRPH_WADDR    (HBUS_BASE+0x044)
 276 #define HBUS_TARG_PRPH_RADDR    (HBUS_BASE+0x048)
 277 #define HBUS_TARG_PRPH_WDAT     (HBUS_BASE+0x04c)
 278 #define HBUS_TARG_PRPH_RDAT     (HBUS_BASE+0x050)
 279
 280 /*
 281  * Per-Tx-queue write pointer (index, really!) (3945 and 4965).
 282  * Indicates index to next TFD that driver will fill (1 past latest filled).
 283  * Bit usage:
 284  *  0-7:  queue write index
 285  * 11-8:  queue selector
 286  */
 287 #define HBUS_TARG_WRPTR         (HBUS_BASE+0x060)
 288 #define HBUS_TARG_MBX_C         (HBUS_BASE+0x030)
 289
 290 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED         (0x00000004)
 291
 292
 293 #endif /* !__iwl_csr_h__ */