3 Broadcom B43 wireless driver
4 IEEE 802.11a PHY driver
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
31 #include "phy_common.h"
37 /* Get the freq, as it has to be written to the device. */
38 static inline u16
channel2freq_a(u8 channel
)
40 B43_WARN_ON(channel
> 200);
42 return (5000 + 5 * channel
);
45 static inline u16
freq_r3A_value(u16 frequency
)
51 else if (frequency
< 5321)
53 else if (frequency
< 5806)
62 /* This function converts a TSSI value to dBm in Q5.2 */
63 static s8
b43_aphy_estimate_power_out(struct b43_wldev
*dev
, s8 tssi
)
65 struct b43_phy
*phy
= &dev
->phy
;
66 struct b43_phy_a
*aphy
= phy
->a
;
70 tmp
= (aphy
->tgt_idle_tssi
- aphy
->cur_idle_tssi
+ tssi
);
72 tmp
= clamp_val(tmp
, 0x00, 0xFF);
73 dbm
= aphy
->tssi2dbm
[tmp
];
74 //TODO: There's a FIXME on the specs
80 static void b43_radio_set_tx_iq(struct b43_wldev
*dev
)
82 static const u8 data_high
[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
83 static const u8 data_low
[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
84 u16 tmp
= b43_radio_read16(dev
, 0x001E);
87 for (i
= 0; i
< 5; i
++) {
88 for (j
= 0; j
< 5; j
++) {
89 if (tmp
== (data_high
[i
] << 4 | data_low
[j
])) {
90 b43_phy_write(dev
, 0x0069,
91 (i
- j
) << 8 | 0x00C0);
98 static void aphy_channel_switch(struct b43_wldev
*dev
, unsigned int channel
)
102 freq
= channel2freq_a(channel
);
104 r8
= b43_radio_read16(dev
, 0x0008);
105 b43_write16(dev
, 0x03F0, freq
);
106 b43_radio_write16(dev
, 0x0008, r8
);
108 //TODO: write max channel TX power? to Radio 0x2D
109 tmp
= b43_radio_read16(dev
, 0x002E);
111 //TODO: OR tmp with the Power out estimation for this channel?
112 b43_radio_write16(dev
, 0x002E, tmp
);
114 if (freq
>= 4920 && freq
<= 5500) {
116 * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
117 * = (freq * 0.025862069
119 r8
= 3 * freq
/ 116; /* is equal to r8 = freq * 0.025862 */
121 b43_radio_write16(dev
, 0x0007, (r8
<< 4) | r8
);
122 b43_radio_write16(dev
, 0x0020, (r8
<< 4) | r8
);
123 b43_radio_write16(dev
, 0x0021, (r8
<< 4) | r8
);
124 b43_radio_write16(dev
, 0x0022, (b43_radio_read16(dev
, 0x0022)
125 & 0x000F) | (r8
<< 4));
126 b43_radio_write16(dev
, 0x002A, (r8
<< 4));
127 b43_radio_write16(dev
, 0x002B, (r8
<< 4));
128 b43_radio_write16(dev
, 0x0008, (b43_radio_read16(dev
, 0x0008)
129 & 0x00F0) | (r8
<< 4));
130 b43_radio_write16(dev
, 0x0029, (b43_radio_read16(dev
, 0x0029)
132 b43_radio_write16(dev
, 0x0035, 0x00AA);
133 b43_radio_write16(dev
, 0x0036, 0x0085);
134 b43_radio_write16(dev
, 0x003A, (b43_radio_read16(dev
, 0x003A)
136 freq_r3A_value(freq
));
137 b43_radio_write16(dev
, 0x003D,
138 b43_radio_read16(dev
, 0x003D) & 0x00FF);
139 b43_radio_write16(dev
, 0x0081, (b43_radio_read16(dev
, 0x0081)
141 b43_radio_write16(dev
, 0x0035,
142 b43_radio_read16(dev
, 0x0035) & 0xFFEF);
143 b43_radio_write16(dev
, 0x0035, (b43_radio_read16(dev
, 0x0035)
145 b43_radio_set_tx_iq(dev
);
146 //TODO: TSSI2dbm workaround
147 //FIXME b43_phy_xmitpower(dev);
150 static void b43_radio_init2060(struct b43_wldev
*dev
)
152 b43_radio_write16(dev
, 0x0004, 0x00C0);
153 b43_radio_write16(dev
, 0x0005, 0x0008);
154 b43_radio_write16(dev
, 0x0009, 0x0040);
155 b43_radio_write16(dev
, 0x0005, 0x00AA);
156 b43_radio_write16(dev
, 0x0032, 0x008F);
157 b43_radio_write16(dev
, 0x0006, 0x008F);
158 b43_radio_write16(dev
, 0x0034, 0x008F);
159 b43_radio_write16(dev
, 0x002C, 0x0007);
160 b43_radio_write16(dev
, 0x0082, 0x0080);
161 b43_radio_write16(dev
, 0x0080, 0x0000);
162 b43_radio_write16(dev
, 0x003F, 0x00DA);
163 b43_radio_write16(dev
, 0x0005, b43_radio_read16(dev
, 0x0005) & ~0x0008);
164 b43_radio_write16(dev
, 0x0081, b43_radio_read16(dev
, 0x0081) & ~0x0010);
165 b43_radio_write16(dev
, 0x0081, b43_radio_read16(dev
, 0x0081) & ~0x0020);
166 b43_radio_write16(dev
, 0x0081, b43_radio_read16(dev
, 0x0081) & ~0x0020);
167 msleep(1); /* delay 400usec */
169 b43_radio_write16(dev
, 0x0081,
170 (b43_radio_read16(dev
, 0x0081) & ~0x0020) | 0x0010);
171 msleep(1); /* delay 400usec */
173 b43_radio_write16(dev
, 0x0005,
174 (b43_radio_read16(dev
, 0x0005) & ~0x0008) | 0x0008);
175 b43_radio_write16(dev
, 0x0085, b43_radio_read16(dev
, 0x0085) & ~0x0010);
176 b43_radio_write16(dev
, 0x0005, b43_radio_read16(dev
, 0x0005) & ~0x0008);
177 b43_radio_write16(dev
, 0x0081, b43_radio_read16(dev
, 0x0081) & ~0x0040);
178 b43_radio_write16(dev
, 0x0081,
179 (b43_radio_read16(dev
, 0x0081) & ~0x0040) | 0x0040);
180 b43_radio_write16(dev
, 0x0005,
181 (b43_radio_read16(dev
, 0x0081) & ~0x0008) | 0x0008);
182 b43_phy_write(dev
, 0x0063, 0xDDC6);
183 b43_phy_write(dev
, 0x0069, 0x07BE);
184 b43_phy_write(dev
, 0x006A, 0x0000);
186 aphy_channel_switch(dev
, dev
->phy
.ops
->get_default_chan(dev
));
191 static void b43_phy_rssiagc(struct b43_wldev
*dev
, u8 enable
)
195 if (dev
->phy
.rev
< 3) {
197 for (i
= 0; i
< B43_TAB_RSSIAGC1_SIZE
; i
++) {
198 b43_ofdmtab_write16(dev
,
199 B43_OFDMTAB_LNAHPFGAIN1
, i
, 0xFFF8);
200 b43_ofdmtab_write16(dev
,
201 B43_OFDMTAB_WRSSI
, i
, 0xFFF8);
204 for (i
= 0; i
< B43_TAB_RSSIAGC1_SIZE
; i
++) {
205 b43_ofdmtab_write16(dev
,
206 B43_OFDMTAB_LNAHPFGAIN1
, i
, b43_tab_rssiagc1
[i
]);
207 b43_ofdmtab_write16(dev
,
208 B43_OFDMTAB_WRSSI
, i
, b43_tab_rssiagc1
[i
]);
212 for (i
= 0; i
< B43_TAB_RSSIAGC1_SIZE
; i
++)
213 b43_ofdmtab_write16(dev
,
214 B43_OFDMTAB_WRSSI
, i
, 0x0820);
216 for (i
= 0; i
< B43_TAB_RSSIAGC2_SIZE
; i
++)
217 b43_ofdmtab_write16(dev
,
218 B43_OFDMTAB_WRSSI
, i
, b43_tab_rssiagc2
[i
]);
222 static void b43_phy_ww(struct b43_wldev
*dev
)
224 u16 b
, curr_s
, best_s
= 0xFFFF;
227 b43_phy_write(dev
, B43_PHY_CRS0
,
228 b43_phy_read(dev
, B43_PHY_CRS0
) & ~B43_PHY_CRS0_EN
);
229 b43_phy_write(dev
, B43_PHY_OFDM(0x1B),
230 b43_phy_read(dev
, B43_PHY_OFDM(0x1B)) | 0x1000);
231 b43_phy_write(dev
, B43_PHY_OFDM(0x82),
232 (b43_phy_read(dev
, B43_PHY_OFDM(0x82)) & 0xF0FF) | 0x0300);
233 b43_radio_write16(dev
, 0x0009,
234 b43_radio_read16(dev
, 0x0009) | 0x0080);
235 b43_radio_write16(dev
, 0x0012,
236 (b43_radio_read16(dev
, 0x0012) & 0xFFFC) | 0x0002);
237 b43_wa_initgains(dev
);
238 b43_phy_write(dev
, B43_PHY_OFDM(0xBA), 0x3ED5);
239 b
= b43_phy_read(dev
, B43_PHY_PWRDOWN
);
240 b43_phy_write(dev
, B43_PHY_PWRDOWN
, (b
& 0xFFF8) | 0x0005);
241 b43_radio_write16(dev
, 0x0004,
242 b43_radio_read16(dev
, 0x0004) | 0x0004);
243 for (i
= 0x10; i
<= 0x20; i
++) {
244 b43_radio_write16(dev
, 0x0013, i
);
245 curr_s
= b43_phy_read(dev
, B43_PHY_OTABLEQ
) & 0x00FF;
249 } else if (curr_s
>= 0x0080)
250 curr_s
= 0x0100 - curr_s
;
254 b43_phy_write(dev
, B43_PHY_PWRDOWN
, b
);
255 b43_radio_write16(dev
, 0x0004,
256 b43_radio_read16(dev
, 0x0004) & 0xFFFB);
257 b43_radio_write16(dev
, 0x0013, best_s
);
258 b43_ofdmtab_write16(dev
, B43_OFDMTAB_AGC1_R1
, 0, 0xFFEC);
259 b43_phy_write(dev
, B43_PHY_OFDM(0xB7), 0x1E80);
260 b43_phy_write(dev
, B43_PHY_OFDM(0xB6), 0x1C00);
261 b43_phy_write(dev
, B43_PHY_OFDM(0xB5), 0x0EC0);
262 b43_phy_write(dev
, B43_PHY_OFDM(0xB2), 0x00C0);
263 b43_phy_write(dev
, B43_PHY_OFDM(0xB9), 0x1FFF);
264 b43_phy_write(dev
, B43_PHY_OFDM(0xBB),
265 (b43_phy_read(dev
, B43_PHY_OFDM(0xBB)) & 0xF000) | 0x0053);
266 b43_phy_write(dev
, B43_PHY_OFDM61
,
267 (b43_phy_read(dev
, B43_PHY_OFDM61
) & 0xFE1F) | 0x0120);
268 b43_phy_write(dev
, B43_PHY_OFDM(0x13),
269 (b43_phy_read(dev
, B43_PHY_OFDM(0x13)) & 0x0FFF) | 0x3000);
270 b43_phy_write(dev
, B43_PHY_OFDM(0x14),
271 (b43_phy_read(dev
, B43_PHY_OFDM(0x14)) & 0x0FFF) | 0x3000);
272 b43_ofdmtab_write16(dev
, B43_OFDMTAB_AGC1
, 6, 0x0017);
273 for (i
= 0; i
< 6; i
++)
274 b43_ofdmtab_write16(dev
, B43_OFDMTAB_AGC1
, i
, 0x000F);
275 b43_ofdmtab_write16(dev
, B43_OFDMTAB_AGC1
, 0x0D, 0x000E);
276 b43_ofdmtab_write16(dev
, B43_OFDMTAB_AGC1
, 0x0E, 0x0011);
277 b43_ofdmtab_write16(dev
, B43_OFDMTAB_AGC1
, 0x0F, 0x0013);
278 b43_phy_write(dev
, B43_PHY_OFDM(0x33), 0x5030);
279 b43_phy_write(dev
, B43_PHY_CRS0
,
280 b43_phy_read(dev
, B43_PHY_CRS0
) | B43_PHY_CRS0_EN
);
283 static void hardware_pctl_init_aphy(struct b43_wldev
*dev
)
288 void b43_phy_inita(struct b43_wldev
*dev
)
290 struct ssb_bus
*bus
= dev
->dev
->bus
;
291 struct b43_phy
*phy
= &dev
->phy
;
293 /* This lowlevel A-PHY init is also called from G-PHY init.
294 * So we must not access phy->a, if called from G-PHY code.
296 B43_WARN_ON((phy
->type
!= B43_PHYTYPE_A
) &&
297 (phy
->type
!= B43_PHYTYPE_G
));
302 if (phy
->type
== B43_PHYTYPE_A
)
303 b43_phy_write(dev
, B43_PHY_OFDM(0x1B),
304 b43_phy_read(dev
, B43_PHY_OFDM(0x1B)) & ~0x1000);
305 if (b43_phy_read(dev
, B43_PHY_ENCORE
) & B43_PHY_ENCORE_EN
)
306 b43_phy_write(dev
, B43_PHY_ENCORE
,
307 b43_phy_read(dev
, B43_PHY_ENCORE
) | 0x0010);
309 b43_phy_write(dev
, B43_PHY_ENCORE
,
310 b43_phy_read(dev
, B43_PHY_ENCORE
) & ~0x1010);
315 if (phy
->type
== B43_PHYTYPE_A
) {
316 if (phy
->gmode
&& (phy
->rev
< 3))
317 b43_phy_write(dev
, 0x0034,
318 b43_phy_read(dev
, 0x0034) | 0x0001);
319 b43_phy_rssiagc(dev
, 0);
321 b43_phy_write(dev
, B43_PHY_CRS0
,
322 b43_phy_read(dev
, B43_PHY_CRS0
) | B43_PHY_CRS0_EN
);
324 b43_radio_init2060(dev
);
326 if ((bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_BCM
) &&
327 ((bus
->boardinfo
.type
== SSB_BOARD_BU4306
) ||
328 (bus
->boardinfo
.type
== SSB_BOARD_BU4309
))) {
335 hardware_pctl_init_aphy(dev
);
337 //TODO: radar detection
340 if ((phy
->type
== B43_PHYTYPE_G
) &&
341 (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_PACTRL
)) {
342 b43_phy_write(dev
, B43_PHY_OFDM(0x6E),
343 (b43_phy_read(dev
, B43_PHY_OFDM(0x6E))
348 /* Initialise the TSSI->dBm lookup table */
349 static int b43_aphy_init_tssi2dbm_table(struct b43_wldev
*dev
)
351 struct b43_phy
*phy
= &dev
->phy
;
352 struct b43_phy_a
*aphy
= phy
->a
;
353 s16 pab0
, pab1
, pab2
;
355 pab0
= (s16
) (dev
->dev
->bus
->sprom
.pa1b0
);
356 pab1
= (s16
) (dev
->dev
->bus
->sprom
.pa1b1
);
357 pab2
= (s16
) (dev
->dev
->bus
->sprom
.pa1b2
);
359 if (pab0
!= 0 && pab1
!= 0 && pab2
!= 0 &&
360 pab0
!= -1 && pab1
!= -1 && pab2
!= -1) {
361 /* The pabX values are set in SPROM. Use them. */
362 if ((s8
) dev
->dev
->bus
->sprom
.itssi_a
!= 0 &&
363 (s8
) dev
->dev
->bus
->sprom
.itssi_a
!= -1)
364 aphy
->tgt_idle_tssi
=
365 (s8
) (dev
->dev
->bus
->sprom
.itssi_a
);
367 aphy
->tgt_idle_tssi
= 62;
368 aphy
->tssi2dbm
= b43_generate_dyn_tssi2dbm_tab(dev
, pab0
,
373 /* pabX values not set in SPROM,
374 * but APHY needs a generated table. */
375 aphy
->tssi2dbm
= NULL
;
376 b43err(dev
->wl
, "Could not generate tssi2dBm "
377 "table (wrong SPROM info)!\n");
384 static int b43_aphy_op_allocate(struct b43_wldev
*dev
)
386 struct b43_phy_a
*aphy
;
389 aphy
= kzalloc(sizeof(*aphy
), GFP_KERNEL
);
394 err
= b43_aphy_init_tssi2dbm_table(dev
);
407 static void b43_aphy_op_prepare_structs(struct b43_wldev
*dev
)
409 struct b43_phy
*phy
= &dev
->phy
;
410 struct b43_phy_a
*aphy
= phy
->a
;
411 const void *tssi2dbm
;
414 /* tssi2dbm table is constant, so it is initialized at alloc time.
415 * Save a copy of the pointer. */
416 tssi2dbm
= aphy
->tssi2dbm
;
417 tgt_idle_tssi
= aphy
->tgt_idle_tssi
;
419 /* Zero out the whole PHY structure. */
420 memset(aphy
, 0, sizeof(*aphy
));
422 aphy
->tssi2dbm
= tssi2dbm
;
423 aphy
->tgt_idle_tssi
= tgt_idle_tssi
;
425 //TODO init struct b43_phy_a
429 static void b43_aphy_op_free(struct b43_wldev
*dev
)
431 struct b43_phy
*phy
= &dev
->phy
;
432 struct b43_phy_a
*aphy
= phy
->a
;
434 kfree(aphy
->tssi2dbm
);
435 aphy
->tssi2dbm
= NULL
;
441 static int b43_aphy_op_init(struct b43_wldev
*dev
)
448 static inline u16
adjust_phyreg(struct b43_wldev
*dev
, u16 offset
)
450 /* OFDM registers are base-registers for the A-PHY. */
451 if ((offset
& B43_PHYROUTE
) == B43_PHYROUTE_OFDM_GPHY
) {
452 offset
&= ~B43_PHYROUTE
;
453 offset
|= B43_PHYROUTE_BASE
;
457 if ((offset
& B43_PHYROUTE
) == B43_PHYROUTE_EXT_GPHY
) {
458 /* Ext-G registers are only available on G-PHYs */
459 b43err(dev
->wl
, "Invalid EXT-G PHY access at "
460 "0x%04X on A-PHY\n", offset
);
463 if ((offset
& B43_PHYROUTE
) == B43_PHYROUTE_N_BMODE
) {
464 /* N-BMODE registers are only available on N-PHYs */
465 b43err(dev
->wl
, "Invalid N-BMODE PHY access at "
466 "0x%04X on A-PHY\n", offset
);
469 #endif /* B43_DEBUG */
474 static u16
b43_aphy_op_read(struct b43_wldev
*dev
, u16 reg
)
476 reg
= adjust_phyreg(dev
, reg
);
477 b43_write16(dev
, B43_MMIO_PHY_CONTROL
, reg
);
478 return b43_read16(dev
, B43_MMIO_PHY_DATA
);
481 static void b43_aphy_op_write(struct b43_wldev
*dev
, u16 reg
, u16 value
)
483 reg
= adjust_phyreg(dev
, reg
);
484 b43_write16(dev
, B43_MMIO_PHY_CONTROL
, reg
);
485 b43_write16(dev
, B43_MMIO_PHY_DATA
, value
);
488 static u16
b43_aphy_op_radio_read(struct b43_wldev
*dev
, u16 reg
)
490 /* Register 1 is a 32-bit register. */
491 B43_WARN_ON(reg
== 1);
492 /* A-PHY needs 0x40 for read access */
495 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, reg
);
496 return b43_read16(dev
, B43_MMIO_RADIO_DATA_LOW
);
499 static void b43_aphy_op_radio_write(struct b43_wldev
*dev
, u16 reg
, u16 value
)
501 /* Register 1 is a 32-bit register. */
502 B43_WARN_ON(reg
== 1);
504 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, reg
);
505 b43_write16(dev
, B43_MMIO_RADIO_DATA_LOW
, value
);
508 static bool b43_aphy_op_supports_hwpctl(struct b43_wldev
*dev
)
510 return (dev
->phy
.rev
>= 5);
513 static void b43_aphy_op_software_rfkill(struct b43_wldev
*dev
,
514 enum rfkill_state state
)
516 struct b43_phy
*phy
= &dev
->phy
;
518 if (state
== RFKILL_STATE_UNBLOCKED
) {
521 b43_radio_write16(dev
, 0x0004, 0x00C0);
522 b43_radio_write16(dev
, 0x0005, 0x0008);
523 b43_phy_write(dev
, 0x0010, b43_phy_read(dev
, 0x0010) & 0xFFF7);
524 b43_phy_write(dev
, 0x0011, b43_phy_read(dev
, 0x0011) & 0xFFF7);
525 b43_radio_init2060(dev
);
527 b43_radio_write16(dev
, 0x0004, 0x00FF);
528 b43_radio_write16(dev
, 0x0005, 0x00FB);
529 b43_phy_write(dev
, 0x0010, b43_phy_read(dev
, 0x0010) | 0x0008);
530 b43_phy_write(dev
, 0x0011, b43_phy_read(dev
, 0x0011) | 0x0008);
534 static int b43_aphy_op_switch_channel(struct b43_wldev
*dev
,
535 unsigned int new_channel
)
537 if (new_channel
> 200)
539 aphy_channel_switch(dev
, new_channel
);
544 static unsigned int b43_aphy_op_get_default_chan(struct b43_wldev
*dev
)
546 return 36; /* Default to channel 36 */
549 static void b43_aphy_op_set_rx_antenna(struct b43_wldev
*dev
, int antenna
)
551 struct b43_phy
*phy
= &dev
->phy
;
556 if (antenna
== B43_ANTENNA_AUTO0
|| antenna
== B43_ANTENNA_AUTO1
)
559 hf
= b43_hf_read(dev
);
560 hf
&= ~B43_HF_ANTDIVHELP
;
561 b43_hf_write(dev
, hf
);
563 tmp
= b43_phy_read(dev
, B43_PHY_BBANDCFG
);
564 tmp
&= ~B43_PHY_BBANDCFG_RXANT
;
565 tmp
|= (autodiv
? B43_ANTENNA_AUTO0
: antenna
)
566 << B43_PHY_BBANDCFG_RXANT_SHIFT
;
567 b43_phy_write(dev
, B43_PHY_BBANDCFG
, tmp
);
570 tmp
= b43_phy_read(dev
, B43_PHY_ANTDWELL
);
571 if (antenna
== B43_ANTENNA_AUTO0
)
572 tmp
&= ~B43_PHY_ANTDWELL_AUTODIV1
;
574 tmp
|= B43_PHY_ANTDWELL_AUTODIV1
;
575 b43_phy_write(dev
, B43_PHY_ANTDWELL
, tmp
);
578 tmp
= b43_phy_read(dev
, B43_PHY_ANTDWELL
);
579 tmp
= (tmp
& 0xFF00) | 0x24;
580 b43_phy_write(dev
, B43_PHY_ANTDWELL
, tmp
);
582 tmp
= b43_phy_read(dev
, B43_PHY_OFDM61
);
584 b43_phy_write(dev
, B43_PHY_OFDM61
, tmp
);
585 if (phy
->analog
== 3) {
586 b43_phy_write(dev
, B43_PHY_CLIPPWRDOWNT
,
588 b43_phy_write(dev
, B43_PHY_ADIVRELATED
,
591 b43_phy_write(dev
, B43_PHY_CLIPPWRDOWNT
,
595 B43_PHY_ADIVRELATED
);
596 tmp
= (tmp
& 0xFF00) | 8;
597 b43_phy_write(dev
, B43_PHY_ADIVRELATED
,
602 hf
|= B43_HF_ANTDIVHELP
;
603 b43_hf_write(dev
, hf
);
606 static void b43_aphy_op_adjust_txpower(struct b43_wldev
*dev
)
610 static enum b43_txpwr_result
b43_aphy_op_recalc_txpower(struct b43_wldev
*dev
,
613 return B43_TXPWR_RES_DONE
;
616 static void b43_aphy_op_pwork_15sec(struct b43_wldev
*dev
)
620 static void b43_aphy_op_pwork_60sec(struct b43_wldev
*dev
)
624 const struct b43_phy_operations b43_phyops_a
= {
625 .allocate
= b43_aphy_op_allocate
,
626 .free
= b43_aphy_op_free
,
627 .prepare_structs
= b43_aphy_op_prepare_structs
,
628 .init
= b43_aphy_op_init
,
629 .phy_read
= b43_aphy_op_read
,
630 .phy_write
= b43_aphy_op_write
,
631 .radio_read
= b43_aphy_op_radio_read
,
632 .radio_write
= b43_aphy_op_radio_write
,
633 .supports_hwpctl
= b43_aphy_op_supports_hwpctl
,
634 .software_rfkill
= b43_aphy_op_software_rfkill
,
635 .switch_analog
= b43_phyop_switch_analog_generic
,
636 .switch_channel
= b43_aphy_op_switch_channel
,
637 .get_default_chan
= b43_aphy_op_get_default_chan
,
638 .set_rx_antenna
= b43_aphy_op_set_rx_antenna
,
639 .recalc_txpower
= b43_aphy_op_recalc_txpower
,
640 .adjust_txpower
= b43_aphy_op_adjust_txpower
,
641 .pwork_15sec
= b43_aphy_op_pwork_15sec
,
642 .pwork_60sec
= b43_aphy_op_pwork_60sec
,