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added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / drivers / net / igb / igb_main.c
blob9dd13ad12ce48a502469c96474e8210ccb5c00a1
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/ipv6.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/mii.h>
38 #include <linux/ethtool.h>
39 #include <linux/if_vlan.h>
40 #include <linux/pci.h>
41 #include <linux/pci-aspm.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/if_ether.h>
45 #include <linux/aer.h>
46 #ifdef CONFIG_IGB_DCA
47 #include <linux/dca.h>
48 #endif
49 #include "igb.h"
50
51 #define DRV_VERSION "1.2.45-k2"
52 char igb_driver_name[] = "igb";
53 char igb_driver_version[] = DRV_VERSION;
54 static const char igb_driver_string[] =
55 "Intel(R) Gigabit Ethernet Network Driver";
56 static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
57
58 static const struct e1000_info *igb_info_tbl[] = {
59 [board_82575] = &e1000_82575_info,
60 };
61
62 static struct pci_device_id igb_pci_tbl[] = {
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
69 /* required last entry */
70 {0, }
71 };
72
73 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
74
75 void igb_reset(struct igb_adapter *);
76 static int igb_setup_all_tx_resources(struct igb_adapter *);
77 static int igb_setup_all_rx_resources(struct igb_adapter *);
78 static void igb_free_all_tx_resources(struct igb_adapter *);
79 static void igb_free_all_rx_resources(struct igb_adapter *);
80 void igb_update_stats(struct igb_adapter *);
81 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
82 static void __devexit igb_remove(struct pci_dev *pdev);
83 static int igb_sw_init(struct igb_adapter *);
84 static int igb_open(struct net_device *);
85 static int igb_close(struct net_device *);
86 static void igb_configure_tx(struct igb_adapter *);
87 static void igb_configure_rx(struct igb_adapter *);
88 static void igb_setup_rctl(struct igb_adapter *);
89 static void igb_clean_all_tx_rings(struct igb_adapter *);
90 static void igb_clean_all_rx_rings(struct igb_adapter *);
91 static void igb_clean_tx_ring(struct igb_ring *);
92 static void igb_clean_rx_ring(struct igb_ring *);
93 static void igb_set_multi(struct net_device *);
94 static void igb_update_phy_info(unsigned long);
95 static void igb_watchdog(unsigned long);
96 static void igb_watchdog_task(struct work_struct *);
97 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
98 struct igb_ring *);
99 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
100 static struct net_device_stats *igb_get_stats(struct net_device *);
101 static int igb_change_mtu(struct net_device *, int);
102 static int igb_set_mac(struct net_device *, void *);
103 static irqreturn_t igb_intr(int irq, void *);
104 static irqreturn_t igb_intr_msi(int irq, void *);
105 static irqreturn_t igb_msix_other(int irq, void *);
106 static irqreturn_t igb_msix_rx(int irq, void *);
107 static irqreturn_t igb_msix_tx(int irq, void *);
108 static int igb_clean_rx_ring_msix(struct napi_struct *, int);
109 #ifdef CONFIG_IGB_DCA
110 static void igb_update_rx_dca(struct igb_ring *);
111 static void igb_update_tx_dca(struct igb_ring *);
112 static void igb_setup_dca(struct igb_adapter *);
113 #endif /* CONFIG_IGB_DCA */
114 static bool igb_clean_tx_irq(struct igb_ring *);
115 static int igb_poll(struct napi_struct *, int);
116 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
117 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
118 #ifdef CONFIG_IGB_LRO
119 static int igb_get_skb_hdr(struct sk_buff *skb, void **, void **, u64 *, void *);
120 #endif
121 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
122 static void igb_tx_timeout(struct net_device *);
123 static void igb_reset_task(struct work_struct *);
124 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
125 static void igb_vlan_rx_add_vid(struct net_device *, u16);
126 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
127 static void igb_restore_vlan(struct igb_adapter *);
128
129 static int igb_suspend(struct pci_dev *, pm_message_t);
130 #ifdef CONFIG_PM
131 static int igb_resume(struct pci_dev *);
132 #endif
133 static void igb_shutdown(struct pci_dev *);
134 #ifdef CONFIG_IGB_DCA
135 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
136 static struct notifier_block dca_notifier = {
137 .notifier_call = igb_notify_dca,
138 .next = NULL,
139 .priority = 0
140 };
141 #endif
142
143 #ifdef CONFIG_NET_POLL_CONTROLLER
144 /* for netdump / net console */
145 static void igb_netpoll(struct net_device *);
146 #endif
147
148 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
149 pci_channel_state_t);
150 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
151 static void igb_io_resume(struct pci_dev *);
152
153 static struct pci_error_handlers igb_err_handler = {
154 .error_detected = igb_io_error_detected,
155 .slot_reset = igb_io_slot_reset,
156 .resume = igb_io_resume,
157 };
158
159
160 static struct pci_driver igb_driver = {
161 .name = igb_driver_name,
162 .id_table = igb_pci_tbl,
163 .probe = igb_probe,
164 .remove = __devexit_p(igb_remove),
165 #ifdef CONFIG_PM
166 /* Power Managment Hooks */
167 .suspend = igb_suspend,
168 .resume = igb_resume,
169 #endif
170 .shutdown = igb_shutdown,
171 .err_handler = &igb_err_handler
172 };
173
174 static int global_quad_port_a; /* global quad port a indication */
175
176 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
177 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
178 MODULE_LICENSE("GPL");
179 MODULE_VERSION(DRV_VERSION);
180
181 #ifdef DEBUG
182 /**
183 * igb_get_hw_dev_name - return device name string
184 * used by hardware layer to print debugging information
185 **/
186 char *igb_get_hw_dev_name(struct e1000_hw *hw)
187 {
188 struct igb_adapter *adapter = hw->back;
189 return adapter->netdev->name;
190 }
191 #endif
192
193 /**
194 * igb_init_module - Driver Registration Routine
195 *
196 * igb_init_module is the first routine called when the driver is
197 * loaded. All it does is register with the PCI subsystem.
198 **/
199 static int __init igb_init_module(void)
200 {
201 int ret;
202 printk(KERN_INFO "%s - version %s\n",
203 igb_driver_string, igb_driver_version);
204
205 printk(KERN_INFO "%s\n", igb_copyright);
206
207 global_quad_port_a = 0;
208
209 #ifdef CONFIG_IGB_DCA
210 dca_register_notify(&dca_notifier);
211 #endif
212
213 ret = pci_register_driver(&igb_driver);
214 return ret;
215 }
216
217 module_init(igb_init_module);
218
219 /**
220 * igb_exit_module - Driver Exit Cleanup Routine
221 *
222 * igb_exit_module is called just before the driver is removed
223 * from memory.
224 **/
225 static void __exit igb_exit_module(void)
226 {
227 #ifdef CONFIG_IGB_DCA
228 dca_unregister_notify(&dca_notifier);
229 #endif
230 pci_unregister_driver(&igb_driver);
231 }
232
233 module_exit(igb_exit_module);
234
235 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
236 /**
237 * igb_cache_ring_register - Descriptor ring to register mapping
238 * @adapter: board private structure to initialize
239 *
240 * Once we know the feature-set enabled for the device, we'll cache
241 * the register offset the descriptor ring is assigned to.
242 **/
243 static void igb_cache_ring_register(struct igb_adapter *adapter)
244 {
245 int i;
246
247 switch (adapter->hw.mac.type) {
248 case e1000_82576:
249 /* The queues are allocated for virtualization such that VF 0
250 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
251 * In order to avoid collision we start at the first free queue
252 * and continue consuming queues in the same sequence
253 */
254 for (i = 0; i < adapter->num_rx_queues; i++)
255 adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
256 for (i = 0; i < adapter->num_tx_queues; i++)
257 adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
258 break;
259 case e1000_82575:
260 default:
261 for (i = 0; i < adapter->num_rx_queues; i++)
262 adapter->rx_ring[i].reg_idx = i;
263 for (i = 0; i < adapter->num_tx_queues; i++)
264 adapter->tx_ring[i].reg_idx = i;
265 break;
266 }
267 }
268
269 /**
270 * igb_alloc_queues - Allocate memory for all rings
271 * @adapter: board private structure to initialize
272 *
273 * We allocate one ring per queue at run-time since we don't know the
274 * number of queues at compile-time.
275 **/
276 static int igb_alloc_queues(struct igb_adapter *adapter)
277 {
278 int i;
279
280 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
281 sizeof(struct igb_ring), GFP_KERNEL);
282 if (!adapter->tx_ring)
283 return -ENOMEM;
284
285 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
286 sizeof(struct igb_ring), GFP_KERNEL);
287 if (!adapter->rx_ring) {
288 kfree(adapter->tx_ring);
289 return -ENOMEM;
290 }
291
292 adapter->rx_ring->buddy = adapter->tx_ring;
293
294 for (i = 0; i < adapter->num_tx_queues; i++) {
295 struct igb_ring *ring = &(adapter->tx_ring[i]);
296 ring->count = adapter->tx_ring_count;
297 ring->adapter = adapter;
298 ring->queue_index = i;
299 }
300 for (i = 0; i < adapter->num_rx_queues; i++) {
301 struct igb_ring *ring = &(adapter->rx_ring[i]);
302 ring->count = adapter->rx_ring_count;
303 ring->adapter = adapter;
304 ring->queue_index = i;
305 ring->itr_register = E1000_ITR;
306
307 /* set a default napi handler for each rx_ring */
308 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
309 }
310
311 igb_cache_ring_register(adapter);
312 return 0;
313 }
314
315 static void igb_free_queues(struct igb_adapter *adapter)
316 {
317 int i;
318
319 for (i = 0; i < adapter->num_rx_queues; i++)
320 netif_napi_del(&adapter->rx_ring[i].napi);
321
322 kfree(adapter->tx_ring);
323 kfree(adapter->rx_ring);
324 }
325
326 #define IGB_N0_QUEUE -1
327 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
328 int tx_queue, int msix_vector)
329 {
330 u32 msixbm = 0;
331 struct e1000_hw *hw = &adapter->hw;
332 u32 ivar, index;
333
334 switch (hw->mac.type) {
335 case e1000_82575:
336 /* The 82575 assigns vectors using a bitmask, which matches the
337 bitmask for the EICR/EIMS/EIMC registers. To assign one
338 or more queues to a vector, we write the appropriate bits
339 into the MSIXBM register for that vector. */
340 if (rx_queue > IGB_N0_QUEUE) {
341 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
342 adapter->rx_ring[rx_queue].eims_value = msixbm;
343 }
344 if (tx_queue > IGB_N0_QUEUE) {
345 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
346 adapter->tx_ring[tx_queue].eims_value =
347 E1000_EICR_TX_QUEUE0 << tx_queue;
348 }
349 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
350 break;
351 case e1000_82576:
352 /* 82576 uses a table-based method for assigning vectors.
353 Each queue has a single entry in the table to which we write
354 a vector number along with a "valid" bit. Sadly, the layout
355 of the table is somewhat counterintuitive. */
356 if (rx_queue > IGB_N0_QUEUE) {
357 index = (rx_queue >> 1);
358 ivar = array_rd32(E1000_IVAR0, index);
359 if (rx_queue & 0x1) {
360 /* vector goes into third byte of register */
361 ivar = ivar & 0xFF00FFFF;
362 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
363 } else {
364 /* vector goes into low byte of register */
365 ivar = ivar & 0xFFFFFF00;
366 ivar |= msix_vector | E1000_IVAR_VALID;
367 }
368 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
369 array_wr32(E1000_IVAR0, index, ivar);
370 }
371 if (tx_queue > IGB_N0_QUEUE) {
372 index = (tx_queue >> 1);
373 ivar = array_rd32(E1000_IVAR0, index);
374 if (tx_queue & 0x1) {
375 /* vector goes into high byte of register */
376 ivar = ivar & 0x00FFFFFF;
377 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
378 } else {
379 /* vector goes into second byte of register */
380 ivar = ivar & 0xFFFF00FF;
381 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
382 }
383 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
384 array_wr32(E1000_IVAR0, index, ivar);
385 }
386 break;
387 default:
388 BUG();
389 break;
390 }
391 }
392
393 /**
394 * igb_configure_msix - Configure MSI-X hardware
395 *
396 * igb_configure_msix sets up the hardware to properly
397 * generate MSI-X interrupts.
398 **/
399 static void igb_configure_msix(struct igb_adapter *adapter)
400 {
401 u32 tmp;
402 int i, vector = 0;
403 struct e1000_hw *hw = &adapter->hw;
404
405 adapter->eims_enable_mask = 0;
406 if (hw->mac.type == e1000_82576)
407 /* Turn on MSI-X capability first, or our settings
408 * won't stick. And it will take days to debug. */
409 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
410 E1000_GPIE_PBA | E1000_GPIE_EIAME |
411 E1000_GPIE_NSICR);
412
413 for (i = 0; i < adapter->num_tx_queues; i++) {
414 struct igb_ring *tx_ring = &adapter->tx_ring[i];
415 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
416 adapter->eims_enable_mask |= tx_ring->eims_value;
417 if (tx_ring->itr_val)
418 writel(tx_ring->itr_val,
419 hw->hw_addr + tx_ring->itr_register);
420 else
421 writel(1, hw->hw_addr + tx_ring->itr_register);
422 }
423
424 for (i = 0; i < adapter->num_rx_queues; i++) {
425 struct igb_ring *rx_ring = &adapter->rx_ring[i];
426 rx_ring->buddy = NULL;
427 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
428 adapter->eims_enable_mask |= rx_ring->eims_value;
429 if (rx_ring->itr_val)
430 writel(rx_ring->itr_val,
431 hw->hw_addr + rx_ring->itr_register);
432 else
433 writel(1, hw->hw_addr + rx_ring->itr_register);
434 }
435
436
437 /* set vector for other causes, i.e. link changes */
438 switch (hw->mac.type) {
439 case e1000_82575:
440 array_wr32(E1000_MSIXBM(0), vector++,
441 E1000_EIMS_OTHER);
442
443 tmp = rd32(E1000_CTRL_EXT);
444 /* enable MSI-X PBA support*/
445 tmp |= E1000_CTRL_EXT_PBA_CLR;
446
447 /* Auto-Mask interrupts upon ICR read. */
448 tmp |= E1000_CTRL_EXT_EIAME;
449 tmp |= E1000_CTRL_EXT_IRCA;
450
451 wr32(E1000_CTRL_EXT, tmp);
452 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
453 adapter->eims_other = E1000_EIMS_OTHER;
454
455 break;
456
457 case e1000_82576:
458 tmp = (vector++ | E1000_IVAR_VALID) << 8;
459 wr32(E1000_IVAR_MISC, tmp);
460
461 adapter->eims_enable_mask = (1 << (vector)) - 1;
462 adapter->eims_other = 1 << (vector - 1);
463 break;
464 default:
465 /* do nothing, since nothing else supports MSI-X */
466 break;
467 } /* switch (hw->mac.type) */
468 wrfl();
469 }
470
471 /**
472 * igb_request_msix - Initialize MSI-X interrupts
473 *
474 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
475 * kernel.
476 **/
477 static int igb_request_msix(struct igb_adapter *adapter)
478 {
479 struct net_device *netdev = adapter->netdev;
480 int i, err = 0, vector = 0;
481
482 vector = 0;
483
484 for (i = 0; i < adapter->num_tx_queues; i++) {
485 struct igb_ring *ring = &(adapter->tx_ring[i]);
486 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
487 err = request_irq(adapter->msix_entries[vector].vector,
488 &igb_msix_tx, 0, ring->name,
489 &(adapter->tx_ring[i]));
490 if (err)
491 goto out;
492 ring->itr_register = E1000_EITR(0) + (vector << 2);
493 ring->itr_val = 976; /* ~4000 ints/sec */
494 vector++;
495 }
496 for (i = 0; i < adapter->num_rx_queues; i++) {
497 struct igb_ring *ring = &(adapter->rx_ring[i]);
498 if (strlen(netdev->name) < (IFNAMSIZ - 5))
499 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
500 else
501 memcpy(ring->name, netdev->name, IFNAMSIZ);
502 err = request_irq(adapter->msix_entries[vector].vector,
503 &igb_msix_rx, 0, ring->name,
504 &(adapter->rx_ring[i]));
505 if (err)
506 goto out;
507 ring->itr_register = E1000_EITR(0) + (vector << 2);
508 ring->itr_val = adapter->itr;
509 /* overwrite the poll routine for MSIX, we've already done
510 * netif_napi_add */
511 ring->napi.poll = &igb_clean_rx_ring_msix;
512 vector++;
513 }
514
515 err = request_irq(adapter->msix_entries[vector].vector,
516 &igb_msix_other, 0, netdev->name, netdev);
517 if (err)
518 goto out;
519
520 igb_configure_msix(adapter);
521 return 0;
522 out:
523 return err;
524 }
525
526 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
527 {
528 if (adapter->msix_entries) {
529 pci_disable_msix(adapter->pdev);
530 kfree(adapter->msix_entries);
531 adapter->msix_entries = NULL;
532 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
533 pci_disable_msi(adapter->pdev);
534 return;
535 }
536
537
538 /**
539 * igb_set_interrupt_capability - set MSI or MSI-X if supported
540 *
541 * Attempt to configure interrupts using the best available
542 * capabilities of the hardware and kernel.
543 **/
544 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
545 {
546 int err;
547 int numvecs, i;
548
549 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
550 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
551 GFP_KERNEL);
552 if (!adapter->msix_entries)
553 goto msi_only;
554
555 for (i = 0; i < numvecs; i++)
556 adapter->msix_entries[i].entry = i;
557
558 err = pci_enable_msix(adapter->pdev,
559 adapter->msix_entries,
560 numvecs);
561 if (err == 0)
562 goto out;
563
564 igb_reset_interrupt_capability(adapter);
565
566 /* If we can't do MSI-X, try MSI */
567 msi_only:
568 adapter->num_rx_queues = 1;
569 adapter->num_tx_queues = 1;
570 if (!pci_enable_msi(adapter->pdev))
571 adapter->flags |= IGB_FLAG_HAS_MSI;
572 out:
573 /* Notify the stack of the (possibly) reduced Tx Queue count. */
574 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
575 return;
576 }
577
578 /**
579 * igb_request_irq - initialize interrupts
580 *
581 * Attempts to configure interrupts using the best available
582 * capabilities of the hardware and kernel.
583 **/
584 static int igb_request_irq(struct igb_adapter *adapter)
585 {
586 struct net_device *netdev = adapter->netdev;
587 struct e1000_hw *hw = &adapter->hw;
588 int err = 0;
589
590 if (adapter->msix_entries) {
591 err = igb_request_msix(adapter);
592 if (!err)
593 goto request_done;
594 /* fall back to MSI */
595 igb_reset_interrupt_capability(adapter);
596 if (!pci_enable_msi(adapter->pdev))
597 adapter->flags |= IGB_FLAG_HAS_MSI;
598 igb_free_all_tx_resources(adapter);
599 igb_free_all_rx_resources(adapter);
600 adapter->num_rx_queues = 1;
601 igb_alloc_queues(adapter);
602 } else {
603 switch (hw->mac.type) {
604 case e1000_82575:
605 wr32(E1000_MSIXBM(0),
606 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
607 break;
608 case e1000_82576:
609 wr32(E1000_IVAR0, E1000_IVAR_VALID);
610 break;
611 default:
612 break;
613 }
614 }
615
616 if (adapter->flags & IGB_FLAG_HAS_MSI) {
617 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
618 netdev->name, netdev);
619 if (!err)
620 goto request_done;
621 /* fall back to legacy interrupts */
622 igb_reset_interrupt_capability(adapter);
623 adapter->flags &= ~IGB_FLAG_HAS_MSI;
624 }
625
626 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
627 netdev->name, netdev);
628
629 if (err)
630 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
631 err);
632
633 request_done:
634 return err;
635 }
636
637 static void igb_free_irq(struct igb_adapter *adapter)
638 {
639 struct net_device *netdev = adapter->netdev;
640
641 if (adapter->msix_entries) {
642 int vector = 0, i;
643
644 for (i = 0; i < adapter->num_tx_queues; i++)
645 free_irq(adapter->msix_entries[vector++].vector,
646 &(adapter->tx_ring[i]));
647 for (i = 0; i < adapter->num_rx_queues; i++)
648 free_irq(adapter->msix_entries[vector++].vector,
649 &(adapter->rx_ring[i]));
650
651 free_irq(adapter->msix_entries[vector++].vector, netdev);
652 return;
653 }
654
655 free_irq(adapter->pdev->irq, netdev);
656 }
657
658 /**
659 * igb_irq_disable - Mask off interrupt generation on the NIC
660 * @adapter: board private structure
661 **/
662 static void igb_irq_disable(struct igb_adapter *adapter)
663 {
664 struct e1000_hw *hw = &adapter->hw;
665
666 if (adapter->msix_entries) {
667 wr32(E1000_EIAM, 0);
668 wr32(E1000_EIMC, ~0);
669 wr32(E1000_EIAC, 0);
670 }
671
672 wr32(E1000_IAM, 0);
673 wr32(E1000_IMC, ~0);
674 wrfl();
675 synchronize_irq(adapter->pdev->irq);
676 }
677
678 /**
679 * igb_irq_enable - Enable default interrupt generation settings
680 * @adapter: board private structure
681 **/
682 static void igb_irq_enable(struct igb_adapter *adapter)
683 {
684 struct e1000_hw *hw = &adapter->hw;
685
686 if (adapter->msix_entries) {
687 wr32(E1000_EIAC, adapter->eims_enable_mask);
688 wr32(E1000_EIAM, adapter->eims_enable_mask);
689 wr32(E1000_EIMS, adapter->eims_enable_mask);
690 wr32(E1000_IMS, E1000_IMS_LSC);
691 } else {
692 wr32(E1000_IMS, IMS_ENABLE_MASK);
693 wr32(E1000_IAM, IMS_ENABLE_MASK);
694 }
695 }
696
697 static void igb_update_mng_vlan(struct igb_adapter *adapter)
698 {
699 struct net_device *netdev = adapter->netdev;
700 u16 vid = adapter->hw.mng_cookie.vlan_id;
701 u16 old_vid = adapter->mng_vlan_id;
702 if (adapter->vlgrp) {
703 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
704 if (adapter->hw.mng_cookie.status &
705 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
706 igb_vlan_rx_add_vid(netdev, vid);
707 adapter->mng_vlan_id = vid;
708 } else
709 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
710
711 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
712 (vid != old_vid) &&
713 !vlan_group_get_device(adapter->vlgrp, old_vid))
714 igb_vlan_rx_kill_vid(netdev, old_vid);
715 } else
716 adapter->mng_vlan_id = vid;
717 }
718 }
719
720 /**
721 * igb_release_hw_control - release control of the h/w to f/w
722 * @adapter: address of board private structure
723 *
724 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
725 * For ASF and Pass Through versions of f/w this means that the
726 * driver is no longer loaded.
727 *
728 **/
729 static void igb_release_hw_control(struct igb_adapter *adapter)
730 {
731 struct e1000_hw *hw = &adapter->hw;
732 u32 ctrl_ext;
733
734 /* Let firmware take over control of h/w */
735 ctrl_ext = rd32(E1000_CTRL_EXT);
736 wr32(E1000_CTRL_EXT,
737 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
738 }
739
740
741 /**
742 * igb_get_hw_control - get control of the h/w from f/w
743 * @adapter: address of board private structure
744 *
745 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
746 * For ASF and Pass Through versions of f/w this means that
747 * the driver is loaded.
748 *
749 **/
750 static void igb_get_hw_control(struct igb_adapter *adapter)
751 {
752 struct e1000_hw *hw = &adapter->hw;
753 u32 ctrl_ext;
754
755 /* Let firmware know the driver has taken over */
756 ctrl_ext = rd32(E1000_CTRL_EXT);
757 wr32(E1000_CTRL_EXT,
758 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
759 }
760
761 /**
762 * igb_configure - configure the hardware for RX and TX
763 * @adapter: private board structure
764 **/
765 static void igb_configure(struct igb_adapter *adapter)
766 {
767 struct net_device *netdev = adapter->netdev;
768 int i;
769
770 igb_get_hw_control(adapter);
771 igb_set_multi(netdev);
772
773 igb_restore_vlan(adapter);
774
775 igb_configure_tx(adapter);
776 igb_setup_rctl(adapter);
777 igb_configure_rx(adapter);
778
779 igb_rx_fifo_flush_82575(&adapter->hw);
780
781 /* call IGB_DESC_UNUSED which always leaves
782 * at least 1 descriptor unused to make sure
783 * next_to_use != next_to_clean */
784 for (i = 0; i < adapter->num_rx_queues; i++) {
785 struct igb_ring *ring = &adapter->rx_ring[i];
786 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
787 }
788
789
790 adapter->tx_queue_len = netdev->tx_queue_len;
791 }
792
793
794 /**
795 * igb_up - Open the interface and prepare it to handle traffic
796 * @adapter: board private structure
797 **/
798
799 int igb_up(struct igb_adapter *adapter)
800 {
801 struct e1000_hw *hw = &adapter->hw;
802 int i;
803
804 /* hardware has been reset, we need to reload some things */
805 igb_configure(adapter);
806
807 clear_bit(__IGB_DOWN, &adapter->state);
808
809 for (i = 0; i < adapter->num_rx_queues; i++)
810 napi_enable(&adapter->rx_ring[i].napi);
811 if (adapter->msix_entries)
812 igb_configure_msix(adapter);
813
814 /* Clear any pending interrupts. */
815 rd32(E1000_ICR);
816 igb_irq_enable(adapter);
817
818 /* Fire a link change interrupt to start the watchdog. */
819 wr32(E1000_ICS, E1000_ICS_LSC);
820 return 0;
821 }
822
823 void igb_down(struct igb_adapter *adapter)
824 {
825 struct e1000_hw *hw = &adapter->hw;
826 struct net_device *netdev = adapter->netdev;
827 u32 tctl, rctl;
828 int i;
829
830 /* signal that we're down so the interrupt handler does not
831 * reschedule our watchdog timer */
832 set_bit(__IGB_DOWN, &adapter->state);
833
834 /* disable receives in the hardware */
835 rctl = rd32(E1000_RCTL);
836 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
837 /* flush and sleep below */
838
839 netif_tx_stop_all_queues(netdev);
840
841 /* disable transmits in the hardware */
842 tctl = rd32(E1000_TCTL);
843 tctl &= ~E1000_TCTL_EN;
844 wr32(E1000_TCTL, tctl);
845 /* flush both disables and wait for them to finish */
846 wrfl();
847 msleep(10);
848
849 for (i = 0; i < adapter->num_rx_queues; i++)
850 napi_disable(&adapter->rx_ring[i].napi);
851
852 igb_irq_disable(adapter);
853
854 del_timer_sync(&adapter->watchdog_timer);
855 del_timer_sync(&adapter->phy_info_timer);
856
857 netdev->tx_queue_len = adapter->tx_queue_len;
858 netif_carrier_off(netdev);
859 adapter->link_speed = 0;
860 adapter->link_duplex = 0;
861
862 if (!pci_channel_offline(adapter->pdev))
863 igb_reset(adapter);
864 igb_clean_all_tx_rings(adapter);
865 igb_clean_all_rx_rings(adapter);
866 }
867
868 void igb_reinit_locked(struct igb_adapter *adapter)
869 {
870 WARN_ON(in_interrupt());
871 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
872 msleep(1);
873 igb_down(adapter);
874 igb_up(adapter);
875 clear_bit(__IGB_RESETTING, &adapter->state);
876 }
877
878 void igb_reset(struct igb_adapter *adapter)
879 {
880 struct e1000_hw *hw = &adapter->hw;
881 struct e1000_mac_info *mac = &hw->mac;
882 struct e1000_fc_info *fc = &hw->fc;
883 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
884 u16 hwm;
885
886 /* Repartition Pba for greater than 9k mtu
887 * To take effect CTRL.RST is required.
888 */
889 if (mac->type != e1000_82576) {
890 pba = E1000_PBA_34K;
891 }
892 else {
893 pba = E1000_PBA_64K;
894 }
895
896 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
897 (mac->type < e1000_82576)) {
898 /* adjust PBA for jumbo frames */
899 wr32(E1000_PBA, pba);
900
901 /* To maintain wire speed transmits, the Tx FIFO should be
902 * large enough to accommodate two full transmit packets,
903 * rounded up to the next 1KB and expressed in KB. Likewise,
904 * the Rx FIFO should be large enough to accommodate at least
905 * one full receive packet and is similarly rounded up and
906 * expressed in KB. */
907 pba = rd32(E1000_PBA);
908 /* upper 16 bits has Tx packet buffer allocation size in KB */
909 tx_space = pba >> 16;
910 /* lower 16 bits has Rx packet buffer allocation size in KB */
911 pba &= 0xffff;
912 /* the tx fifo also stores 16 bytes of information about the tx
913 * but don't include ethernet FCS because hardware appends it */
914 min_tx_space = (adapter->max_frame_size +
915 sizeof(struct e1000_tx_desc) -
916 ETH_FCS_LEN) * 2;
917 min_tx_space = ALIGN(min_tx_space, 1024);
918 min_tx_space >>= 10;
919 /* software strips receive CRC, so leave room for it */
920 min_rx_space = adapter->max_frame_size;
921 min_rx_space = ALIGN(min_rx_space, 1024);
922 min_rx_space >>= 10;
923
924 /* If current Tx allocation is less than the min Tx FIFO size,
925 * and the min Tx FIFO size is less than the current Rx FIFO
926 * allocation, take space away from current Rx allocation */
927 if (tx_space < min_tx_space &&
928 ((min_tx_space - tx_space) < pba)) {
929 pba = pba - (min_tx_space - tx_space);
930
931 /* if short on rx space, rx wins and must trump tx
932 * adjustment */
933 if (pba < min_rx_space)
934 pba = min_rx_space;
935 }
936 wr32(E1000_PBA, pba);
937 }
938
939 /* flow control settings */
940 /* The high water mark must be low enough to fit one full frame
941 * (or the size used for early receive) above it in the Rx FIFO.
942 * Set it to the lower of:
943 * - 90% of the Rx FIFO size, or
944 * - the full Rx FIFO size minus one full frame */
945 hwm = min(((pba << 10) * 9 / 10),
946 ((pba << 10) - 2 * adapter->max_frame_size));
947
948 if (mac->type < e1000_82576) {
949 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
950 fc->low_water = fc->high_water - 8;
951 } else {
952 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
953 fc->low_water = fc->high_water - 16;
954 }
955 fc->pause_time = 0xFFFF;
956 fc->send_xon = 1;
957 fc->type = fc->original_type;
958
959 /* Allow time for pending master requests to run */
960 adapter->hw.mac.ops.reset_hw(&adapter->hw);
961 wr32(E1000_WUC, 0);
962
963 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
964 dev_err(&adapter->pdev->dev, "Hardware Error\n");
965
966 igb_update_mng_vlan(adapter);
967
968 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
969 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
970
971 igb_reset_adaptive(&adapter->hw);
972 igb_get_phy_info(&adapter->hw);
973 }
974
975 /**
976 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
977 * @pdev: PCI device information struct
978 *
979 * Returns true if an adapter needs ioport resources
980 **/
981 static int igb_is_need_ioport(struct pci_dev *pdev)
982 {
983 switch (pdev->device) {
984 /* Currently there are no adapters that need ioport resources */
985 default:
986 return false;
987 }
988 }
989
990 static const struct net_device_ops igb_netdev_ops = {
991 .ndo_open = igb_open,
992 .ndo_stop = igb_close,
993 .ndo_start_xmit = igb_xmit_frame_adv,
994 .ndo_get_stats = igb_get_stats,
995 .ndo_set_multicast_list = igb_set_multi,
996 .ndo_set_mac_address = igb_set_mac,
997 .ndo_change_mtu = igb_change_mtu,
998 .ndo_do_ioctl = igb_ioctl,
999 .ndo_tx_timeout = igb_tx_timeout,
1000 .ndo_validate_addr = eth_validate_addr,
1001 .ndo_vlan_rx_register = igb_vlan_rx_register,
1002 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1003 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1004 #ifdef CONFIG_NET_POLL_CONTROLLER
1005 .ndo_poll_controller = igb_netpoll,
1006 #endif
1007 };
1008
1009 /**
1010 * igb_probe - Device Initialization Routine
1011 * @pdev: PCI device information struct
1012 * @ent: entry in igb_pci_tbl
1013 *
1014 * Returns 0 on success, negative on failure
1015 *
1016 * igb_probe initializes an adapter identified by a pci_dev structure.
1017 * The OS initialization, configuring of the adapter private structure,
1018 * and a hardware reset occur.
1019 **/
1020 static int __devinit igb_probe(struct pci_dev *pdev,
1021 const struct pci_device_id *ent)
1022 {
1023 struct net_device *netdev;
1024 struct igb_adapter *adapter;
1025 struct e1000_hw *hw;
1026 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1027 unsigned long mmio_start, mmio_len;
1028 int i, err, pci_using_dac;
1029 u16 eeprom_data = 0;
1030 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1031 u32 part_num;
1032 int bars, need_ioport;
1033
1034 /* do not allocate ioport bars when not needed */
1035 need_ioport = igb_is_need_ioport(pdev);
1036 if (need_ioport) {
1037 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
1038 err = pci_enable_device(pdev);
1039 } else {
1040 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1041 err = pci_enable_device_mem(pdev);
1042 }
1043 if (err)
1044 return err;
1045
1046 pci_using_dac = 0;
1047 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1048 if (!err) {
1049 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1050 if (!err)
1051 pci_using_dac = 1;
1052 } else {
1053 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1054 if (err) {
1055 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1056 if (err) {
1057 dev_err(&pdev->dev, "No usable DMA "
1058 "configuration, aborting\n");
1059 goto err_dma;
1060 }
1061 }
1062 }
1063
1064 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
1065 if (err)
1066 goto err_pci_reg;
1067
1068 err = pci_enable_pcie_error_reporting(pdev);
1069 if (err) {
1070 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1071 "0x%x\n", err);
1072 /* non-fatal, continue */
1073 }
1074
1075 pci_set_master(pdev);
1076 pci_save_state(pdev);
1077
1078 err = -ENOMEM;
1079 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
1080 if (!netdev)
1081 goto err_alloc_etherdev;
1082
1083 SET_NETDEV_DEV(netdev, &pdev->dev);
1084
1085 pci_set_drvdata(pdev, netdev);
1086 adapter = netdev_priv(netdev);
1087 adapter->netdev = netdev;
1088 adapter->pdev = pdev;
1089 hw = &adapter->hw;
1090 hw->back = adapter;
1091 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1092 adapter->bars = bars;
1093 adapter->need_ioport = need_ioport;
1094
1095 mmio_start = pci_resource_start(pdev, 0);
1096 mmio_len = pci_resource_len(pdev, 0);
1097
1098 err = -EIO;
1099 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1100 if (!adapter->hw.hw_addr)
1101 goto err_ioremap;
1102
1103 netdev->netdev_ops = &igb_netdev_ops;
1104 igb_set_ethtool_ops(netdev);
1105 netdev->watchdog_timeo = 5 * HZ;
1106
1107 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1108
1109 netdev->mem_start = mmio_start;
1110 netdev->mem_end = mmio_start + mmio_len;
1111
1112 /* PCI config space info */
1113 hw->vendor_id = pdev->vendor;
1114 hw->device_id = pdev->device;
1115 hw->revision_id = pdev->revision;
1116 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1117 hw->subsystem_device_id = pdev->subsystem_device;
1118
1119 /* setup the private structure */
1120 hw->back = adapter;
1121 /* Copy the default MAC, PHY and NVM function pointers */
1122 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1123 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1124 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1125 /* Initialize skew-specific constants */
1126 err = ei->get_invariants(hw);
1127 if (err)
1128 goto err_hw_init;
1129
1130 err = igb_sw_init(adapter);
1131 if (err)
1132 goto err_sw_init;
1133
1134 igb_get_bus_info_pcie(hw);
1135
1136 /* set flags */
1137 switch (hw->mac.type) {
1138 case e1000_82575:
1139 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1140 break;
1141 case e1000_82576:
1142 default:
1143 break;
1144 }
1145
1146 hw->phy.autoneg_wait_to_complete = false;
1147 hw->mac.adaptive_ifs = true;
1148
1149 /* Copper options */
1150 if (hw->phy.media_type == e1000_media_type_copper) {
1151 hw->phy.mdix = AUTO_ALL_MODES;
1152 hw->phy.disable_polarity_correction = false;
1153 hw->phy.ms_type = e1000_ms_hw_default;
1154 }
1155
1156 if (igb_check_reset_block(hw))
1157 dev_info(&pdev->dev,
1158 "PHY reset is blocked due to SOL/IDER session.\n");
1159
1160 netdev->features = NETIF_F_SG |
1161 NETIF_F_HW_CSUM |
1162 NETIF_F_HW_VLAN_TX |
1163 NETIF_F_HW_VLAN_RX |
1164 NETIF_F_HW_VLAN_FILTER;
1165
1166 netdev->features |= NETIF_F_TSO;
1167 netdev->features |= NETIF_F_TSO6;
1168
1169 #ifdef CONFIG_IGB_LRO
1170 netdev->features |= NETIF_F_LRO;
1171 #endif
1172
1173 netdev->vlan_features |= NETIF_F_TSO;
1174 netdev->vlan_features |= NETIF_F_TSO6;
1175 netdev->vlan_features |= NETIF_F_HW_CSUM;
1176 netdev->vlan_features |= NETIF_F_SG;
1177
1178 if (pci_using_dac)
1179 netdev->features |= NETIF_F_HIGHDMA;
1180
1181 netdev->features |= NETIF_F_LLTX;
1182 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1183
1184 /* before reading the NVM, reset the controller to put the device in a
1185 * known good starting state */
1186 hw->mac.ops.reset_hw(hw);
1187
1188 /* make sure the NVM is good */
1189 if (igb_validate_nvm_checksum(hw) < 0) {
1190 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1191 err = -EIO;
1192 goto err_eeprom;
1193 }
1194
1195 /* copy the MAC address out of the NVM */
1196 if (hw->mac.ops.read_mac_addr(hw))
1197 dev_err(&pdev->dev, "NVM Read Error\n");
1198
1199 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1200 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1201
1202 if (!is_valid_ether_addr(netdev->perm_addr)) {
1203 dev_err(&pdev->dev, "Invalid MAC Address\n");
1204 err = -EIO;
1205 goto err_eeprom;
1206 }
1207
1208 init_timer(&adapter->watchdog_timer);
1209 adapter->watchdog_timer.function = &igb_watchdog;
1210 adapter->watchdog_timer.data = (unsigned long) adapter;
1211
1212 init_timer(&adapter->phy_info_timer);
1213 adapter->phy_info_timer.function = &igb_update_phy_info;
1214 adapter->phy_info_timer.data = (unsigned long) adapter;
1215
1216 INIT_WORK(&adapter->reset_task, igb_reset_task);
1217 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1218
1219 /* Initialize link & ring properties that are user-changeable */
1220 adapter->tx_ring->count = 256;
1221 for (i = 0; i < adapter->num_tx_queues; i++)
1222 adapter->tx_ring[i].count = adapter->tx_ring->count;
1223 adapter->rx_ring->count = 256;
1224 for (i = 0; i < adapter->num_rx_queues; i++)
1225 adapter->rx_ring[i].count = adapter->rx_ring->count;
1226
1227 adapter->fc_autoneg = true;
1228 hw->mac.autoneg = true;
1229 hw->phy.autoneg_advertised = 0x2f;
1230
1231 hw->fc.original_type = e1000_fc_default;
1232 hw->fc.type = e1000_fc_default;
1233
1234 adapter->itr_setting = 3;
1235 adapter->itr = IGB_START_ITR;
1236
1237 igb_validate_mdi_setting(hw);
1238
1239 adapter->rx_csum = 1;
1240
1241 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1242 * enable the ACPI Magic Packet filter
1243 */
1244
1245 if (hw->bus.func == 0 ||
1246 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1247 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1248 &eeprom_data);
1249
1250 if (eeprom_data & eeprom_apme_mask)
1251 adapter->eeprom_wol |= E1000_WUFC_MAG;
1252
1253 /* now that we have the eeprom settings, apply the special cases where
1254 * the eeprom may be wrong or the board simply won't support wake on
1255 * lan on a particular port */
1256 switch (pdev->device) {
1257 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1258 adapter->eeprom_wol = 0;
1259 break;
1260 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1261 case E1000_DEV_ID_82576_FIBER:
1262 case E1000_DEV_ID_82576_SERDES:
1263 /* Wake events only supported on port A for dual fiber
1264 * regardless of eeprom setting */
1265 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1266 adapter->eeprom_wol = 0;
1267 break;
1268 }
1269
1270 /* initialize the wol settings based on the eeprom settings */
1271 adapter->wol = adapter->eeprom_wol;
1272 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1273
1274 /* reset the hardware with the new settings */
1275 igb_reset(adapter);
1276
1277 /* let the f/w know that the h/w is now under the control of the
1278 * driver. */
1279 igb_get_hw_control(adapter);
1280
1281 /* tell the stack to leave us alone until igb_open() is called */
1282 netif_carrier_off(netdev);
1283 netif_tx_stop_all_queues(netdev);
1284
1285 strcpy(netdev->name, "eth%d");
1286 err = register_netdev(netdev);
1287 if (err)
1288 goto err_register;
1289
1290 #ifdef CONFIG_IGB_DCA
1291 if (dca_add_requester(&pdev->dev) == 0) {
1292 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1293 dev_info(&pdev->dev, "DCA enabled\n");
1294 /* Always use CB2 mode, difference is masked
1295 * in the CB driver. */
1296 wr32(E1000_DCA_CTRL, 2);
1297 igb_setup_dca(adapter);
1298 }
1299 #endif
1300
1301 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1302 /* print bus type/speed/width info */
1303 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1304 netdev->name,
1305 ((hw->bus.speed == e1000_bus_speed_2500)
1306 ? "2.5Gb/s" : "unknown"),
1307 ((hw->bus.width == e1000_bus_width_pcie_x4)
1308 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1309 ? "Width x1" : "unknown"),
1310 netdev->dev_addr);
1311
1312 igb_read_part_num(hw, &part_num);
1313 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1314 (part_num >> 8), (part_num & 0xff));
1315
1316 dev_info(&pdev->dev,
1317 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1318 adapter->msix_entries ? "MSI-X" :
1319 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1320 adapter->num_rx_queues, adapter->num_tx_queues);
1321
1322 return 0;
1323
1324 err_register:
1325 igb_release_hw_control(adapter);
1326 err_eeprom:
1327 if (!igb_check_reset_block(hw))
1328 igb_reset_phy(hw);
1329
1330 if (hw->flash_address)
1331 iounmap(hw->flash_address);
1332
1333 igb_remove_device(hw);
1334 igb_free_queues(adapter);
1335 err_sw_init:
1336 err_hw_init:
1337 iounmap(hw->hw_addr);
1338 err_ioremap:
1339 free_netdev(netdev);
1340 err_alloc_etherdev:
1341 pci_release_selected_regions(pdev, bars);
1342 err_pci_reg:
1343 err_dma:
1344 pci_disable_device(pdev);
1345 return err;
1346 }
1347
1348 /**
1349 * igb_remove - Device Removal Routine
1350 * @pdev: PCI device information struct
1351 *
1352 * igb_remove is called by the PCI subsystem to alert the driver
1353 * that it should release a PCI device. The could be caused by a
1354 * Hot-Plug event, or because the driver is going to be removed from
1355 * memory.
1356 **/
1357 static void __devexit igb_remove(struct pci_dev *pdev)
1358 {
1359 struct net_device *netdev = pci_get_drvdata(pdev);
1360 struct igb_adapter *adapter = netdev_priv(netdev);
1361 #ifdef CONFIG_IGB_DCA
1362 struct e1000_hw *hw = &adapter->hw;
1363 #endif
1364 int err;
1365
1366 /* flush_scheduled work may reschedule our watchdog task, so
1367 * explicitly disable watchdog tasks from being rescheduled */
1368 set_bit(__IGB_DOWN, &adapter->state);
1369 del_timer_sync(&adapter->watchdog_timer);
1370 del_timer_sync(&adapter->phy_info_timer);
1371
1372 flush_scheduled_work();
1373
1374 #ifdef CONFIG_IGB_DCA
1375 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1376 dev_info(&pdev->dev, "DCA disabled\n");
1377 dca_remove_requester(&pdev->dev);
1378 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1379 wr32(E1000_DCA_CTRL, 1);
1380 }
1381 #endif
1382
1383 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1384 * would have already happened in close and is redundant. */
1385 igb_release_hw_control(adapter);
1386
1387 unregister_netdev(netdev);
1388
1389 if (!igb_check_reset_block(&adapter->hw))
1390 igb_reset_phy(&adapter->hw);
1391
1392 igb_remove_device(&adapter->hw);
1393 igb_reset_interrupt_capability(adapter);
1394
1395 igb_free_queues(adapter);
1396
1397 iounmap(adapter->hw.hw_addr);
1398 if (adapter->hw.flash_address)
1399 iounmap(adapter->hw.flash_address);
1400 pci_release_selected_regions(pdev, adapter->bars);
1401
1402 free_netdev(netdev);
1403
1404 err = pci_disable_pcie_error_reporting(pdev);
1405 if (err)
1406 dev_err(&pdev->dev,
1407 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1408
1409 pci_disable_device(pdev);
1410 }
1411
1412 /**
1413 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1414 * @adapter: board private structure to initialize
1415 *
1416 * igb_sw_init initializes the Adapter private data structure.
1417 * Fields are initialized based on PCI device information and
1418 * OS network device settings (MTU size).
1419 **/
1420 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1421 {
1422 struct e1000_hw *hw = &adapter->hw;
1423 struct net_device *netdev = adapter->netdev;
1424 struct pci_dev *pdev = adapter->pdev;
1425
1426 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1427
1428 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1429 adapter->rx_ring_count = IGB_DEFAULT_RXD;
1430 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1431 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1432 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1433 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1434
1435 /* Number of supported queues. */
1436 /* Having more queues than CPUs doesn't make sense. */
1437 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
1438 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
1439
1440 /* This call may decrease the number of queues depending on
1441 * interrupt mode. */
1442 igb_set_interrupt_capability(adapter);
1443
1444 if (igb_alloc_queues(adapter)) {
1445 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1446 return -ENOMEM;
1447 }
1448
1449 /* Explicitly disable IRQ since the NIC can be in any state. */
1450 igb_irq_disable(adapter);
1451
1452 set_bit(__IGB_DOWN, &adapter->state);
1453 return 0;
1454 }
1455
1456 /**
1457 * igb_open - Called when a network interface is made active
1458 * @netdev: network interface device structure
1459 *
1460 * Returns 0 on success, negative value on failure
1461 *
1462 * The open entry point is called when a network interface is made
1463 * active by the system (IFF_UP). At this point all resources needed
1464 * for transmit and receive operations are allocated, the interrupt
1465 * handler is registered with the OS, the watchdog timer is started,
1466 * and the stack is notified that the interface is ready.
1467 **/
1468 static int igb_open(struct net_device *netdev)
1469 {
1470 struct igb_adapter *adapter = netdev_priv(netdev);
1471 struct e1000_hw *hw = &adapter->hw;
1472 int err;
1473 int i;
1474
1475 /* disallow open during test */
1476 if (test_bit(__IGB_TESTING, &adapter->state))
1477 return -EBUSY;
1478
1479 /* allocate transmit descriptors */
1480 err = igb_setup_all_tx_resources(adapter);
1481 if (err)
1482 goto err_setup_tx;
1483
1484 /* allocate receive descriptors */
1485 err = igb_setup_all_rx_resources(adapter);
1486 if (err)
1487 goto err_setup_rx;
1488
1489 /* e1000_power_up_phy(adapter); */
1490
1491 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1492 if ((adapter->hw.mng_cookie.status &
1493 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1494 igb_update_mng_vlan(adapter);
1495
1496 /* before we allocate an interrupt, we must be ready to handle it.
1497 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1498 * as soon as we call pci_request_irq, so we have to setup our
1499 * clean_rx handler before we do so. */
1500 igb_configure(adapter);
1501
1502 err = igb_request_irq(adapter);
1503 if (err)
1504 goto err_req_irq;
1505
1506 /* From here on the code is the same as igb_up() */
1507 clear_bit(__IGB_DOWN, &adapter->state);
1508
1509 for (i = 0; i < adapter->num_rx_queues; i++)
1510 napi_enable(&adapter->rx_ring[i].napi);
1511
1512 /* Clear any pending interrupts. */
1513 rd32(E1000_ICR);
1514
1515 igb_irq_enable(adapter);
1516
1517 netif_tx_start_all_queues(netdev);
1518
1519 /* Fire a link status change interrupt to start the watchdog. */
1520 wr32(E1000_ICS, E1000_ICS_LSC);
1521
1522 return 0;
1523
1524 err_req_irq:
1525 igb_release_hw_control(adapter);
1526 /* e1000_power_down_phy(adapter); */
1527 igb_free_all_rx_resources(adapter);
1528 err_setup_rx:
1529 igb_free_all_tx_resources(adapter);
1530 err_setup_tx:
1531 igb_reset(adapter);
1532
1533 return err;
1534 }
1535
1536 /**
1537 * igb_close - Disables a network interface
1538 * @netdev: network interface device structure
1539 *
1540 * Returns 0, this is not allowed to fail
1541 *
1542 * The close entry point is called when an interface is de-activated
1543 * by the OS. The hardware is still under the driver's control, but
1544 * needs to be disabled. A global MAC reset is issued to stop the
1545 * hardware, and all transmit and receive resources are freed.
1546 **/
1547 static int igb_close(struct net_device *netdev)
1548 {
1549 struct igb_adapter *adapter = netdev_priv(netdev);
1550
1551 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1552 igb_down(adapter);
1553
1554 igb_free_irq(adapter);
1555
1556 igb_free_all_tx_resources(adapter);
1557 igb_free_all_rx_resources(adapter);
1558
1559 /* kill manageability vlan ID if supported, but not if a vlan with
1560 * the same ID is registered on the host OS (let 8021q kill it) */
1561 if ((adapter->hw.mng_cookie.status &
1562 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1563 !(adapter->vlgrp &&
1564 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1565 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1566
1567 return 0;
1568 }
1569
1570 /**
1571 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1572 * @adapter: board private structure
1573 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1574 *
1575 * Return 0 on success, negative on failure
1576 **/
1577
1578 int igb_setup_tx_resources(struct igb_adapter *adapter,
1579 struct igb_ring *tx_ring)
1580 {
1581 struct pci_dev *pdev = adapter->pdev;
1582 int size;
1583
1584 size = sizeof(struct igb_buffer) * tx_ring->count;
1585 tx_ring->buffer_info = vmalloc(size);
1586 if (!tx_ring->buffer_info)
1587 goto err;
1588 memset(tx_ring->buffer_info, 0, size);
1589
1590 /* round up to nearest 4K */
1591 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
1592 tx_ring->size = ALIGN(tx_ring->size, 4096);
1593
1594 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1595 &tx_ring->dma);
1596
1597 if (!tx_ring->desc)
1598 goto err;
1599
1600 tx_ring->adapter = adapter;
1601 tx_ring->next_to_use = 0;
1602 tx_ring->next_to_clean = 0;
1603 return 0;
1604
1605 err:
1606 vfree(tx_ring->buffer_info);
1607 dev_err(&adapter->pdev->dev,
1608 "Unable to allocate memory for the transmit descriptor ring\n");
1609 return -ENOMEM;
1610 }
1611
1612 /**
1613 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1614 * (Descriptors) for all queues
1615 * @adapter: board private structure
1616 *
1617 * Return 0 on success, negative on failure
1618 **/
1619 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1620 {
1621 int i, err = 0;
1622 int r_idx;
1623
1624 for (i = 0; i < adapter->num_tx_queues; i++) {
1625 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1626 if (err) {
1627 dev_err(&adapter->pdev->dev,
1628 "Allocation for Tx Queue %u failed\n", i);
1629 for (i--; i >= 0; i--)
1630 igb_free_tx_resources(&adapter->tx_ring[i]);
1631 break;
1632 }
1633 }
1634
1635 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1636 r_idx = i % adapter->num_tx_queues;
1637 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1638 }
1639 return err;
1640 }
1641
1642 /**
1643 * igb_configure_tx - Configure transmit Unit after Reset
1644 * @adapter: board private structure
1645 *
1646 * Configure the Tx unit of the MAC after a reset.
1647 **/
1648 static void igb_configure_tx(struct igb_adapter *adapter)
1649 {
1650 u64 tdba;
1651 struct e1000_hw *hw = &adapter->hw;
1652 u32 tctl;
1653 u32 txdctl, txctrl;
1654 int i, j;
1655
1656 for (i = 0; i < adapter->num_tx_queues; i++) {
1657 struct igb_ring *ring = &(adapter->tx_ring[i]);
1658 j = ring->reg_idx;
1659 wr32(E1000_TDLEN(j),
1660 ring->count * sizeof(struct e1000_tx_desc));
1661 tdba = ring->dma;
1662 wr32(E1000_TDBAL(j),
1663 tdba & 0x00000000ffffffffULL);
1664 wr32(E1000_TDBAH(j), tdba >> 32);
1665
1666 ring->head = E1000_TDH(j);
1667 ring->tail = E1000_TDT(j);
1668 writel(0, hw->hw_addr + ring->tail);
1669 writel(0, hw->hw_addr + ring->head);
1670 txdctl = rd32(E1000_TXDCTL(j));
1671 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1672 wr32(E1000_TXDCTL(j), txdctl);
1673
1674 /* Turn off Relaxed Ordering on head write-backs. The
1675 * writebacks MUST be delivered in order or it will
1676 * completely screw up our bookeeping.
1677 */
1678 txctrl = rd32(E1000_DCA_TXCTRL(j));
1679 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1680 wr32(E1000_DCA_TXCTRL(j), txctrl);
1681 }
1682
1683
1684
1685 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1686
1687 /* Program the Transmit Control Register */
1688
1689 tctl = rd32(E1000_TCTL);
1690 tctl &= ~E1000_TCTL_CT;
1691 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1692 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1693
1694 igb_config_collision_dist(hw);
1695
1696 /* Setup Transmit Descriptor Settings for eop descriptor */
1697 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1698
1699 /* Enable transmits */
1700 tctl |= E1000_TCTL_EN;
1701
1702 wr32(E1000_TCTL, tctl);
1703 }
1704
1705 /**
1706 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1707 * @adapter: board private structure
1708 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1709 *
1710 * Returns 0 on success, negative on failure
1711 **/
1712
1713 int igb_setup_rx_resources(struct igb_adapter *adapter,
1714 struct igb_ring *rx_ring)
1715 {
1716 struct pci_dev *pdev = adapter->pdev;
1717 int size, desc_len;
1718
1719 #ifdef CONFIG_IGB_LRO
1720 size = sizeof(struct net_lro_desc) * MAX_LRO_DESCRIPTORS;
1721 rx_ring->lro_mgr.lro_arr = vmalloc(size);
1722 if (!rx_ring->lro_mgr.lro_arr)
1723 goto err;
1724 memset(rx_ring->lro_mgr.lro_arr, 0, size);
1725 #endif
1726
1727 size = sizeof(struct igb_buffer) * rx_ring->count;
1728 rx_ring->buffer_info = vmalloc(size);
1729 if (!rx_ring->buffer_info)
1730 goto err;
1731 memset(rx_ring->buffer_info, 0, size);
1732
1733 desc_len = sizeof(union e1000_adv_rx_desc);
1734
1735 /* Round up to nearest 4K */
1736 rx_ring->size = rx_ring->count * desc_len;
1737 rx_ring->size = ALIGN(rx_ring->size, 4096);
1738
1739 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1740 &rx_ring->dma);
1741
1742 if (!rx_ring->desc)
1743 goto err;
1744
1745 rx_ring->next_to_clean = 0;
1746 rx_ring->next_to_use = 0;
1747
1748 rx_ring->adapter = adapter;
1749
1750 return 0;
1751
1752 err:
1753 #ifdef CONFIG_IGB_LRO
1754 vfree(rx_ring->lro_mgr.lro_arr);
1755 rx_ring->lro_mgr.lro_arr = NULL;
1756 #endif
1757 vfree(rx_ring->buffer_info);
1758 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1759 "the receive descriptor ring\n");
1760 return -ENOMEM;
1761 }
1762
1763 /**
1764 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1765 * (Descriptors) for all queues
1766 * @adapter: board private structure
1767 *
1768 * Return 0 on success, negative on failure
1769 **/
1770 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1771 {
1772 int i, err = 0;
1773
1774 for (i = 0; i < adapter->num_rx_queues; i++) {
1775 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1776 if (err) {
1777 dev_err(&adapter->pdev->dev,
1778 "Allocation for Rx Queue %u failed\n", i);
1779 for (i--; i >= 0; i--)
1780 igb_free_rx_resources(&adapter->rx_ring[i]);
1781 break;
1782 }
1783 }
1784
1785 return err;
1786 }
1787
1788 /**
1789 * igb_setup_rctl - configure the receive control registers
1790 * @adapter: Board private structure
1791 **/
1792 static void igb_setup_rctl(struct igb_adapter *adapter)
1793 {
1794 struct e1000_hw *hw = &adapter->hw;
1795 u32 rctl;
1796 u32 srrctl = 0;
1797 int i, j;
1798
1799 rctl = rd32(E1000_RCTL);
1800
1801 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1802 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1803
1804 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1805 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1806
1807 /*
1808 * enable stripping of CRC. It's unlikely this will break BMC
1809 * redirection as it did with e1000. Newer features require
1810 * that the HW strips the CRC.
1811 */
1812 rctl |= E1000_RCTL_SECRC;
1813
1814 /*
1815 * disable store bad packets and clear size bits.
1816 */
1817 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
1818
1819 /* enable LPE when to prevent packets larger than max_frame_size */
1820 rctl |= E1000_RCTL_LPE;
1821
1822 /* Setup buffer sizes */
1823 switch (adapter->rx_buffer_len) {
1824 case IGB_RXBUFFER_256:
1825 rctl |= E1000_RCTL_SZ_256;
1826 break;
1827 case IGB_RXBUFFER_512:
1828 rctl |= E1000_RCTL_SZ_512;
1829 break;
1830 default:
1831 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1832 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1833 break;
1834 }
1835
1836 /* 82575 and greater support packet-split where the protocol
1837 * header is placed in skb->data and the packet data is
1838 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1839 * In the case of a non-split, skb->data is linearly filled,
1840 * followed by the page buffers. Therefore, skb->data is
1841 * sized to hold the largest protocol header.
1842 */
1843 /* allocations using alloc_page take too long for regular MTU
1844 * so only enable packet split for jumbo frames */
1845 if (adapter->netdev->mtu > ETH_DATA_LEN) {
1846 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1847 srrctl |= adapter->rx_ps_hdr_size <<
1848 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1849 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1850 } else {
1851 adapter->rx_ps_hdr_size = 0;
1852 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1853 }
1854
1855 for (i = 0; i < adapter->num_rx_queues; i++) {
1856 j = adapter->rx_ring[i].reg_idx;
1857 wr32(E1000_SRRCTL(j), srrctl);
1858 }
1859
1860 wr32(E1000_RCTL, rctl);
1861 }
1862
1863 /**
1864 * igb_configure_rx - Configure receive Unit after Reset
1865 * @adapter: board private structure
1866 *
1867 * Configure the Rx unit of the MAC after a reset.
1868 **/
1869 static void igb_configure_rx(struct igb_adapter *adapter)
1870 {
1871 u64 rdba;
1872 struct e1000_hw *hw = &adapter->hw;
1873 u32 rctl, rxcsum;
1874 u32 rxdctl;
1875 int i, j;
1876
1877 /* disable receives while setting up the descriptors */
1878 rctl = rd32(E1000_RCTL);
1879 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1880 wrfl();
1881 mdelay(10);
1882
1883 if (adapter->itr_setting > 3)
1884 wr32(E1000_ITR, adapter->itr);
1885
1886 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1887 * the Base and Length of the Rx Descriptor Ring */
1888 for (i = 0; i < adapter->num_rx_queues; i++) {
1889 struct igb_ring *ring = &(adapter->rx_ring[i]);
1890 j = ring->reg_idx;
1891 rdba = ring->dma;
1892 wr32(E1000_RDBAL(j),
1893 rdba & 0x00000000ffffffffULL);
1894 wr32(E1000_RDBAH(j), rdba >> 32);
1895 wr32(E1000_RDLEN(j),
1896 ring->count * sizeof(union e1000_adv_rx_desc));
1897
1898 ring->head = E1000_RDH(j);
1899 ring->tail = E1000_RDT(j);
1900 writel(0, hw->hw_addr + ring->tail);
1901 writel(0, hw->hw_addr + ring->head);
1902
1903 rxdctl = rd32(E1000_RXDCTL(j));
1904 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1905 rxdctl &= 0xFFF00000;
1906 rxdctl |= IGB_RX_PTHRESH;
1907 rxdctl |= IGB_RX_HTHRESH << 8;
1908 rxdctl |= IGB_RX_WTHRESH << 16;
1909 wr32(E1000_RXDCTL(j), rxdctl);
1910 #ifdef CONFIG_IGB_LRO
1911 /* Intitial LRO Settings */
1912 ring->lro_mgr.max_aggr = MAX_LRO_AGGR;
1913 ring->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1914 ring->lro_mgr.get_skb_header = igb_get_skb_hdr;
1915 ring->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1916 ring->lro_mgr.dev = adapter->netdev;
1917 ring->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1918 ring->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1919 #endif
1920 }
1921
1922 if (adapter->num_rx_queues > 1) {
1923 u32 random[10];
1924 u32 mrqc;
1925 u32 j, shift;
1926 union e1000_reta {
1927 u32 dword;
1928 u8 bytes[4];
1929 } reta;
1930
1931 get_random_bytes(&random[0], 40);
1932
1933 if (hw->mac.type >= e1000_82576)
1934 shift = 0;
1935 else
1936 shift = 6;
1937 for (j = 0; j < (32 * 4); j++) {
1938 reta.bytes[j & 3] =
1939 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
1940 if ((j & 3) == 3)
1941 writel(reta.dword,
1942 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1943 }
1944 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1945
1946 /* Fill out hash function seeds */
1947 for (j = 0; j < 10; j++)
1948 array_wr32(E1000_RSSRK(0), j, random[j]);
1949
1950 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1951 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1952 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1953 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1954 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1955 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1956 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1957 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1958
1959
1960 wr32(E1000_MRQC, mrqc);
1961
1962 /* Multiqueue and raw packet checksumming are mutually
1963 * exclusive. Note that this not the same as TCP/IP
1964 * checksumming, which works fine. */
1965 rxcsum = rd32(E1000_RXCSUM);
1966 rxcsum |= E1000_RXCSUM_PCSD;
1967 wr32(E1000_RXCSUM, rxcsum);
1968 } else {
1969 /* Enable Receive Checksum Offload for TCP and UDP */
1970 rxcsum = rd32(E1000_RXCSUM);
1971 if (adapter->rx_csum) {
1972 rxcsum |= E1000_RXCSUM_TUOFL;
1973
1974 /* Enable IPv4 payload checksum for UDP fragments
1975 * Must be used in conjunction with packet-split. */
1976 if (adapter->rx_ps_hdr_size)
1977 rxcsum |= E1000_RXCSUM_IPPCSE;
1978 } else {
1979 rxcsum &= ~E1000_RXCSUM_TUOFL;
1980 /* don't need to clear IPPCSE as it defaults to 0 */
1981 }
1982 wr32(E1000_RXCSUM, rxcsum);
1983 }
1984
1985 if (adapter->vlgrp)
1986 wr32(E1000_RLPML,
1987 adapter->max_frame_size + VLAN_TAG_SIZE);
1988 else
1989 wr32(E1000_RLPML, adapter->max_frame_size);
1990
1991 /* Enable Receives */
1992 wr32(E1000_RCTL, rctl);
1993 }
1994
1995 /**
1996 * igb_free_tx_resources - Free Tx Resources per Queue
1997 * @tx_ring: Tx descriptor ring for a specific queue
1998 *
1999 * Free all transmit software resources
2000 **/
2001 void igb_free_tx_resources(struct igb_ring *tx_ring)
2002 {
2003 struct pci_dev *pdev = tx_ring->adapter->pdev;
2004
2005 igb_clean_tx_ring(tx_ring);
2006
2007 vfree(tx_ring->buffer_info);
2008 tx_ring->buffer_info = NULL;
2009
2010 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2011
2012 tx_ring->desc = NULL;
2013 }
2014
2015 /**
2016 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2017 * @adapter: board private structure
2018 *
2019 * Free all transmit software resources
2020 **/
2021 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2022 {
2023 int i;
2024
2025 for (i = 0; i < adapter->num_tx_queues; i++)
2026 igb_free_tx_resources(&adapter->tx_ring[i]);
2027 }
2028
2029 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2030 struct igb_buffer *buffer_info)
2031 {
2032 if (buffer_info->dma) {
2033 pci_unmap_page(adapter->pdev,
2034 buffer_info->dma,
2035 buffer_info->length,
2036 PCI_DMA_TODEVICE);
2037 buffer_info->dma = 0;
2038 }
2039 if (buffer_info->skb) {
2040 dev_kfree_skb_any(buffer_info->skb);
2041 buffer_info->skb = NULL;
2042 }
2043 buffer_info->time_stamp = 0;
2044 /* buffer_info must be completely set up in the transmit path */
2045 }
2046
2047 /**
2048 * igb_clean_tx_ring - Free Tx Buffers
2049 * @tx_ring: ring to be cleaned
2050 **/
2051 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2052 {
2053 struct igb_adapter *adapter = tx_ring->adapter;
2054 struct igb_buffer *buffer_info;
2055 unsigned long size;
2056 unsigned int i;
2057
2058 if (!tx_ring->buffer_info)
2059 return;
2060 /* Free all the Tx ring sk_buffs */
2061
2062 for (i = 0; i < tx_ring->count; i++) {
2063 buffer_info = &tx_ring->buffer_info[i];
2064 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2065 }
2066
2067 size = sizeof(struct igb_buffer) * tx_ring->count;
2068 memset(tx_ring->buffer_info, 0, size);
2069
2070 /* Zero out the descriptor ring */
2071
2072 memset(tx_ring->desc, 0, tx_ring->size);
2073
2074 tx_ring->next_to_use = 0;
2075 tx_ring->next_to_clean = 0;
2076
2077 writel(0, adapter->hw.hw_addr + tx_ring->head);
2078 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2079 }
2080
2081 /**
2082 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2083 * @adapter: board private structure
2084 **/
2085 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2086 {
2087 int i;
2088
2089 for (i = 0; i < adapter->num_tx_queues; i++)
2090 igb_clean_tx_ring(&adapter->tx_ring[i]);
2091 }
2092
2093 /**
2094 * igb_free_rx_resources - Free Rx Resources
2095 * @rx_ring: ring to clean the resources from
2096 *
2097 * Free all receive software resources
2098 **/
2099 void igb_free_rx_resources(struct igb_ring *rx_ring)
2100 {
2101 struct pci_dev *pdev = rx_ring->adapter->pdev;
2102
2103 igb_clean_rx_ring(rx_ring);
2104
2105 vfree(rx_ring->buffer_info);
2106 rx_ring->buffer_info = NULL;
2107
2108 #ifdef CONFIG_IGB_LRO
2109 vfree(rx_ring->lro_mgr.lro_arr);
2110 rx_ring->lro_mgr.lro_arr = NULL;
2111 #endif
2112
2113 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2114
2115 rx_ring->desc = NULL;
2116 }
2117
2118 /**
2119 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2120 * @adapter: board private structure
2121 *
2122 * Free all receive software resources
2123 **/
2124 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2125 {
2126 int i;
2127
2128 for (i = 0; i < adapter->num_rx_queues; i++)
2129 igb_free_rx_resources(&adapter->rx_ring[i]);
2130 }
2131
2132 /**
2133 * igb_clean_rx_ring - Free Rx Buffers per Queue
2134 * @rx_ring: ring to free buffers from
2135 **/
2136 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2137 {
2138 struct igb_adapter *adapter = rx_ring->adapter;
2139 struct igb_buffer *buffer_info;
2140 struct pci_dev *pdev = adapter->pdev;
2141 unsigned long size;
2142 unsigned int i;
2143
2144 if (!rx_ring->buffer_info)
2145 return;
2146 /* Free all the Rx ring sk_buffs */
2147 for (i = 0; i < rx_ring->count; i++) {
2148 buffer_info = &rx_ring->buffer_info[i];
2149 if (buffer_info->dma) {
2150 if (adapter->rx_ps_hdr_size)
2151 pci_unmap_single(pdev, buffer_info->dma,
2152 adapter->rx_ps_hdr_size,
2153 PCI_DMA_FROMDEVICE);
2154 else
2155 pci_unmap_single(pdev, buffer_info->dma,
2156 adapter->rx_buffer_len,
2157 PCI_DMA_FROMDEVICE);
2158 buffer_info->dma = 0;
2159 }
2160
2161 if (buffer_info->skb) {
2162 dev_kfree_skb(buffer_info->skb);
2163 buffer_info->skb = NULL;
2164 }
2165 if (buffer_info->page) {
2166 if (buffer_info->page_dma)
2167 pci_unmap_page(pdev, buffer_info->page_dma,
2168 PAGE_SIZE / 2,
2169 PCI_DMA_FROMDEVICE);
2170 put_page(buffer_info->page);
2171 buffer_info->page = NULL;
2172 buffer_info->page_dma = 0;
2173 buffer_info->page_offset = 0;
2174 }
2175 }
2176
2177 size = sizeof(struct igb_buffer) * rx_ring->count;
2178 memset(rx_ring->buffer_info, 0, size);
2179
2180 /* Zero out the descriptor ring */
2181 memset(rx_ring->desc, 0, rx_ring->size);
2182
2183 rx_ring->next_to_clean = 0;
2184 rx_ring->next_to_use = 0;
2185
2186 writel(0, adapter->hw.hw_addr + rx_ring->head);
2187 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2188 }
2189
2190 /**
2191 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2192 * @adapter: board private structure
2193 **/
2194 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2195 {
2196 int i;
2197
2198 for (i = 0; i < adapter->num_rx_queues; i++)
2199 igb_clean_rx_ring(&adapter->rx_ring[i]);
2200 }
2201
2202 /**
2203 * igb_set_mac - Change the Ethernet Address of the NIC
2204 * @netdev: network interface device structure
2205 * @p: pointer to an address structure
2206 *
2207 * Returns 0 on success, negative on failure
2208 **/
2209 static int igb_set_mac(struct net_device *netdev, void *p)
2210 {
2211 struct igb_adapter *adapter = netdev_priv(netdev);
2212 struct sockaddr *addr = p;
2213
2214 if (!is_valid_ether_addr(addr->sa_data))
2215 return -EADDRNOTAVAIL;
2216
2217 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2218 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2219
2220 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2221
2222 return 0;
2223 }
2224
2225 /**
2226 * igb_set_multi - Multicast and Promiscuous mode set
2227 * @netdev: network interface device structure
2228 *
2229 * The set_multi entry point is called whenever the multicast address
2230 * list or the network interface flags are updated. This routine is
2231 * responsible for configuring the hardware for proper multicast,
2232 * promiscuous mode, and all-multi behavior.
2233 **/
2234 static void igb_set_multi(struct net_device *netdev)
2235 {
2236 struct igb_adapter *adapter = netdev_priv(netdev);
2237 struct e1000_hw *hw = &adapter->hw;
2238 struct e1000_mac_info *mac = &hw->mac;
2239 struct dev_mc_list *mc_ptr;
2240 u8 *mta_list;
2241 u32 rctl;
2242 int i;
2243
2244 /* Check for Promiscuous and All Multicast modes */
2245
2246 rctl = rd32(E1000_RCTL);
2247
2248 if (netdev->flags & IFF_PROMISC) {
2249 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2250 rctl &= ~E1000_RCTL_VFE;
2251 } else {
2252 if (netdev->flags & IFF_ALLMULTI) {
2253 rctl |= E1000_RCTL_MPE;
2254 rctl &= ~E1000_RCTL_UPE;
2255 } else
2256 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2257 rctl |= E1000_RCTL_VFE;
2258 }
2259 wr32(E1000_RCTL, rctl);
2260
2261 if (!netdev->mc_count) {
2262 /* nothing to program, so clear mc list */
2263 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
2264 mac->rar_entry_count);
2265 return;
2266 }
2267
2268 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2269 if (!mta_list)
2270 return;
2271
2272 /* The shared function expects a packed array of only addresses. */
2273 mc_ptr = netdev->mc_list;
2274
2275 for (i = 0; i < netdev->mc_count; i++) {
2276 if (!mc_ptr)
2277 break;
2278 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2279 mc_ptr = mc_ptr->next;
2280 }
2281 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2282 mac->rar_entry_count);
2283 kfree(mta_list);
2284 }
2285
2286 /* Need to wait a few seconds after link up to get diagnostic information from
2287 * the phy */
2288 static void igb_update_phy_info(unsigned long data)
2289 {
2290 struct igb_adapter *adapter = (struct igb_adapter *) data;
2291 igb_get_phy_info(&adapter->hw);
2292 }
2293
2294 /**
2295 * igb_watchdog - Timer Call-back
2296 * @data: pointer to adapter cast into an unsigned long
2297 **/
2298 static void igb_watchdog(unsigned long data)
2299 {
2300 struct igb_adapter *adapter = (struct igb_adapter *)data;
2301 /* Do the rest outside of interrupt context */
2302 schedule_work(&adapter->watchdog_task);
2303 }
2304
2305 static void igb_watchdog_task(struct work_struct *work)
2306 {
2307 struct igb_adapter *adapter = container_of(work,
2308 struct igb_adapter, watchdog_task);
2309 struct e1000_hw *hw = &adapter->hw;
2310
2311 struct net_device *netdev = adapter->netdev;
2312 struct igb_ring *tx_ring = adapter->tx_ring;
2313 struct e1000_mac_info *mac = &adapter->hw.mac;
2314 u32 link;
2315 u32 eics = 0;
2316 s32 ret_val;
2317 int i;
2318
2319 if ((netif_carrier_ok(netdev)) &&
2320 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2321 goto link_up;
2322
2323 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2324 if ((ret_val == E1000_ERR_PHY) &&
2325 (hw->phy.type == e1000_phy_igp_3) &&
2326 (rd32(E1000_CTRL) &
2327 E1000_PHY_CTRL_GBE_DISABLE))
2328 dev_info(&adapter->pdev->dev,
2329 "Gigabit has been disabled, downgrading speed\n");
2330
2331 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2332 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2333 link = mac->serdes_has_link;
2334 else
2335 link = rd32(E1000_STATUS) &
2336 E1000_STATUS_LU;
2337
2338 if (link) {
2339 if (!netif_carrier_ok(netdev)) {
2340 u32 ctrl;
2341 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2342 &adapter->link_speed,
2343 &adapter->link_duplex);
2344
2345 ctrl = rd32(E1000_CTRL);
2346 /* Links status message must follow this format */
2347 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2348 "Flow Control: %s\n",
2349 netdev->name,
2350 adapter->link_speed,
2351 adapter->link_duplex == FULL_DUPLEX ?
2352 "Full Duplex" : "Half Duplex",
2353 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2354 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2355 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2356 E1000_CTRL_TFCE) ? "TX" : "None")));
2357
2358 /* tweak tx_queue_len according to speed/duplex and
2359 * adjust the timeout factor */
2360 netdev->tx_queue_len = adapter->tx_queue_len;
2361 adapter->tx_timeout_factor = 1;
2362 switch (adapter->link_speed) {
2363 case SPEED_10:
2364 netdev->tx_queue_len = 10;
2365 adapter->tx_timeout_factor = 14;
2366 break;
2367 case SPEED_100:
2368 netdev->tx_queue_len = 100;
2369 /* maybe add some timeout factor ? */
2370 break;
2371 }
2372
2373 netif_carrier_on(netdev);
2374 netif_tx_wake_all_queues(netdev);
2375
2376 if (!test_bit(__IGB_DOWN, &adapter->state))
2377 mod_timer(&adapter->phy_info_timer,
2378 round_jiffies(jiffies + 2 * HZ));
2379 }
2380 } else {
2381 if (netif_carrier_ok(netdev)) {
2382 adapter->link_speed = 0;
2383 adapter->link_duplex = 0;
2384 /* Links status message must follow this format */
2385 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2386 netdev->name);
2387 netif_carrier_off(netdev);
2388 netif_tx_stop_all_queues(netdev);
2389 if (!test_bit(__IGB_DOWN, &adapter->state))
2390 mod_timer(&adapter->phy_info_timer,
2391 round_jiffies(jiffies + 2 * HZ));
2392 }
2393 }
2394
2395 link_up:
2396 igb_update_stats(adapter);
2397
2398 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2399 adapter->tpt_old = adapter->stats.tpt;
2400 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2401 adapter->colc_old = adapter->stats.colc;
2402
2403 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2404 adapter->gorc_old = adapter->stats.gorc;
2405 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2406 adapter->gotc_old = adapter->stats.gotc;
2407
2408 igb_update_adaptive(&adapter->hw);
2409
2410 if (!netif_carrier_ok(netdev)) {
2411 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2412 /* We've lost link, so the controller stops DMA,
2413 * but we've got queued Tx work that's never going
2414 * to get done, so reset controller to flush Tx.
2415 * (Do the reset outside of interrupt context). */
2416 adapter->tx_timeout_count++;
2417 schedule_work(&adapter->reset_task);
2418 }
2419 }
2420
2421 /* Cause software interrupt to ensure rx ring is cleaned */
2422 if (adapter->msix_entries) {
2423 for (i = 0; i < adapter->num_rx_queues; i++)
2424 eics |= adapter->rx_ring[i].eims_value;
2425 wr32(E1000_EICS, eics);
2426 } else {
2427 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2428 }
2429
2430 /* Force detection of hung controller every watchdog period */
2431 tx_ring->detect_tx_hung = true;
2432
2433 /* Reset the timer */
2434 if (!test_bit(__IGB_DOWN, &adapter->state))
2435 mod_timer(&adapter->watchdog_timer,
2436 round_jiffies(jiffies + 2 * HZ));
2437 }
2438
2439 enum latency_range {
2440 lowest_latency = 0,
2441 low_latency = 1,
2442 bulk_latency = 2,
2443 latency_invalid = 255
2444 };
2445
2446
2447 /**
2448 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2449 *
2450 * Stores a new ITR value based on strictly on packet size. This
2451 * algorithm is less sophisticated than that used in igb_update_itr,
2452 * due to the difficulty of synchronizing statistics across multiple
2453 * receive rings. The divisors and thresholds used by this fuction
2454 * were determined based on theoretical maximum wire speed and testing
2455 * data, in order to minimize response time while increasing bulk
2456 * throughput.
2457 * This functionality is controlled by the InterruptThrottleRate module
2458 * parameter (see igb_param.c)
2459 * NOTE: This function is called only when operating in a multiqueue
2460 * receive environment.
2461 * @rx_ring: pointer to ring
2462 **/
2463 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2464 {
2465 int new_val = rx_ring->itr_val;
2466 int avg_wire_size = 0;
2467 struct igb_adapter *adapter = rx_ring->adapter;
2468
2469 if (!rx_ring->total_packets)
2470 goto clear_counts; /* no packets, so don't do anything */
2471
2472 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2473 * ints/sec - ITR timer value of 120 ticks.
2474 */
2475 if (adapter->link_speed != SPEED_1000) {
2476 new_val = 120;
2477 goto set_itr_val;
2478 }
2479 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2480
2481 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2482 avg_wire_size += 24;
2483
2484 /* Don't starve jumbo frames */
2485 avg_wire_size = min(avg_wire_size, 3000);
2486
2487 /* Give a little boost to mid-size frames */
2488 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2489 new_val = avg_wire_size / 3;
2490 else
2491 new_val = avg_wire_size / 2;
2492
2493 set_itr_val:
2494 if (new_val != rx_ring->itr_val) {
2495 rx_ring->itr_val = new_val;
2496 rx_ring->set_itr = 1;
2497 }
2498 clear_counts:
2499 rx_ring->total_bytes = 0;
2500 rx_ring->total_packets = 0;
2501 }
2502
2503 /**
2504 * igb_update_itr - update the dynamic ITR value based on statistics
2505 * Stores a new ITR value based on packets and byte
2506 * counts during the last interrupt. The advantage of per interrupt
2507 * computation is faster updates and more accurate ITR for the current
2508 * traffic pattern. Constants in this function were computed
2509 * based on theoretical maximum wire speed and thresholds were set based
2510 * on testing data as well as attempting to minimize response time
2511 * while increasing bulk throughput.
2512 * this functionality is controlled by the InterruptThrottleRate module
2513 * parameter (see igb_param.c)
2514 * NOTE: These calculations are only valid when operating in a single-
2515 * queue environment.
2516 * @adapter: pointer to adapter
2517 * @itr_setting: current adapter->itr
2518 * @packets: the number of packets during this measurement interval
2519 * @bytes: the number of bytes during this measurement interval
2520 **/
2521 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2522 int packets, int bytes)
2523 {
2524 unsigned int retval = itr_setting;
2525
2526 if (packets == 0)
2527 goto update_itr_done;
2528
2529 switch (itr_setting) {
2530 case lowest_latency:
2531 /* handle TSO and jumbo frames */
2532 if (bytes/packets > 8000)
2533 retval = bulk_latency;
2534 else if ((packets < 5) && (bytes > 512))
2535 retval = low_latency;
2536 break;
2537 case low_latency: /* 50 usec aka 20000 ints/s */
2538 if (bytes > 10000) {
2539 /* this if handles the TSO accounting */
2540 if (bytes/packets > 8000) {
2541 retval = bulk_latency;
2542 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2543 retval = bulk_latency;
2544 } else if ((packets > 35)) {
2545 retval = lowest_latency;
2546 }
2547 } else if (bytes/packets > 2000) {
2548 retval = bulk_latency;
2549 } else if (packets <= 2 && bytes < 512) {
2550 retval = lowest_latency;
2551 }
2552 break;
2553 case bulk_latency: /* 250 usec aka 4000 ints/s */
2554 if (bytes > 25000) {
2555 if (packets > 35)
2556 retval = low_latency;
2557 } else if (bytes < 6000) {
2558 retval = low_latency;
2559 }
2560 break;
2561 }
2562
2563 update_itr_done:
2564 return retval;
2565 }
2566
2567 static void igb_set_itr(struct igb_adapter *adapter)
2568 {
2569 u16 current_itr;
2570 u32 new_itr = adapter->itr;
2571
2572 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2573 if (adapter->link_speed != SPEED_1000) {
2574 current_itr = 0;
2575 new_itr = 4000;
2576 goto set_itr_now;
2577 }
2578
2579 adapter->rx_itr = igb_update_itr(adapter,
2580 adapter->rx_itr,
2581 adapter->rx_ring->total_packets,
2582 adapter->rx_ring->total_bytes);
2583
2584 if (adapter->rx_ring->buddy) {
2585 adapter->tx_itr = igb_update_itr(adapter,
2586 adapter->tx_itr,
2587 adapter->tx_ring->total_packets,
2588 adapter->tx_ring->total_bytes);
2589
2590 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2591 } else {
2592 current_itr = adapter->rx_itr;
2593 }
2594
2595 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2596 if (adapter->itr_setting == 3 &&
2597 current_itr == lowest_latency)
2598 current_itr = low_latency;
2599
2600 switch (current_itr) {
2601 /* counts and packets in update_itr are dependent on these numbers */
2602 case lowest_latency:
2603 new_itr = 70000;
2604 break;
2605 case low_latency:
2606 new_itr = 20000; /* aka hwitr = ~200 */
2607 break;
2608 case bulk_latency:
2609 new_itr = 4000;
2610 break;
2611 default:
2612 break;
2613 }
2614
2615 set_itr_now:
2616 adapter->rx_ring->total_bytes = 0;
2617 adapter->rx_ring->total_packets = 0;
2618 if (adapter->rx_ring->buddy) {
2619 adapter->rx_ring->buddy->total_bytes = 0;
2620 adapter->rx_ring->buddy->total_packets = 0;
2621 }
2622
2623 if (new_itr != adapter->itr) {
2624 /* this attempts to bias the interrupt rate towards Bulk
2625 * by adding intermediate steps when interrupt rate is
2626 * increasing */
2627 new_itr = new_itr > adapter->itr ?
2628 min(adapter->itr + (new_itr >> 2), new_itr) :
2629 new_itr;
2630 /* Don't write the value here; it resets the adapter's
2631 * internal timer, and causes us to delay far longer than
2632 * we should between interrupts. Instead, we write the ITR
2633 * value at the beginning of the next interrupt so the timing
2634 * ends up being correct.
2635 */
2636 adapter->itr = new_itr;
2637 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2638 adapter->rx_ring->set_itr = 1;
2639 }
2640
2641 return;
2642 }
2643
2644
2645 #define IGB_TX_FLAGS_CSUM 0x00000001
2646 #define IGB_TX_FLAGS_VLAN 0x00000002
2647 #define IGB_TX_FLAGS_TSO 0x00000004
2648 #define IGB_TX_FLAGS_IPV4 0x00000008
2649 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2650 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2651
2652 static inline int igb_tso_adv(struct igb_adapter *adapter,
2653 struct igb_ring *tx_ring,
2654 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2655 {
2656 struct e1000_adv_tx_context_desc *context_desc;
2657 unsigned int i;
2658 int err;
2659 struct igb_buffer *buffer_info;
2660 u32 info = 0, tu_cmd = 0;
2661 u32 mss_l4len_idx, l4len;
2662 *hdr_len = 0;
2663
2664 if (skb_header_cloned(skb)) {
2665 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2666 if (err)
2667 return err;
2668 }
2669
2670 l4len = tcp_hdrlen(skb);
2671 *hdr_len += l4len;
2672
2673 if (skb->protocol == htons(ETH_P_IP)) {
2674 struct iphdr *iph = ip_hdr(skb);
2675 iph->tot_len = 0;
2676 iph->check = 0;
2677 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2678 iph->daddr, 0,
2679 IPPROTO_TCP,
2680 0);
2681 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2682 ipv6_hdr(skb)->payload_len = 0;
2683 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2684 &ipv6_hdr(skb)->daddr,
2685 0, IPPROTO_TCP, 0);
2686 }
2687
2688 i = tx_ring->next_to_use;
2689
2690 buffer_info = &tx_ring->buffer_info[i];
2691 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2692 /* VLAN MACLEN IPLEN */
2693 if (tx_flags & IGB_TX_FLAGS_VLAN)
2694 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2695 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2696 *hdr_len += skb_network_offset(skb);
2697 info |= skb_network_header_len(skb);
2698 *hdr_len += skb_network_header_len(skb);
2699 context_desc->vlan_macip_lens = cpu_to_le32(info);
2700
2701 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2702 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2703
2704 if (skb->protocol == htons(ETH_P_IP))
2705 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2706 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2707
2708 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2709
2710 /* MSS L4LEN IDX */
2711 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2712 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2713
2714 /* Context index must be unique per ring. */
2715 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2716 mss_l4len_idx |= tx_ring->queue_index << 4;
2717
2718 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2719 context_desc->seqnum_seed = 0;
2720
2721 buffer_info->time_stamp = jiffies;
2722 buffer_info->next_to_watch = i;
2723 buffer_info->dma = 0;
2724 i++;
2725 if (i == tx_ring->count)
2726 i = 0;
2727
2728 tx_ring->next_to_use = i;
2729
2730 return true;
2731 }
2732
2733 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2734 struct igb_ring *tx_ring,
2735 struct sk_buff *skb, u32 tx_flags)
2736 {
2737 struct e1000_adv_tx_context_desc *context_desc;
2738 unsigned int i;
2739 struct igb_buffer *buffer_info;
2740 u32 info = 0, tu_cmd = 0;
2741
2742 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2743 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2744 i = tx_ring->next_to_use;
2745 buffer_info = &tx_ring->buffer_info[i];
2746 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2747
2748 if (tx_flags & IGB_TX_FLAGS_VLAN)
2749 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2750 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2751 if (skb->ip_summed == CHECKSUM_PARTIAL)
2752 info |= skb_network_header_len(skb);
2753
2754 context_desc->vlan_macip_lens = cpu_to_le32(info);
2755
2756 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2757
2758 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2759 switch (skb->protocol) {
2760 case __constant_htons(ETH_P_IP):
2761 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2762 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2763 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2764 break;
2765 case __constant_htons(ETH_P_IPV6):
2766 /* XXX what about other V6 headers?? */
2767 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2768 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2769 break;
2770 default:
2771 if (unlikely(net_ratelimit()))
2772 dev_warn(&adapter->pdev->dev,
2773 "partial checksum but proto=%x!\n",
2774 skb->protocol);
2775 break;
2776 }
2777 }
2778
2779 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2780 context_desc->seqnum_seed = 0;
2781 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2782 context_desc->mss_l4len_idx =
2783 cpu_to_le32(tx_ring->queue_index << 4);
2784
2785 buffer_info->time_stamp = jiffies;
2786 buffer_info->next_to_watch = i;
2787 buffer_info->dma = 0;
2788
2789 i++;
2790 if (i == tx_ring->count)
2791 i = 0;
2792 tx_ring->next_to_use = i;
2793
2794 return true;
2795 }
2796
2797
2798 return false;
2799 }
2800
2801 #define IGB_MAX_TXD_PWR 16
2802 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2803
2804 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2805 struct igb_ring *tx_ring, struct sk_buff *skb,
2806 unsigned int first)
2807 {
2808 struct igb_buffer *buffer_info;
2809 unsigned int len = skb_headlen(skb);
2810 unsigned int count = 0, i;
2811 unsigned int f;
2812
2813 i = tx_ring->next_to_use;
2814
2815 buffer_info = &tx_ring->buffer_info[i];
2816 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2817 buffer_info->length = len;
2818 /* set time_stamp *before* dma to help avoid a possible race */
2819 buffer_info->time_stamp = jiffies;
2820 buffer_info->next_to_watch = i;
2821 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2822 PCI_DMA_TODEVICE);
2823 count++;
2824 i++;
2825 if (i == tx_ring->count)
2826 i = 0;
2827
2828 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2829 struct skb_frag_struct *frag;
2830
2831 frag = &skb_shinfo(skb)->frags[f];
2832 len = frag->size;
2833
2834 buffer_info = &tx_ring->buffer_info[i];
2835 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2836 buffer_info->length = len;
2837 buffer_info->time_stamp = jiffies;
2838 buffer_info->next_to_watch = i;
2839 buffer_info->dma = pci_map_page(adapter->pdev,
2840 frag->page,
2841 frag->page_offset,
2842 len,
2843 PCI_DMA_TODEVICE);
2844
2845 count++;
2846 i++;
2847 if (i == tx_ring->count)
2848 i = 0;
2849 }
2850
2851 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
2852 tx_ring->buffer_info[i].skb = skb;
2853 tx_ring->buffer_info[first].next_to_watch = i;
2854
2855 return count;
2856 }
2857
2858 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2859 struct igb_ring *tx_ring,
2860 int tx_flags, int count, u32 paylen,
2861 u8 hdr_len)
2862 {
2863 union e1000_adv_tx_desc *tx_desc = NULL;
2864 struct igb_buffer *buffer_info;
2865 u32 olinfo_status = 0, cmd_type_len;
2866 unsigned int i;
2867
2868 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2869 E1000_ADVTXD_DCMD_DEXT);
2870
2871 if (tx_flags & IGB_TX_FLAGS_VLAN)
2872 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2873
2874 if (tx_flags & IGB_TX_FLAGS_TSO) {
2875 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2876
2877 /* insert tcp checksum */
2878 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2879
2880 /* insert ip checksum */
2881 if (tx_flags & IGB_TX_FLAGS_IPV4)
2882 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2883
2884 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2885 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2886 }
2887
2888 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2889 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2890 IGB_TX_FLAGS_VLAN)))
2891 olinfo_status |= tx_ring->queue_index << 4;
2892
2893 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2894
2895 i = tx_ring->next_to_use;
2896 while (count--) {
2897 buffer_info = &tx_ring->buffer_info[i];
2898 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2899 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2900 tx_desc->read.cmd_type_len =
2901 cpu_to_le32(cmd_type_len | buffer_info->length);
2902 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2903 i++;
2904 if (i == tx_ring->count)
2905 i = 0;
2906 }
2907
2908 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2909 /* Force memory writes to complete before letting h/w
2910 * know there are new descriptors to fetch. (Only
2911 * applicable for weak-ordered memory model archs,
2912 * such as IA-64). */
2913 wmb();
2914
2915 tx_ring->next_to_use = i;
2916 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2917 /* we need this if more than one processor can write to our tail
2918 * at a time, it syncronizes IO on IA64/Altix systems */
2919 mmiowb();
2920 }
2921
2922 static int __igb_maybe_stop_tx(struct net_device *netdev,
2923 struct igb_ring *tx_ring, int size)
2924 {
2925 struct igb_adapter *adapter = netdev_priv(netdev);
2926
2927 netif_stop_subqueue(netdev, tx_ring->queue_index);
2928
2929 /* Herbert's original patch had:
2930 * smp_mb__after_netif_stop_queue();
2931 * but since that doesn't exist yet, just open code it. */
2932 smp_mb();
2933
2934 /* We need to check again in a case another CPU has just
2935 * made room available. */
2936 if (IGB_DESC_UNUSED(tx_ring) < size)
2937 return -EBUSY;
2938
2939 /* A reprieve! */
2940 netif_wake_subqueue(netdev, tx_ring->queue_index);
2941 ++adapter->restart_queue;
2942 return 0;
2943 }
2944
2945 static int igb_maybe_stop_tx(struct net_device *netdev,
2946 struct igb_ring *tx_ring, int size)
2947 {
2948 if (IGB_DESC_UNUSED(tx_ring) >= size)
2949 return 0;
2950 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2951 }
2952
2953 #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2954
2955 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2956 struct net_device *netdev,
2957 struct igb_ring *tx_ring)
2958 {
2959 struct igb_adapter *adapter = netdev_priv(netdev);
2960 unsigned int first;
2961 unsigned int tx_flags = 0;
2962 unsigned int len;
2963 u8 hdr_len = 0;
2964 int tso = 0;
2965
2966 len = skb_headlen(skb);
2967
2968 if (test_bit(__IGB_DOWN, &adapter->state)) {
2969 dev_kfree_skb_any(skb);
2970 return NETDEV_TX_OK;
2971 }
2972
2973 if (skb->len <= 0) {
2974 dev_kfree_skb_any(skb);
2975 return NETDEV_TX_OK;
2976 }
2977
2978 /* need: 1 descriptor per page,
2979 * + 2 desc gap to keep tail from touching head,
2980 * + 1 desc for skb->data,
2981 * + 1 desc for context descriptor,
2982 * otherwise try next time */
2983 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2984 /* this is a hard error */
2985 return NETDEV_TX_BUSY;
2986 }
2987 skb_orphan(skb);
2988
2989 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2990 tx_flags |= IGB_TX_FLAGS_VLAN;
2991 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2992 }
2993
2994 if (skb->protocol == htons(ETH_P_IP))
2995 tx_flags |= IGB_TX_FLAGS_IPV4;
2996
2997 first = tx_ring->next_to_use;
2998
2999 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3000 &hdr_len) : 0;
3001
3002 if (tso < 0) {
3003 dev_kfree_skb_any(skb);
3004 return NETDEV_TX_OK;
3005 }
3006
3007 if (tso)
3008 tx_flags |= IGB_TX_FLAGS_TSO;
3009 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
3010 if (skb->ip_summed == CHECKSUM_PARTIAL)
3011 tx_flags |= IGB_TX_FLAGS_CSUM;
3012
3013 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
3014 igb_tx_map_adv(adapter, tx_ring, skb, first),
3015 skb->len, hdr_len);
3016
3017 netdev->trans_start = jiffies;
3018
3019 /* Make sure there is space in the ring for the next send. */
3020 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3021
3022 return NETDEV_TX_OK;
3023 }
3024
3025 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3026 {
3027 struct igb_adapter *adapter = netdev_priv(netdev);
3028 struct igb_ring *tx_ring;
3029
3030 int r_idx = 0;
3031 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3032 tx_ring = adapter->multi_tx_table[r_idx];
3033
3034 /* This goes back to the question of how to logically map a tx queue
3035 * to a flow. Right now, performance is impacted slightly negatively
3036 * if using multiple tx queues. If the stack breaks away from a
3037 * single qdisc implementation, we can look at this again. */
3038 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3039 }
3040
3041 /**
3042 * igb_tx_timeout - Respond to a Tx Hang
3043 * @netdev: network interface device structure
3044 **/
3045 static void igb_tx_timeout(struct net_device *netdev)
3046 {
3047 struct igb_adapter *adapter = netdev_priv(netdev);
3048 struct e1000_hw *hw = &adapter->hw;
3049
3050 /* Do the reset outside of interrupt context */
3051 adapter->tx_timeout_count++;
3052 schedule_work(&adapter->reset_task);
3053 wr32(E1000_EICS, adapter->eims_enable_mask &
3054 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3055 }
3056
3057 static void igb_reset_task(struct work_struct *work)
3058 {
3059 struct igb_adapter *adapter;
3060 adapter = container_of(work, struct igb_adapter, reset_task);
3061
3062 igb_reinit_locked(adapter);
3063 }
3064
3065 /**
3066 * igb_get_stats - Get System Network Statistics
3067 * @netdev: network interface device structure
3068 *
3069 * Returns the address of the device statistics structure.
3070 * The statistics are actually updated from the timer callback.
3071 **/
3072 static struct net_device_stats *
3073 igb_get_stats(struct net_device *netdev)
3074 {
3075 struct igb_adapter *adapter = netdev_priv(netdev);
3076
3077 /* only return the current stats */
3078 return &adapter->net_stats;
3079 }
3080
3081 /**
3082 * igb_change_mtu - Change the Maximum Transfer Unit
3083 * @netdev: network interface device structure
3084 * @new_mtu: new value for maximum frame size
3085 *
3086 * Returns 0 on success, negative on failure
3087 **/
3088 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3089 {
3090 struct igb_adapter *adapter = netdev_priv(netdev);
3091 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3092
3093 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3094 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3095 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3096 return -EINVAL;
3097 }
3098
3099 #define MAX_STD_JUMBO_FRAME_SIZE 9234
3100 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3101 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3102 return -EINVAL;
3103 }
3104
3105 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3106 msleep(1);
3107 /* igb_down has a dependency on max_frame_size */
3108 adapter->max_frame_size = max_frame;
3109 if (netif_running(netdev))
3110 igb_down(adapter);
3111
3112 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3113 * means we reserve 2 more, this pushes us to allocate from the next
3114 * larger slab size.
3115 * i.e. RXBUFFER_2048 --> size-4096 slab
3116 */
3117
3118 if (max_frame <= IGB_RXBUFFER_256)
3119 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3120 else if (max_frame <= IGB_RXBUFFER_512)
3121 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3122 else if (max_frame <= IGB_RXBUFFER_1024)
3123 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3124 else if (max_frame <= IGB_RXBUFFER_2048)
3125 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3126 else
3127 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3128 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3129 #else
3130 adapter->rx_buffer_len = PAGE_SIZE / 2;
3131 #endif
3132 /* adjust allocation if LPE protects us, and we aren't using SBP */
3133 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3134 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3135 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3136
3137 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3138 netdev->mtu, new_mtu);
3139 netdev->mtu = new_mtu;
3140
3141 if (netif_running(netdev))
3142 igb_up(adapter);
3143 else
3144 igb_reset(adapter);
3145
3146 clear_bit(__IGB_RESETTING, &adapter->state);
3147
3148 return 0;
3149 }
3150
3151 /**
3152 * igb_update_stats - Update the board statistics counters
3153 * @adapter: board private structure
3154 **/
3155
3156 void igb_update_stats(struct igb_adapter *adapter)
3157 {
3158 struct e1000_hw *hw = &adapter->hw;
3159 struct pci_dev *pdev = adapter->pdev;
3160 u16 phy_tmp;
3161
3162 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3163
3164 /*
3165 * Prevent stats update while adapter is being reset, or if the pci
3166 * connection is down.
3167 */
3168 if (adapter->link_speed == 0)
3169 return;
3170 if (pci_channel_offline(pdev))
3171 return;
3172
3173 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3174 adapter->stats.gprc += rd32(E1000_GPRC);
3175 adapter->stats.gorc += rd32(E1000_GORCL);
3176 rd32(E1000_GORCH); /* clear GORCL */
3177 adapter->stats.bprc += rd32(E1000_BPRC);
3178 adapter->stats.mprc += rd32(E1000_MPRC);
3179 adapter->stats.roc += rd32(E1000_ROC);
3180
3181 adapter->stats.prc64 += rd32(E1000_PRC64);
3182 adapter->stats.prc127 += rd32(E1000_PRC127);
3183 adapter->stats.prc255 += rd32(E1000_PRC255);
3184 adapter->stats.prc511 += rd32(E1000_PRC511);
3185 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3186 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3187 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3188 adapter->stats.sec += rd32(E1000_SEC);
3189
3190 adapter->stats.mpc += rd32(E1000_MPC);
3191 adapter->stats.scc += rd32(E1000_SCC);
3192 adapter->stats.ecol += rd32(E1000_ECOL);
3193 adapter->stats.mcc += rd32(E1000_MCC);
3194 adapter->stats.latecol += rd32(E1000_LATECOL);
3195 adapter->stats.dc += rd32(E1000_DC);
3196 adapter->stats.rlec += rd32(E1000_RLEC);
3197 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3198 adapter->stats.xontxc += rd32(E1000_XONTXC);
3199 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3200 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3201 adapter->stats.fcruc += rd32(E1000_FCRUC);
3202 adapter->stats.gptc += rd32(E1000_GPTC);
3203 adapter->stats.gotc += rd32(E1000_GOTCL);
3204 rd32(E1000_GOTCH); /* clear GOTCL */
3205 adapter->stats.rnbc += rd32(E1000_RNBC);
3206 adapter->stats.ruc += rd32(E1000_RUC);
3207 adapter->stats.rfc += rd32(E1000_RFC);
3208 adapter->stats.rjc += rd32(E1000_RJC);
3209 adapter->stats.tor += rd32(E1000_TORH);
3210 adapter->stats.tot += rd32(E1000_TOTH);
3211 adapter->stats.tpr += rd32(E1000_TPR);
3212
3213 adapter->stats.ptc64 += rd32(E1000_PTC64);
3214 adapter->stats.ptc127 += rd32(E1000_PTC127);
3215 adapter->stats.ptc255 += rd32(E1000_PTC255);
3216 adapter->stats.ptc511 += rd32(E1000_PTC511);
3217 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3218 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3219
3220 adapter->stats.mptc += rd32(E1000_MPTC);
3221 adapter->stats.bptc += rd32(E1000_BPTC);
3222
3223 /* used for adaptive IFS */
3224
3225 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3226 adapter->stats.tpt += hw->mac.tx_packet_delta;
3227 hw->mac.collision_delta = rd32(E1000_COLC);
3228 adapter->stats.colc += hw->mac.collision_delta;
3229
3230 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3231 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3232 adapter->stats.tncrs += rd32(E1000_TNCRS);
3233 adapter->stats.tsctc += rd32(E1000_TSCTC);
3234 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3235
3236 adapter->stats.iac += rd32(E1000_IAC);
3237 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3238 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3239 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3240 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3241 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3242 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3243 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3244 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3245
3246 /* Fill out the OS statistics structure */
3247 adapter->net_stats.multicast = adapter->stats.mprc;
3248 adapter->net_stats.collisions = adapter->stats.colc;
3249
3250 /* Rx Errors */
3251
3252 /* RLEC on some newer hardware can be incorrect so build
3253 * our own version based on RUC and ROC */
3254 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3255 adapter->stats.crcerrs + adapter->stats.algnerrc +
3256 adapter->stats.ruc + adapter->stats.roc +
3257 adapter->stats.cexterr;
3258 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3259 adapter->stats.roc;
3260 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3261 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3262 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3263
3264 /* Tx Errors */
3265 adapter->net_stats.tx_errors = adapter->stats.ecol +
3266 adapter->stats.latecol;
3267 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3268 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3269 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3270
3271 /* Tx Dropped needs to be maintained elsewhere */
3272
3273 /* Phy Stats */
3274 if (hw->phy.media_type == e1000_media_type_copper) {
3275 if ((adapter->link_speed == SPEED_1000) &&
3276 (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
3277 &phy_tmp))) {
3278 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3279 adapter->phy_stats.idle_errors += phy_tmp;
3280 }
3281 }
3282
3283 /* Management Stats */
3284 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3285 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3286 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3287 }
3288
3289
3290 static irqreturn_t igb_msix_other(int irq, void *data)
3291 {
3292 struct net_device *netdev = data;
3293 struct igb_adapter *adapter = netdev_priv(netdev);
3294 struct e1000_hw *hw = &adapter->hw;
3295 u32 icr = rd32(E1000_ICR);
3296
3297 /* reading ICR causes bit 31 of EICR to be cleared */
3298 if (!(icr & E1000_ICR_LSC))
3299 goto no_link_interrupt;
3300 hw->mac.get_link_status = 1;
3301 /* guard against interrupt when we're going down */
3302 if (!test_bit(__IGB_DOWN, &adapter->state))
3303 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3304
3305 no_link_interrupt:
3306 wr32(E1000_IMS, E1000_IMS_LSC);
3307 wr32(E1000_EIMS, adapter->eims_other);
3308
3309 return IRQ_HANDLED;
3310 }
3311
3312 static irqreturn_t igb_msix_tx(int irq, void *data)
3313 {
3314 struct igb_ring *tx_ring = data;
3315 struct igb_adapter *adapter = tx_ring->adapter;
3316 struct e1000_hw *hw = &adapter->hw;
3317
3318 #ifdef CONFIG_IGB_DCA
3319 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3320 igb_update_tx_dca(tx_ring);
3321 #endif
3322 tx_ring->total_bytes = 0;
3323 tx_ring->total_packets = 0;
3324
3325 /* auto mask will automatically reenable the interrupt when we write
3326 * EICS */
3327 if (!igb_clean_tx_irq(tx_ring))
3328 /* Ring was not completely cleaned, so fire another interrupt */
3329 wr32(E1000_EICS, tx_ring->eims_value);
3330 else
3331 wr32(E1000_EIMS, tx_ring->eims_value);
3332
3333 return IRQ_HANDLED;
3334 }
3335
3336 static void igb_write_itr(struct igb_ring *ring)
3337 {
3338 struct e1000_hw *hw = &ring->adapter->hw;
3339 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3340 switch (hw->mac.type) {
3341 case e1000_82576:
3342 wr32(ring->itr_register,
3343 ring->itr_val |
3344 0x80000000);
3345 break;
3346 default:
3347 wr32(ring->itr_register,
3348 ring->itr_val |
3349 (ring->itr_val << 16));
3350 break;
3351 }
3352 ring->set_itr = 0;
3353 }
3354 }
3355
3356 static irqreturn_t igb_msix_rx(int irq, void *data)
3357 {
3358 struct igb_ring *rx_ring = data;
3359
3360 /* Write the ITR value calculated at the end of the
3361 * previous interrupt.
3362 */
3363
3364 igb_write_itr(rx_ring);
3365
3366 if (netif_rx_schedule_prep(&rx_ring->napi))
3367 __netif_rx_schedule(&rx_ring->napi);
3368
3369 #ifdef CONFIG_IGB_DCA
3370 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3371 igb_update_rx_dca(rx_ring);
3372 #endif
3373 return IRQ_HANDLED;
3374 }
3375
3376 #ifdef CONFIG_IGB_DCA
3377 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3378 {
3379 u32 dca_rxctrl;
3380 struct igb_adapter *adapter = rx_ring->adapter;
3381 struct e1000_hw *hw = &adapter->hw;
3382 int cpu = get_cpu();
3383 int q = rx_ring->reg_idx;
3384
3385 if (rx_ring->cpu != cpu) {
3386 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3387 if (hw->mac.type == e1000_82576) {
3388 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3389 dca_rxctrl |= dca_get_tag(cpu) <<
3390 E1000_DCA_RXCTRL_CPUID_SHIFT;
3391 } else {
3392 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3393 dca_rxctrl |= dca_get_tag(cpu);
3394 }
3395 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3396 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3397 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3398 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3399 rx_ring->cpu = cpu;
3400 }
3401 put_cpu();
3402 }
3403
3404 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3405 {
3406 u32 dca_txctrl;
3407 struct igb_adapter *adapter = tx_ring->adapter;
3408 struct e1000_hw *hw = &adapter->hw;
3409 int cpu = get_cpu();
3410 int q = tx_ring->reg_idx;
3411
3412 if (tx_ring->cpu != cpu) {
3413 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3414 if (hw->mac.type == e1000_82576) {
3415 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3416 dca_txctrl |= dca_get_tag(cpu) <<
3417 E1000_DCA_TXCTRL_CPUID_SHIFT;
3418 } else {
3419 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3420 dca_txctrl |= dca_get_tag(cpu);
3421 }
3422 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3423 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3424 tx_ring->cpu = cpu;
3425 }
3426 put_cpu();
3427 }
3428
3429 static void igb_setup_dca(struct igb_adapter *adapter)
3430 {
3431 int i;
3432
3433 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3434 return;
3435
3436 for (i = 0; i < adapter->num_tx_queues; i++) {
3437 adapter->tx_ring[i].cpu = -1;
3438 igb_update_tx_dca(&adapter->tx_ring[i]);
3439 }
3440 for (i = 0; i < adapter->num_rx_queues; i++) {
3441 adapter->rx_ring[i].cpu = -1;
3442 igb_update_rx_dca(&adapter->rx_ring[i]);
3443 }
3444 }
3445
3446 static int __igb_notify_dca(struct device *dev, void *data)
3447 {
3448 struct net_device *netdev = dev_get_drvdata(dev);
3449 struct igb_adapter *adapter = netdev_priv(netdev);
3450 struct e1000_hw *hw = &adapter->hw;
3451 unsigned long event = *(unsigned long *)data;
3452
3453 switch (event) {
3454 case DCA_PROVIDER_ADD:
3455 /* if already enabled, don't do it again */
3456 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3457 break;
3458 /* Always use CB2 mode, difference is masked
3459 * in the CB driver. */
3460 wr32(E1000_DCA_CTRL, 2);
3461 if (dca_add_requester(dev) == 0) {
3462 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3463 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3464 igb_setup_dca(adapter);
3465 break;
3466 }
3467 /* Fall Through since DCA is disabled. */
3468 case DCA_PROVIDER_REMOVE:
3469 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3470 /* without this a class_device is left
3471 * hanging around in the sysfs model */
3472 dca_remove_requester(dev);
3473 dev_info(&adapter->pdev->dev, "DCA disabled\n");
3474 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3475 wr32(E1000_DCA_CTRL, 1);
3476 }
3477 break;
3478 }
3479
3480 return 0;
3481 }
3482
3483 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3484 void *p)
3485 {
3486 int ret_val;
3487
3488 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3489 __igb_notify_dca);
3490
3491 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3492 }
3493 #endif /* CONFIG_IGB_DCA */
3494
3495 /**
3496 * igb_intr_msi - Interrupt Handler
3497 * @irq: interrupt number
3498 * @data: pointer to a network interface device structure
3499 **/
3500 static irqreturn_t igb_intr_msi(int irq, void *data)
3501 {
3502 struct net_device *netdev = data;
3503 struct igb_adapter *adapter = netdev_priv(netdev);
3504 struct e1000_hw *hw = &adapter->hw;
3505 /* read ICR disables interrupts using IAM */
3506 u32 icr = rd32(E1000_ICR);
3507
3508 igb_write_itr(adapter->rx_ring);
3509
3510 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3511 hw->mac.get_link_status = 1;
3512 if (!test_bit(__IGB_DOWN, &adapter->state))
3513 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3514 }
3515
3516 netif_rx_schedule(&adapter->rx_ring[0].napi);
3517
3518 return IRQ_HANDLED;
3519 }
3520
3521 /**
3522 * igb_intr - Interrupt Handler
3523 * @irq: interrupt number
3524 * @data: pointer to a network interface device structure
3525 **/
3526 static irqreturn_t igb_intr(int irq, void *data)
3527 {
3528 struct net_device *netdev = data;
3529 struct igb_adapter *adapter = netdev_priv(netdev);
3530 struct e1000_hw *hw = &adapter->hw;
3531 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3532 * need for the IMC write */
3533 u32 icr = rd32(E1000_ICR);
3534 u32 eicr = 0;
3535 if (!icr)
3536 return IRQ_NONE; /* Not our interrupt */
3537
3538 igb_write_itr(adapter->rx_ring);
3539
3540 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3541 * not set, then the adapter didn't send an interrupt */
3542 if (!(icr & E1000_ICR_INT_ASSERTED))
3543 return IRQ_NONE;
3544
3545 eicr = rd32(E1000_EICR);
3546
3547 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3548 hw->mac.get_link_status = 1;
3549 /* guard against interrupt when we're going down */
3550 if (!test_bit(__IGB_DOWN, &adapter->state))
3551 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3552 }
3553
3554 netif_rx_schedule(&adapter->rx_ring[0].napi);
3555
3556 return IRQ_HANDLED;
3557 }
3558
3559 /**
3560 * igb_poll - NAPI Rx polling callback
3561 * @napi: napi polling structure
3562 * @budget: count of how many packets we should handle
3563 **/
3564 static int igb_poll(struct napi_struct *napi, int budget)
3565 {
3566 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3567 struct igb_adapter *adapter = rx_ring->adapter;
3568 struct net_device *netdev = adapter->netdev;
3569 int tx_clean_complete, work_done = 0;
3570
3571 /* this poll routine only supports one tx and one rx queue */
3572 #ifdef CONFIG_IGB_DCA
3573 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3574 igb_update_tx_dca(&adapter->tx_ring[0]);
3575 #endif
3576 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
3577
3578 #ifdef CONFIG_IGB_DCA
3579 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3580 igb_update_rx_dca(&adapter->rx_ring[0]);
3581 #endif
3582 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
3583
3584 /* If no Tx and not enough Rx work done, exit the polling mode */
3585 if ((tx_clean_complete && (work_done < budget)) ||
3586 !netif_running(netdev)) {
3587 if (adapter->itr_setting & 3)
3588 igb_set_itr(adapter);
3589 netif_rx_complete(napi);
3590 if (!test_bit(__IGB_DOWN, &adapter->state))
3591 igb_irq_enable(adapter);
3592 return 0;
3593 }
3594
3595 return 1;
3596 }
3597
3598 static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3599 {
3600 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3601 struct igb_adapter *adapter = rx_ring->adapter;
3602 struct e1000_hw *hw = &adapter->hw;
3603 struct net_device *netdev = adapter->netdev;
3604 int work_done = 0;
3605
3606 #ifdef CONFIG_IGB_DCA
3607 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3608 igb_update_rx_dca(rx_ring);
3609 #endif
3610 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
3611
3612
3613 /* If not enough Rx work done, exit the polling mode */
3614 if ((work_done == 0) || !netif_running(netdev)) {
3615 netif_rx_complete(napi);
3616
3617 if (adapter->itr_setting & 3) {
3618 if (adapter->num_rx_queues == 1)
3619 igb_set_itr(adapter);
3620 else
3621 igb_update_ring_itr(rx_ring);
3622 }
3623
3624 if (!test_bit(__IGB_DOWN, &adapter->state))
3625 wr32(E1000_EIMS, rx_ring->eims_value);
3626
3627 return 0;
3628 }
3629
3630 return 1;
3631 }
3632
3633 /**
3634 * igb_clean_tx_irq - Reclaim resources after transmit completes
3635 * @adapter: board private structure
3636 * returns true if ring is completely cleaned
3637 **/
3638 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
3639 {
3640 struct igb_adapter *adapter = tx_ring->adapter;
3641 struct net_device *netdev = adapter->netdev;
3642 struct e1000_hw *hw = &adapter->hw;
3643 struct igb_buffer *buffer_info;
3644 struct sk_buff *skb;
3645 union e1000_adv_tx_desc *tx_desc, *eop_desc;
3646 unsigned int total_bytes = 0, total_packets = 0;
3647 unsigned int i, eop, count = 0;
3648 bool cleaned = false;
3649
3650 i = tx_ring->next_to_clean;
3651 eop = tx_ring->buffer_info[i].next_to_watch;
3652 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3653
3654 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3655 (count < tx_ring->count)) {
3656 for (cleaned = false; !cleaned; count++) {
3657 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3658 buffer_info = &tx_ring->buffer_info[i];
3659 cleaned = (i == eop);
3660 skb = buffer_info->skb;
3661
3662 if (skb) {
3663 unsigned int segs, bytecount;
3664 /* gso_segs is currently only valid for tcp */
3665 segs = skb_shinfo(skb)->gso_segs ?: 1;
3666 /* multiply data chunks by size of headers */
3667 bytecount = ((segs - 1) * skb_headlen(skb)) +
3668 skb->len;
3669 total_packets += segs;
3670 total_bytes += bytecount;
3671 }
3672
3673 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3674 tx_desc->wb.status = 0;
3675
3676 i++;
3677 if (i == tx_ring->count)
3678 i = 0;
3679 }
3680
3681 eop = tx_ring->buffer_info[i].next_to_watch;
3682 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3683 }
3684
3685 tx_ring->next_to_clean = i;
3686
3687 if (unlikely(count &&
3688 netif_carrier_ok(netdev) &&
3689 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3690 /* Make sure that anybody stopping the queue after this
3691 * sees the new next_to_clean.
3692 */
3693 smp_mb();
3694 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3695 !(test_bit(__IGB_DOWN, &adapter->state))) {
3696 netif_wake_subqueue(netdev, tx_ring->queue_index);
3697 ++adapter->restart_queue;
3698 }
3699 }
3700
3701 if (tx_ring->detect_tx_hung) {
3702 /* Detect a transmit hang in hardware, this serializes the
3703 * check with the clearing of time_stamp and movement of i */
3704 tx_ring->detect_tx_hung = false;
3705 if (tx_ring->buffer_info[i].time_stamp &&
3706 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3707 (adapter->tx_timeout_factor * HZ))
3708 && !(rd32(E1000_STATUS) &
3709 E1000_STATUS_TXOFF)) {
3710
3711 /* detected Tx unit hang */
3712 dev_err(&adapter->pdev->dev,
3713 "Detected Tx Unit Hang\n"
3714 " Tx Queue <%d>\n"
3715 " TDH <%x>\n"
3716 " TDT <%x>\n"
3717 " next_to_use <%x>\n"
3718 " next_to_clean <%x>\n"
3719 "buffer_info[next_to_clean]\n"
3720 " time_stamp <%lx>\n"
3721 " next_to_watch <%x>\n"
3722 " jiffies <%lx>\n"
3723 " desc.status <%x>\n",
3724 tx_ring->queue_index,
3725 readl(adapter->hw.hw_addr + tx_ring->head),
3726 readl(adapter->hw.hw_addr + tx_ring->tail),
3727 tx_ring->next_to_use,
3728 tx_ring->next_to_clean,
3729 tx_ring->buffer_info[i].time_stamp,
3730 eop,
3731 jiffies,
3732 eop_desc->wb.status);
3733 netif_stop_subqueue(netdev, tx_ring->queue_index);
3734 }
3735 }
3736 tx_ring->total_bytes += total_bytes;
3737 tx_ring->total_packets += total_packets;
3738 tx_ring->tx_stats.bytes += total_bytes;
3739 tx_ring->tx_stats.packets += total_packets;
3740 adapter->net_stats.tx_bytes += total_bytes;
3741 adapter->net_stats.tx_packets += total_packets;
3742 return (count < tx_ring->count);
3743 }
3744
3745 #ifdef CONFIG_IGB_LRO
3746 /**
3747 * igb_get_skb_hdr - helper function for LRO header processing
3748 * @skb: pointer to sk_buff to be added to LRO packet
3749 * @iphdr: pointer to ip header structure
3750 * @tcph: pointer to tcp header structure
3751 * @hdr_flags: pointer to header flags
3752 * @priv: pointer to the receive descriptor for the current sk_buff
3753 **/
3754 static int igb_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
3755 u64 *hdr_flags, void *priv)
3756 {
3757 union e1000_adv_rx_desc *rx_desc = priv;
3758 u16 pkt_type = rx_desc->wb.lower.lo_dword.pkt_info &
3759 (E1000_RXDADV_PKTTYPE_IPV4 | E1000_RXDADV_PKTTYPE_TCP);
3760
3761 /* Verify that this is a valid IPv4 TCP packet */
3762 if (pkt_type != (E1000_RXDADV_PKTTYPE_IPV4 |
3763 E1000_RXDADV_PKTTYPE_TCP))
3764 return -1;
3765
3766 /* Set network headers */
3767 skb_reset_network_header(skb);
3768 skb_set_transport_header(skb, ip_hdrlen(skb));
3769 *iphdr = ip_hdr(skb);
3770 *tcph = tcp_hdr(skb);
3771 *hdr_flags = LRO_IPV4 | LRO_TCP;
3772
3773 return 0;
3774
3775 }
3776 #endif /* CONFIG_IGB_LRO */
3777
3778 /**
3779 * igb_receive_skb - helper function to handle rx indications
3780 * @ring: pointer to receive ring receving this packet
3781 * @status: descriptor status field as written by hardware
3782 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3783 * @skb: pointer to sk_buff to be indicated to stack
3784 **/
3785 static void igb_receive_skb(struct igb_ring *ring, u8 status,
3786 union e1000_adv_rx_desc * rx_desc,
3787 struct sk_buff *skb)
3788 {
3789 struct igb_adapter * adapter = ring->adapter;
3790 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3791
3792 #ifdef CONFIG_IGB_LRO
3793 if (adapter->netdev->features & NETIF_F_LRO &&
3794 skb->ip_summed == CHECKSUM_UNNECESSARY) {
3795 if (vlan_extracted)
3796 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
3797 adapter->vlgrp,
3798 le16_to_cpu(rx_desc->wb.upper.vlan),
3799 rx_desc);
3800 else
3801 lro_receive_skb(&ring->lro_mgr,skb, rx_desc);
3802 ring->lro_used = 1;
3803 } else {
3804 #endif
3805 if (vlan_extracted)
3806 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3807 le16_to_cpu(rx_desc->wb.upper.vlan));
3808 else
3809
3810 netif_receive_skb(skb);
3811 #ifdef CONFIG_IGB_LRO
3812 }
3813 #endif
3814 }
3815
3816
3817 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3818 u32 status_err, struct sk_buff *skb)
3819 {
3820 skb->ip_summed = CHECKSUM_NONE;
3821
3822 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3823 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3824 return;
3825 /* TCP/UDP checksum error bit is set */
3826 if (status_err &
3827 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3828 /* let the stack verify checksum errors */
3829 adapter->hw_csum_err++;
3830 return;
3831 }
3832 /* It must be a TCP or UDP packet with a valid checksum */
3833 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3834 skb->ip_summed = CHECKSUM_UNNECESSARY;
3835
3836 adapter->hw_csum_good++;
3837 }
3838
3839 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3840 int *work_done, int budget)
3841 {
3842 struct igb_adapter *adapter = rx_ring->adapter;
3843 struct net_device *netdev = adapter->netdev;
3844 struct pci_dev *pdev = adapter->pdev;
3845 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3846 struct igb_buffer *buffer_info , *next_buffer;
3847 struct sk_buff *skb;
3848 unsigned int i;
3849 u32 length, hlen, staterr;
3850 bool cleaned = false;
3851 int cleaned_count = 0;
3852 unsigned int total_bytes = 0, total_packets = 0;
3853
3854 i = rx_ring->next_to_clean;
3855 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3856 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3857
3858 while (staterr & E1000_RXD_STAT_DD) {
3859 if (*work_done >= budget)
3860 break;
3861 (*work_done)++;
3862 buffer_info = &rx_ring->buffer_info[i];
3863
3864 /* HW will not DMA in data larger than the given buffer, even
3865 * if it parses the (NFS, of course) header to be larger. In
3866 * that case, it fills the header buffer and spills the rest
3867 * into the page.
3868 */
3869 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3870 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
3871 if (hlen > adapter->rx_ps_hdr_size)
3872 hlen = adapter->rx_ps_hdr_size;
3873
3874 length = le16_to_cpu(rx_desc->wb.upper.length);
3875 cleaned = true;
3876 cleaned_count++;
3877
3878 skb = buffer_info->skb;
3879 prefetch(skb->data - NET_IP_ALIGN);
3880 buffer_info->skb = NULL;
3881 if (!adapter->rx_ps_hdr_size) {
3882 pci_unmap_single(pdev, buffer_info->dma,
3883 adapter->rx_buffer_len +
3884 NET_IP_ALIGN,
3885 PCI_DMA_FROMDEVICE);
3886 skb_put(skb, length);
3887 goto send_up;
3888 }
3889
3890 if (!skb_shinfo(skb)->nr_frags) {
3891 pci_unmap_single(pdev, buffer_info->dma,
3892 adapter->rx_ps_hdr_size +
3893 NET_IP_ALIGN,
3894 PCI_DMA_FROMDEVICE);
3895 skb_put(skb, hlen);
3896 }
3897
3898 if (length) {
3899 pci_unmap_page(pdev, buffer_info->page_dma,
3900 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3901 buffer_info->page_dma = 0;
3902
3903 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3904 buffer_info->page,
3905 buffer_info->page_offset,
3906 length);
3907
3908 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3909 (page_count(buffer_info->page) != 1))
3910 buffer_info->page = NULL;
3911 else
3912 get_page(buffer_info->page);
3913
3914 skb->len += length;
3915 skb->data_len += length;
3916
3917 skb->truesize += length;
3918 }
3919 send_up:
3920 i++;
3921 if (i == rx_ring->count)
3922 i = 0;
3923 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3924 prefetch(next_rxd);
3925 next_buffer = &rx_ring->buffer_info[i];
3926
3927 if (!(staterr & E1000_RXD_STAT_EOP)) {
3928 buffer_info->skb = next_buffer->skb;
3929 buffer_info->dma = next_buffer->dma;
3930 next_buffer->skb = skb;
3931 next_buffer->dma = 0;
3932 goto next_desc;
3933 }
3934
3935 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3936 dev_kfree_skb_irq(skb);
3937 goto next_desc;
3938 }
3939
3940 total_bytes += skb->len;
3941 total_packets++;
3942
3943 igb_rx_checksum_adv(adapter, staterr, skb);
3944
3945 skb->protocol = eth_type_trans(skb, netdev);
3946
3947 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
3948
3949 next_desc:
3950 rx_desc->wb.upper.status_error = 0;
3951
3952 /* return some buffers to hardware, one at a time is too slow */
3953 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3954 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
3955 cleaned_count = 0;
3956 }
3957
3958 /* use prefetched values */
3959 rx_desc = next_rxd;
3960 buffer_info = next_buffer;
3961
3962 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3963 }
3964
3965 rx_ring->next_to_clean = i;
3966 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3967
3968 #ifdef CONFIG_IGB_LRO
3969 if (rx_ring->lro_used) {
3970 lro_flush_all(&rx_ring->lro_mgr);
3971 rx_ring->lro_used = 0;
3972 }
3973 #endif
3974
3975 if (cleaned_count)
3976 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
3977
3978 rx_ring->total_packets += total_packets;
3979 rx_ring->total_bytes += total_bytes;
3980 rx_ring->rx_stats.packets += total_packets;
3981 rx_ring->rx_stats.bytes += total_bytes;
3982 adapter->net_stats.rx_bytes += total_bytes;
3983 adapter->net_stats.rx_packets += total_packets;
3984 return cleaned;
3985 }
3986
3987
3988 /**
3989 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3990 * @adapter: address of board private structure
3991 **/
3992 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
3993 int cleaned_count)
3994 {
3995 struct igb_adapter *adapter = rx_ring->adapter;
3996 struct net_device *netdev = adapter->netdev;
3997 struct pci_dev *pdev = adapter->pdev;
3998 union e1000_adv_rx_desc *rx_desc;
3999 struct igb_buffer *buffer_info;
4000 struct sk_buff *skb;
4001 unsigned int i;
4002
4003 i = rx_ring->next_to_use;
4004 buffer_info = &rx_ring->buffer_info[i];
4005
4006 while (cleaned_count--) {
4007 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4008
4009 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4010 if (!buffer_info->page) {
4011 buffer_info->page = alloc_page(GFP_ATOMIC);
4012 if (!buffer_info->page) {
4013 adapter->alloc_rx_buff_failed++;
4014 goto no_buffers;
4015 }
4016 buffer_info->page_offset = 0;
4017 } else {
4018 buffer_info->page_offset ^= PAGE_SIZE / 2;
4019 }
4020 buffer_info->page_dma =
4021 pci_map_page(pdev,
4022 buffer_info->page,
4023 buffer_info->page_offset,
4024 PAGE_SIZE / 2,
4025 PCI_DMA_FROMDEVICE);
4026 }
4027
4028 if (!buffer_info->skb) {
4029 int bufsz;
4030
4031 if (adapter->rx_ps_hdr_size)
4032 bufsz = adapter->rx_ps_hdr_size;
4033 else
4034 bufsz = adapter->rx_buffer_len;
4035 bufsz += NET_IP_ALIGN;
4036 skb = netdev_alloc_skb(netdev, bufsz);
4037
4038 if (!skb) {
4039 adapter->alloc_rx_buff_failed++;
4040 goto no_buffers;
4041 }
4042
4043 /* Make buffer alignment 2 beyond a 16 byte boundary
4044 * this will result in a 16 byte aligned IP header after
4045 * the 14 byte MAC header is removed
4046 */
4047 skb_reserve(skb, NET_IP_ALIGN);
4048
4049 buffer_info->skb = skb;
4050 buffer_info->dma = pci_map_single(pdev, skb->data,
4051 bufsz,
4052 PCI_DMA_FROMDEVICE);
4053
4054 }
4055 /* Refresh the desc even if buffer_addrs didn't change because
4056 * each write-back erases this info. */
4057 if (adapter->rx_ps_hdr_size) {
4058 rx_desc->read.pkt_addr =
4059 cpu_to_le64(buffer_info->page_dma);
4060 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4061 } else {
4062 rx_desc->read.pkt_addr =
4063 cpu_to_le64(buffer_info->dma);
4064 rx_desc->read.hdr_addr = 0;
4065 }
4066
4067 i++;
4068 if (i == rx_ring->count)
4069 i = 0;
4070 buffer_info = &rx_ring->buffer_info[i];
4071 }
4072
4073 no_buffers:
4074 if (rx_ring->next_to_use != i) {
4075 rx_ring->next_to_use = i;
4076 if (i == 0)
4077 i = (rx_ring->count - 1);
4078 else
4079 i--;
4080
4081 /* Force memory writes to complete before letting h/w
4082 * know there are new descriptors to fetch. (Only
4083 * applicable for weak-ordered memory model archs,
4084 * such as IA-64). */
4085 wmb();
4086 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4087 }
4088 }
4089
4090 /**
4091 * igb_mii_ioctl -
4092 * @netdev:
4093 * @ifreq:
4094 * @cmd:
4095 **/
4096 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4097 {
4098 struct igb_adapter *adapter = netdev_priv(netdev);
4099 struct mii_ioctl_data *data = if_mii(ifr);
4100
4101 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4102 return -EOPNOTSUPP;
4103
4104 switch (cmd) {
4105 case SIOCGMIIPHY:
4106 data->phy_id = adapter->hw.phy.addr;
4107 break;
4108 case SIOCGMIIREG:
4109 if (!capable(CAP_NET_ADMIN))
4110 return -EPERM;
4111 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4112 &data->val_out))
4113 return -EIO;
4114 break;
4115 case SIOCSMIIREG:
4116 default:
4117 return -EOPNOTSUPP;
4118 }
4119 return 0;
4120 }
4121
4122 /**
4123 * igb_ioctl -
4124 * @netdev:
4125 * @ifreq:
4126 * @cmd:
4127 **/
4128 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4129 {
4130 switch (cmd) {
4131 case SIOCGMIIPHY:
4132 case SIOCGMIIREG:
4133 case SIOCSMIIREG:
4134 return igb_mii_ioctl(netdev, ifr, cmd);
4135 default:
4136 return -EOPNOTSUPP;
4137 }
4138 }
4139
4140 static void igb_vlan_rx_register(struct net_device *netdev,
4141 struct vlan_group *grp)
4142 {
4143 struct igb_adapter *adapter = netdev_priv(netdev);
4144 struct e1000_hw *hw = &adapter->hw;
4145 u32 ctrl, rctl;
4146
4147 igb_irq_disable(adapter);
4148 adapter->vlgrp = grp;
4149
4150 if (grp) {
4151 /* enable VLAN tag insert/strip */
4152 ctrl = rd32(E1000_CTRL);
4153 ctrl |= E1000_CTRL_VME;
4154 wr32(E1000_CTRL, ctrl);
4155
4156 /* enable VLAN receive filtering */
4157 rctl = rd32(E1000_RCTL);
4158 rctl &= ~E1000_RCTL_CFIEN;
4159 wr32(E1000_RCTL, rctl);
4160 igb_update_mng_vlan(adapter);
4161 wr32(E1000_RLPML,
4162 adapter->max_frame_size + VLAN_TAG_SIZE);
4163 } else {
4164 /* disable VLAN tag insert/strip */
4165 ctrl = rd32(E1000_CTRL);
4166 ctrl &= ~E1000_CTRL_VME;
4167 wr32(E1000_CTRL, ctrl);
4168
4169 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4170 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4171 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4172 }
4173 wr32(E1000_RLPML,
4174 adapter->max_frame_size);
4175 }
4176
4177 if (!test_bit(__IGB_DOWN, &adapter->state))
4178 igb_irq_enable(adapter);
4179 }
4180
4181 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4182 {
4183 struct igb_adapter *adapter = netdev_priv(netdev);
4184 struct e1000_hw *hw = &adapter->hw;
4185 u32 vfta, index;
4186
4187 if ((adapter->hw.mng_cookie.status &
4188 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4189 (vid == adapter->mng_vlan_id))
4190 return;
4191 /* add VID to filter table */
4192 index = (vid >> 5) & 0x7F;
4193 vfta = array_rd32(E1000_VFTA, index);
4194 vfta |= (1 << (vid & 0x1F));
4195 igb_write_vfta(&adapter->hw, index, vfta);
4196 }
4197
4198 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4199 {
4200 struct igb_adapter *adapter = netdev_priv(netdev);
4201 struct e1000_hw *hw = &adapter->hw;
4202 u32 vfta, index;
4203
4204 igb_irq_disable(adapter);
4205 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4206
4207 if (!test_bit(__IGB_DOWN, &adapter->state))
4208 igb_irq_enable(adapter);
4209
4210 if ((adapter->hw.mng_cookie.status &
4211 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4212 (vid == adapter->mng_vlan_id)) {
4213 /* release control to f/w */
4214 igb_release_hw_control(adapter);
4215 return;
4216 }
4217
4218 /* remove VID from filter table */
4219 index = (vid >> 5) & 0x7F;
4220 vfta = array_rd32(E1000_VFTA, index);
4221 vfta &= ~(1 << (vid & 0x1F));
4222 igb_write_vfta(&adapter->hw, index, vfta);
4223 }
4224
4225 static void igb_restore_vlan(struct igb_adapter *adapter)
4226 {
4227 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4228
4229 if (adapter->vlgrp) {
4230 u16 vid;
4231 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4232 if (!vlan_group_get_device(adapter->vlgrp, vid))
4233 continue;
4234 igb_vlan_rx_add_vid(adapter->netdev, vid);
4235 }
4236 }
4237 }
4238
4239 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4240 {
4241 struct e1000_mac_info *mac = &adapter->hw.mac;
4242
4243 mac->autoneg = 0;
4244
4245 /* Fiber NICs only allow 1000 gbps Full duplex */
4246 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4247 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4248 dev_err(&adapter->pdev->dev,
4249 "Unsupported Speed/Duplex configuration\n");
4250 return -EINVAL;
4251 }
4252
4253 switch (spddplx) {
4254 case SPEED_10 + DUPLEX_HALF:
4255 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4256 break;
4257 case SPEED_10 + DUPLEX_FULL:
4258 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4259 break;
4260 case SPEED_100 + DUPLEX_HALF:
4261 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4262 break;
4263 case SPEED_100 + DUPLEX_FULL:
4264 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4265 break;
4266 case SPEED_1000 + DUPLEX_FULL:
4267 mac->autoneg = 1;
4268 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4269 break;
4270 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4271 default:
4272 dev_err(&adapter->pdev->dev,
4273 "Unsupported Speed/Duplex configuration\n");
4274 return -EINVAL;
4275 }
4276 return 0;
4277 }
4278
4279
4280 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4281 {
4282 struct net_device *netdev = pci_get_drvdata(pdev);
4283 struct igb_adapter *adapter = netdev_priv(netdev);
4284 struct e1000_hw *hw = &adapter->hw;
4285 u32 ctrl, rctl, status;
4286 u32 wufc = adapter->wol;
4287 #ifdef CONFIG_PM
4288 int retval = 0;
4289 #endif
4290
4291 netif_device_detach(netdev);
4292
4293 if (netif_running(netdev))
4294 igb_close(netdev);
4295
4296 igb_reset_interrupt_capability(adapter);
4297
4298 igb_free_queues(adapter);
4299
4300 #ifdef CONFIG_PM
4301 retval = pci_save_state(pdev);
4302 if (retval)
4303 return retval;
4304 #endif
4305
4306 status = rd32(E1000_STATUS);
4307 if (status & E1000_STATUS_LU)
4308 wufc &= ~E1000_WUFC_LNKC;
4309
4310 if (wufc) {
4311 igb_setup_rctl(adapter);
4312 igb_set_multi(netdev);
4313
4314 /* turn on all-multi mode if wake on multicast is enabled */
4315 if (wufc & E1000_WUFC_MC) {
4316 rctl = rd32(E1000_RCTL);
4317 rctl |= E1000_RCTL_MPE;
4318 wr32(E1000_RCTL, rctl);
4319 }
4320
4321 ctrl = rd32(E1000_CTRL);
4322 /* advertise wake from D3Cold */
4323 #define E1000_CTRL_ADVD3WUC 0x00100000
4324 /* phy power management enable */
4325 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4326 ctrl |= E1000_CTRL_ADVD3WUC;
4327 wr32(E1000_CTRL, ctrl);
4328
4329 /* Allow time for pending master requests to run */
4330 igb_disable_pcie_master(&adapter->hw);
4331
4332 wr32(E1000_WUC, E1000_WUC_PME_EN);
4333 wr32(E1000_WUFC, wufc);
4334 } else {
4335 wr32(E1000_WUC, 0);
4336 wr32(E1000_WUFC, 0);
4337 }
4338
4339 /* make sure adapter isn't asleep if manageability/wol is enabled */
4340 if (wufc || adapter->en_mng_pt) {
4341 pci_enable_wake(pdev, PCI_D3hot, 1);
4342 pci_enable_wake(pdev, PCI_D3cold, 1);
4343 } else {
4344 igb_shutdown_fiber_serdes_link_82575(hw);
4345 pci_enable_wake(pdev, PCI_D3hot, 0);
4346 pci_enable_wake(pdev, PCI_D3cold, 0);
4347 }
4348
4349 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4350 * would have already happened in close and is redundant. */
4351 igb_release_hw_control(adapter);
4352
4353 pci_disable_device(pdev);
4354
4355 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4356
4357 return 0;
4358 }
4359
4360 #ifdef CONFIG_PM
4361 static int igb_resume(struct pci_dev *pdev)
4362 {
4363 struct net_device *netdev = pci_get_drvdata(pdev);
4364 struct igb_adapter *adapter = netdev_priv(netdev);
4365 struct e1000_hw *hw = &adapter->hw;
4366 u32 err;
4367
4368 pci_set_power_state(pdev, PCI_D0);
4369 pci_restore_state(pdev);
4370
4371 if (adapter->need_ioport)
4372 err = pci_enable_device(pdev);
4373 else
4374 err = pci_enable_device_mem(pdev);
4375 if (err) {
4376 dev_err(&pdev->dev,
4377 "igb: Cannot enable PCI device from suspend\n");
4378 return err;
4379 }
4380 pci_set_master(pdev);
4381
4382 pci_enable_wake(pdev, PCI_D3hot, 0);
4383 pci_enable_wake(pdev, PCI_D3cold, 0);
4384
4385 igb_set_interrupt_capability(adapter);
4386
4387 if (igb_alloc_queues(adapter)) {
4388 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4389 return -ENOMEM;
4390 }
4391
4392 /* e1000_power_up_phy(adapter); */
4393
4394 igb_reset(adapter);
4395 wr32(E1000_WUS, ~0);
4396
4397 if (netif_running(netdev)) {
4398 err = igb_open(netdev);
4399 if (err)
4400 return err;
4401 }
4402
4403 netif_device_attach(netdev);
4404
4405 /* let the f/w know that the h/w is now under the control of the
4406 * driver. */
4407 igb_get_hw_control(adapter);
4408
4409 return 0;
4410 }
4411 #endif
4412
4413 static void igb_shutdown(struct pci_dev *pdev)
4414 {
4415 igb_suspend(pdev, PMSG_SUSPEND);
4416 }
4417
4418 #ifdef CONFIG_NET_POLL_CONTROLLER
4419 /*
4420 * Polling 'interrupt' - used by things like netconsole to send skbs
4421 * without having to re-enable interrupts. It's not called while
4422 * the interrupt routine is executing.
4423 */
4424 static void igb_netpoll(struct net_device *netdev)
4425 {
4426 struct igb_adapter *adapter = netdev_priv(netdev);
4427 int i;
4428 int work_done = 0;
4429
4430 igb_irq_disable(adapter);
4431 adapter->flags |= IGB_FLAG_IN_NETPOLL;
4432
4433 for (i = 0; i < adapter->num_tx_queues; i++)
4434 igb_clean_tx_irq(&adapter->tx_ring[i]);
4435
4436 for (i = 0; i < adapter->num_rx_queues; i++)
4437 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
4438 &work_done,
4439 adapter->rx_ring[i].napi.weight);
4440
4441 adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
4442 igb_irq_enable(adapter);
4443 }
4444 #endif /* CONFIG_NET_POLL_CONTROLLER */
4445
4446 /**
4447 * igb_io_error_detected - called when PCI error is detected
4448 * @pdev: Pointer to PCI device
4449 * @state: The current pci connection state
4450 *
4451 * This function is called after a PCI bus error affecting
4452 * this device has been detected.
4453 */
4454 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4455 pci_channel_state_t state)
4456 {
4457 struct net_device *netdev = pci_get_drvdata(pdev);
4458 struct igb_adapter *adapter = netdev_priv(netdev);
4459
4460 netif_device_detach(netdev);
4461
4462 if (netif_running(netdev))
4463 igb_down(adapter);
4464 pci_disable_device(pdev);
4465
4466 /* Request a slot slot reset. */
4467 return PCI_ERS_RESULT_NEED_RESET;
4468 }
4469
4470 /**
4471 * igb_io_slot_reset - called after the pci bus has been reset.
4472 * @pdev: Pointer to PCI device
4473 *
4474 * Restart the card from scratch, as if from a cold-boot. Implementation
4475 * resembles the first-half of the igb_resume routine.
4476 */
4477 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4478 {
4479 struct net_device *netdev = pci_get_drvdata(pdev);
4480 struct igb_adapter *adapter = netdev_priv(netdev);
4481 struct e1000_hw *hw = &adapter->hw;
4482 pci_ers_result_t result;
4483 int err;
4484
4485 if (adapter->need_ioport)
4486 err = pci_enable_device(pdev);
4487 else
4488 err = pci_enable_device_mem(pdev);
4489
4490 if (err) {
4491 dev_err(&pdev->dev,
4492 "Cannot re-enable PCI device after reset.\n");
4493 result = PCI_ERS_RESULT_DISCONNECT;
4494 } else {
4495 pci_set_master(pdev);
4496 pci_restore_state(pdev);
4497
4498 pci_enable_wake(pdev, PCI_D3hot, 0);
4499 pci_enable_wake(pdev, PCI_D3cold, 0);
4500
4501 igb_reset(adapter);
4502 wr32(E1000_WUS, ~0);
4503 result = PCI_ERS_RESULT_RECOVERED;
4504 }
4505
4506 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4507 if (err) {
4508 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4509 "failed 0x%0x\n", err);
4510 /* non-fatal, continue */
4511 }
4512
4513 return result;
4514 }
4515
4516 /**
4517 * igb_io_resume - called when traffic can start flowing again.
4518 * @pdev: Pointer to PCI device
4519 *
4520 * This callback is called when the error recovery driver tells us that
4521 * its OK to resume normal operation. Implementation resembles the
4522 * second-half of the igb_resume routine.
4523 */
4524 static void igb_io_resume(struct pci_dev *pdev)
4525 {
4526 struct net_device *netdev = pci_get_drvdata(pdev);
4527 struct igb_adapter *adapter = netdev_priv(netdev);
4528
4529 if (netif_running(netdev)) {
4530 if (igb_up(adapter)) {
4531 dev_err(&pdev->dev, "igb_up failed after reset\n");
4532 return;
4533 }
4534 }
4535
4536 netif_device_attach(netdev);
4537
4538 /* let the f/w know that the h/w is now under the control of the
4539 * driver. */
4540 igb_get_hw_control(adapter);
4541 }
4542
4543 /* igb_main.c */
Nao low-level kernelspace/userspace library that runs on our robots, Nao-Team HTWK