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added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / drivers / net / dnet.c
blobedf23c9ea63c669daaca2108723b5b374c3e059d
1 /*
2 * Dave DNET Ethernet Controller driver
3 *
4 * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
5 * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/version.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/init.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/platform_device.h>
24 #include <linux/phy.h>
25 #include <linux/platform_device.h>
26
27 #include "dnet.h"
28
29 #undef DEBUG
30
31 /* function for reading internal MAC register */
32 u16 dnet_readw_mac(struct dnet *bp, u16 reg)
33 {
34 u16 data_read;
35
36 /* issue a read */
37 dnet_writel(bp, reg, MACREG_ADDR);
38
39 /* since a read/write op to the MAC is very slow,
40 * we must wait before reading the data */
41 ndelay(500);
42
43 /* read data read from the MAC register */
44 data_read = dnet_readl(bp, MACREG_DATA);
45
46 /* all done */
47 return data_read;
48 }
49
50 /* function for writing internal MAC register */
51 void dnet_writew_mac(struct dnet *bp, u16 reg, u16 val)
52 {
53 /* load data to write */
54 dnet_writel(bp, val, MACREG_DATA);
55
56 /* issue a write */
57 dnet_writel(bp, reg | DNET_INTERNAL_WRITE, MACREG_ADDR);
58
59 /* since a read/write op to the MAC is very slow,
60 * we must wait before exiting */
61 ndelay(500);
62 }
63
64 static void __dnet_set_hwaddr(struct dnet *bp)
65 {
66 u16 tmp;
67
68 tmp = cpu_to_be16(*((u16 *) bp->dev->dev_addr));
69 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
70 tmp = cpu_to_be16(*((u16 *) (bp->dev->dev_addr + 2)));
71 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
72 tmp = cpu_to_be16(*((u16 *) (bp->dev->dev_addr + 4)));
73 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);
74 }
75
76 static void __devinit dnet_get_hwaddr(struct dnet *bp)
77 {
78 u16 tmp;
79 u8 addr[6];
80
81 /*
82 * from MAC docs:
83 * "Note that the MAC address is stored in the registers in Hexadecimal
84 * form. For example, to set the MAC Address to: AC-DE-48-00-00-80
85 * would require writing 0xAC (octet 0) to address 0x0B (high byte of
86 * Mac_addr[15:0]), 0xDE (octet 1) to address 0x0A (Low byte of
87 * Mac_addr[15:0]), 0x48 (octet 2) to address 0x0D (high byte of
88 * Mac_addr[15:0]), 0x00 (octet 3) to address 0x0C (Low byte of
89 * Mac_addr[15:0]), 0x00 (octet 4) to address 0x0F (high byte of
90 * Mac_addr[15:0]), and 0x80 (octet 5) to address * 0x0E (Low byte of
91 * Mac_addr[15:0]).
92 */
93 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG);
94 *((u16 *) addr) = be16_to_cpu(tmp);
95 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG);
96 *((u16 *) (addr + 2)) = be16_to_cpu(tmp);
97 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG);
98 *((u16 *) (addr + 4)) = be16_to_cpu(tmp);
99
100 if (is_valid_ether_addr(addr))
101 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
102 }
103
104 static int dnet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
105 {
106 struct dnet *bp = bus->priv;
107 u16 value;
108
109 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
110 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
111 cpu_relax();
112
113 /* only 5 bits allowed for phy-addr and reg_offset */
114 mii_id &= 0x1f;
115 regnum &= 0x1f;
116
117 /* prepare reg_value for a read */
118 value = (mii_id << 8);
119 value |= regnum;
120
121 /* write control word */
122 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
123
124 /* wait for end of transfer */
125 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
126 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
127 cpu_relax();
128
129 value = dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG);
130
131 pr_debug("mdio_read %02x:%02x <- %04x\n", mii_id, regnum, value);
132
133 return value;
134 }
135
136 static int dnet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
137 u16 value)
138 {
139 struct dnet *bp = bus->priv;
140 u16 tmp;
141
142 pr_debug("mdio_write %02x:%02x <- %04x\n", mii_id, regnum, value);
143
144 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
145 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
146 cpu_relax();
147
148 /* prepare for a write operation */
149 tmp = (1 << 13);
150
151 /* only 5 bits allowed for phy-addr and reg_offset */
152 mii_id &= 0x1f;
153 regnum &= 0x1f;
154
155 /* only 16 bits on data */
156 value &= 0xffff;
157
158 /* prepare reg_value for a write */
159 tmp |= (mii_id << 8);
160 tmp |= regnum;
161
162 /* write data to write first */
163 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
164
165 /* write control word */
166 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
167
168 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
169 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
170 cpu_relax();
171
172 return 0;
173 }
174
175 static int dnet_mdio_reset(struct mii_bus *bus)
176 {
177 return 0;
178 }
179
180 static void dnet_handle_link_change(struct net_device *dev)
181 {
182 struct dnet *bp = netdev_priv(dev);
183 struct phy_device *phydev = bp->phy_dev;
184 unsigned long flags;
185 u32 mode_reg, ctl_reg;
186
187 int status_change = 0;
188
189 spin_lock_irqsave(&bp->lock, flags);
190
191 mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG);
192 ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
193
194 if (phydev->link) {
195 if (bp->duplex != phydev->duplex) {
196 if (phydev->duplex)
197 ctl_reg &=
198 ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
199 else
200 ctl_reg |=
201 DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
202
203 bp->duplex = phydev->duplex;
204 status_change = 1;
205 }
206
207 if (bp->speed != phydev->speed) {
208 status_change = 1;
209 switch (phydev->speed) {
210 case 1000:
211 mode_reg |= DNET_INTERNAL_MODE_GBITEN;
212 break;
213 case 100:
214 case 10:
215 mode_reg &= ~DNET_INTERNAL_MODE_GBITEN;
216 break;
217 default:
218 printk(KERN_WARNING
219 "%s: Ack! Speed (%d) is not "
220 "10/100/1000!\n", dev->name,
221 phydev->speed);
222 break;
223 }
224 bp->speed = phydev->speed;
225 }
226 }
227
228 if (phydev->link != bp->link) {
229 if (phydev->link) {
230 mode_reg |=
231 (DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
232 } else {
233 mode_reg &=
234 ~(DNET_INTERNAL_MODE_RXEN |
235 DNET_INTERNAL_MODE_TXEN);
236 bp->speed = 0;
237 bp->duplex = -1;
238 }
239 bp->link = phydev->link;
240
241 status_change = 1;
242 }
243
244 if (status_change) {
245 dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
246 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg);
247 }
248
249 spin_unlock_irqrestore(&bp->lock, flags);
250
251 if (status_change) {
252 if (phydev->link)
253 printk(KERN_INFO "%s: link up (%d/%s)\n",
254 dev->name, phydev->speed,
255 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
256 else
257 printk(KERN_INFO "%s: link down\n", dev->name);
258 }
259 }
260
261 static int dnet_mii_probe(struct net_device *dev)
262 {
263 struct dnet *bp = netdev_priv(dev);
264 struct phy_device *phydev = NULL;
265 int phy_addr;
266
267 /* find the first phy */
268 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
269 if (bp->mii_bus->phy_map[phy_addr]) {
270 phydev = bp->mii_bus->phy_map[phy_addr];
271 break;
272 }
273 }
274
275 if (!phydev) {
276 printk(KERN_ERR "%s: no PHY found\n", dev->name);
277 return -ENODEV;
278 }
279
280 /* TODO : add pin_irq */
281
282 /* attach the mac to the phy */
283 if (bp->capabilities & DNET_HAS_RMII) {
284 phydev = phy_connect(dev, dev_name(&phydev->dev),
285 &dnet_handle_link_change, 0,
286 PHY_INTERFACE_MODE_RMII);
287 } else {
288 phydev = phy_connect(dev, dev_name(&phydev->dev),
289 &dnet_handle_link_change, 0,
290 PHY_INTERFACE_MODE_MII);
291 }
292
293 if (IS_ERR(phydev)) {
294 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
295 return PTR_ERR(phydev);
296 }
297
298 /* mask with MAC supported features */
299 if (bp->capabilities & DNET_HAS_GIGABIT)
300 phydev->supported &= PHY_GBIT_FEATURES;
301 else
302 phydev->supported &= PHY_BASIC_FEATURES;
303
304 phydev->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause;
305
306 phydev->advertising = phydev->supported;
307
308 bp->link = 0;
309 bp->speed = 0;
310 bp->duplex = -1;
311 bp->phy_dev = phydev;
312
313 return 0;
314 }
315
316 static int dnet_mii_init(struct dnet *bp)
317 {
318 int err, i;
319
320 bp->mii_bus = mdiobus_alloc();
321 if (bp->mii_bus == NULL)
322 return -ENOMEM;
323
324 bp->mii_bus->name = "dnet_mii_bus";
325 bp->mii_bus->read = &dnet_mdio_read;
326 bp->mii_bus->write = &dnet_mdio_write;
327 bp->mii_bus->reset = &dnet_mdio_reset;
328
329 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
330
331 bp->mii_bus->priv = bp;
332
333 bp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
334 if (!bp->mii_bus->irq) {
335 err = -ENOMEM;
336 goto err_out;
337 }
338
339 for (i = 0; i < PHY_MAX_ADDR; i++)
340 bp->mii_bus->irq[i] = PHY_POLL;
341
342 platform_set_drvdata(bp->dev, bp->mii_bus);
343
344 if (mdiobus_register(bp->mii_bus)) {
345 err = -ENXIO;
346 goto err_out_free_mdio_irq;
347 }
348
349 if (dnet_mii_probe(bp->dev) != 0) {
350 err = -ENXIO;
351 goto err_out_unregister_bus;
352 }
353
354 return 0;
355
356 err_out_unregister_bus:
357 mdiobus_unregister(bp->mii_bus);
358 err_out_free_mdio_irq:
359 kfree(bp->mii_bus->irq);
360 err_out:
361 mdiobus_free(bp->mii_bus);
362 return err;
363 }
364
365 /* For Neptune board: LINK1000 as Link LED and TX as activity LED */
366 int dnet_phy_marvell_fixup(struct phy_device *phydev)
367 {
368 return phy_write(phydev, 0x18, 0x4148);
369 }
370
371 static void dnet_update_stats(struct dnet *bp)
372 {
373 u32 __iomem *reg = bp->regs + DNET_RX_PKT_IGNR_CNT;
374 u32 *p = &bp->hw_stats.rx_pkt_ignr;
375 u32 *end = &bp->hw_stats.rx_byte + 1;
376
377 WARN_ON((unsigned long)(end - p - 1) !=
378 (DNET_RX_BYTE_CNT - DNET_RX_PKT_IGNR_CNT) / 4);
379
380 for (; p < end; p++, reg++)
381 *p += readl(reg);
382
383 reg = bp->regs + DNET_TX_UNICAST_CNT;
384 p = &bp->hw_stats.tx_unicast;
385 end = &bp->hw_stats.tx_byte + 1;
386
387 WARN_ON((unsigned long)(end - p - 1) !=
388 (DNET_TX_BYTE_CNT - DNET_TX_UNICAST_CNT) / 4);
389
390 for (; p < end; p++, reg++)
391 *p += readl(reg);
392 }
393
394 static int dnet_poll(struct napi_struct *napi, int budget)
395 {
396 struct dnet *bp = container_of(napi, struct dnet, napi);
397 struct net_device *dev = bp->dev;
398 int npackets = 0;
399 unsigned int pkt_len;
400 struct sk_buff *skb;
401 unsigned int *data_ptr;
402 u32 int_enable;
403 u32 cmd_word;
404 int i;
405
406 while (npackets < budget) {
407 /*
408 * break out of while loop if there are no more
409 * packets waiting
410 */
411 if (!(dnet_readl(bp, RX_FIFO_WCNT) >> 16)) {
412 napi_complete(napi);
413 int_enable = dnet_readl(bp, INTR_ENB);
414 int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF;
415 dnet_writel(bp, int_enable, INTR_ENB);
416 return 0;
417 }
418
419 cmd_word = dnet_readl(bp, RX_LEN_FIFO);
420 pkt_len = cmd_word & 0xFFFF;
421
422 if (cmd_word & 0xDF180000)
423 printk(KERN_ERR "%s packet receive error %x\n",
424 __func__, cmd_word);
425
426 skb = dev_alloc_skb(pkt_len + 5);
427 if (skb != NULL) {
428 /* Align IP on 16 byte boundaries */
429 skb_reserve(skb, 2);
430 /*
431 * 'skb_put()' points to the start of sk_buff
432 * data area.
433 */
434 data_ptr = (unsigned int *)skb_put(skb, pkt_len);
435 for (i = 0; i < (pkt_len + 3) >> 2; i++)
436 *data_ptr++ = dnet_readl(bp, RX_DATA_FIFO);
437 skb->protocol = eth_type_trans(skb, dev);
438 netif_receive_skb(skb);
439 npackets++;
440 } else
441 printk(KERN_NOTICE
442 "%s: No memory to allocate a sk_buff of "
443 "size %u.\n", dev->name, pkt_len);
444 }
445
446 budget -= npackets;
447
448 if (npackets < budget) {
449 /* We processed all packets available. Tell NAPI it can
450 * stop polling then re-enable rx interrupts */
451 napi_complete(napi);
452 int_enable = dnet_readl(bp, INTR_ENB);
453 int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF;
454 dnet_writel(bp, int_enable, INTR_ENB);
455 return 0;
456 }
457
458 /* There are still packets waiting */
459 return 1;
460 }
461
462 static irqreturn_t dnet_interrupt(int irq, void *dev_id)
463 {
464 struct net_device *dev = dev_id;
465 struct dnet *bp = netdev_priv(dev);
466 u32 int_src, int_enable, int_current;
467 unsigned long flags;
468 unsigned int handled = 0;
469
470 spin_lock_irqsave(&bp->lock, flags);
471
472 /* read and clear the DNET irq (clear on read) */
473 int_src = dnet_readl(bp, INTR_SRC);
474 int_enable = dnet_readl(bp, INTR_ENB);
475 int_current = int_src & int_enable;
476
477 /* restart the queue if we had stopped it for TX fifo almost full */
478 if (int_current & DNET_INTR_SRC_TX_FIFOAE) {
479 int_enable = dnet_readl(bp, INTR_ENB);
480 int_enable &= ~DNET_INTR_ENB_TX_FIFOAE;
481 dnet_writel(bp, int_enable, INTR_ENB);
482 netif_wake_queue(dev);
483 handled = 1;
484 }
485
486 /* RX FIFO error checking */
487 if (int_current &
488 (DNET_INTR_SRC_RX_CMDFIFOFF | DNET_INTR_SRC_RX_DATAFIFOFF)) {
489 printk(KERN_ERR "%s: RX fifo error %x, irq %x\n", __func__,
490 dnet_readl(bp, RX_STATUS), int_current);
491 /* we can only flush the RX FIFOs */
492 dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH, SYS_CTL);
493 ndelay(500);
494 dnet_writel(bp, 0, SYS_CTL);
495 handled = 1;
496 }
497
498 /* TX FIFO error checking */
499 if (int_current &
500 (DNET_INTR_SRC_TX_FIFOFULL | DNET_INTR_SRC_TX_DISCFRM)) {
501 printk(KERN_ERR "%s: TX fifo error %x, irq %x\n", __func__,
502 dnet_readl(bp, TX_STATUS), int_current);
503 /* we can only flush the TX FIFOs */
504 dnet_writel(bp, DNET_SYS_CTL_TXFIFOFLUSH, SYS_CTL);
505 ndelay(500);
506 dnet_writel(bp, 0, SYS_CTL);
507 handled = 1;
508 }
509
510 if (int_current & DNET_INTR_SRC_RX_CMDFIFOAF) {
511 if (napi_schedule_prep(&bp->napi)) {
512 /*
513 * There's no point taking any more interrupts
514 * until we have processed the buffers
515 */
516 /* Disable Rx interrupts and schedule NAPI poll */
517 int_enable = dnet_readl(bp, INTR_ENB);
518 int_enable &= ~DNET_INTR_SRC_RX_CMDFIFOAF;
519 dnet_writel(bp, int_enable, INTR_ENB);
520 __napi_schedule(&bp->napi);
521 }
522 handled = 1;
523 }
524
525 if (!handled)
526 pr_debug("%s: irq %x remains\n", __func__, int_current);
527
528 spin_unlock_irqrestore(&bp->lock, flags);
529
530 return IRQ_RETVAL(handled);
531 }
532
533 #ifdef DEBUG
534 static inline void dnet_print_skb(struct sk_buff *skb)
535 {
536 int k;
537 printk(KERN_DEBUG PFX "data:");
538 for (k = 0; k < skb->len; k++)
539 printk(" %02x", (unsigned int)skb->data[k]);
540 printk("\n");
541 }
542 #else
543 #define dnet_print_skb(skb) do {} while (0)
544 #endif
545
546 static int dnet_start_xmit(struct sk_buff *skb, struct net_device *dev)
547 {
548
549 struct dnet *bp = netdev_priv(dev);
550 u32 tx_status, irq_enable;
551 unsigned int len, i, tx_cmd, wrsz;
552 unsigned long flags;
553 unsigned int *bufp;
554
555 tx_status = dnet_readl(bp, TX_STATUS);
556
557 pr_debug("start_xmit: len %u head %p data %p\n",
558 skb->len, skb->head, skb->data);
559 dnet_print_skb(skb);
560
561 /* frame size (words) */
562 len = (skb->len + 3) >> 2;
563
564 spin_lock_irqsave(&bp->lock, flags);
565
566 tx_status = dnet_readl(bp, TX_STATUS);
567
568 bufp = (unsigned int *)(((unsigned long) skb->data) & ~0x3UL);
569 wrsz = (u32) skb->len + 3;
570 wrsz += ((unsigned long) skb->data) & 0x3;
571 wrsz >>= 2;
572 tx_cmd = ((((unsigned long)(skb->data)) & 0x03) << 16) | (u32) skb->len;
573
574 /* check if there is enough room for the current frame */
575 if (wrsz < (DNET_FIFO_SIZE - dnet_readl(bp, TX_FIFO_WCNT))) {
576 for (i = 0; i < wrsz; i++)
577 dnet_writel(bp, *bufp++, TX_DATA_FIFO);
578
579 /*
580 * inform MAC that a packet's written and ready to be
581 * shipped out
582 */
583 dnet_writel(bp, tx_cmd, TX_LEN_FIFO);
584 }
585
586 if (dnet_readl(bp, TX_FIFO_WCNT) > DNET_FIFO_TX_DATA_AF_TH) {
587 netif_stop_queue(dev);
588 tx_status = dnet_readl(bp, INTR_SRC);
589 irq_enable = dnet_readl(bp, INTR_ENB);
590 irq_enable |= DNET_INTR_ENB_TX_FIFOAE;
591 dnet_writel(bp, irq_enable, INTR_ENB);
592 }
593
594 /* free the buffer */
595 dev_kfree_skb(skb);
596
597 spin_unlock_irqrestore(&bp->lock, flags);
598
599 dev->trans_start = jiffies;
600
601 return 0;
602 }
603
604 static void dnet_reset_hw(struct dnet *bp)
605 {
606 /* put ts_mac in IDLE state i.e. disable rx/tx */
607 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, DNET_INTERNAL_MODE_FCEN);
608
609 /*
610 * RX FIFO almost full threshold: only cmd FIFO almost full is
611 * implemented for RX side
612 */
613 dnet_writel(bp, DNET_FIFO_RX_CMD_AF_TH, RX_FIFO_TH);
614 /*
615 * TX FIFO almost empty threshold: only data FIFO almost empty
616 * is implemented for TX side
617 */
618 dnet_writel(bp, DNET_FIFO_TX_DATA_AE_TH, TX_FIFO_TH);
619
620 /* flush rx/tx fifos */
621 dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH,
622 SYS_CTL);
623 msleep(1);
624 dnet_writel(bp, 0, SYS_CTL);
625 }
626
627 static void dnet_init_hw(struct dnet *bp)
628 {
629 u32 config;
630
631 dnet_reset_hw(bp);
632 __dnet_set_hwaddr(bp);
633
634 config = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
635
636 if (bp->dev->flags & IFF_PROMISC)
637 /* Copy All Frames */
638 config |= DNET_INTERNAL_RXTX_CONTROL_ENPROMISC;
639 if (!(bp->dev->flags & IFF_BROADCAST))
640 /* No BroadCast */
641 config |= DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST;
642
643 config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |
644 DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
645 DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
646 DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
647
648 dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, config);
649
650 /* clear irq before enabling them */
651 config = dnet_readl(bp, INTR_SRC);
652
653 /* enable RX/TX interrupt, recv packet ready interrupt */
654 dnet_writel(bp, DNET_INTR_ENB_GLOBAL_ENABLE | DNET_INTR_ENB_RX_SUMMARY |
655 DNET_INTR_ENB_TX_SUMMARY | DNET_INTR_ENB_RX_FIFOERR |
656 DNET_INTR_ENB_RX_ERROR | DNET_INTR_ENB_RX_FIFOFULL |
657 DNET_INTR_ENB_TX_FIFOFULL | DNET_INTR_ENB_TX_DISCFRM |
658 DNET_INTR_ENB_RX_PKTRDY, INTR_ENB);
659 }
660
661 static int dnet_open(struct net_device *dev)
662 {
663 struct dnet *bp = netdev_priv(dev);
664
665 /* if the phy is not yet register, retry later */
666 if (!bp->phy_dev)
667 return -EAGAIN;
668
669 if (!is_valid_ether_addr(dev->dev_addr))
670 return -EADDRNOTAVAIL;
671
672 napi_enable(&bp->napi);
673 dnet_init_hw(bp);
674
675 phy_start_aneg(bp->phy_dev);
676
677 /* schedule a link state check */
678 phy_start(bp->phy_dev);
679
680 netif_start_queue(dev);
681
682 return 0;
683 }
684
685 static int dnet_close(struct net_device *dev)
686 {
687 struct dnet *bp = netdev_priv(dev);
688
689 netif_stop_queue(dev);
690 napi_disable(&bp->napi);
691
692 if (bp->phy_dev)
693 phy_stop(bp->phy_dev);
694
695 dnet_reset_hw(bp);
696 netif_carrier_off(dev);
697
698 return 0;
699 }
700
701 static inline void dnet_print_pretty_hwstats(struct dnet_stats *hwstat)
702 {
703 pr_debug("%s\n", __func__);
704 pr_debug("----------------------------- RX statistics "
705 "-------------------------------\n");
706 pr_debug("RX_PKT_IGNR_CNT %-8x\n", hwstat->rx_pkt_ignr);
707 pr_debug("RX_LEN_CHK_ERR_CNT %-8x\n", hwstat->rx_len_chk_err);
708 pr_debug("RX_LNG_FRM_CNT %-8x\n", hwstat->rx_lng_frm);
709 pr_debug("RX_SHRT_FRM_CNT %-8x\n", hwstat->rx_shrt_frm);
710 pr_debug("RX_IPG_VIOL_CNT %-8x\n", hwstat->rx_ipg_viol);
711 pr_debug("RX_CRC_ERR_CNT %-8x\n", hwstat->rx_crc_err);
712 pr_debug("RX_OK_PKT_CNT %-8x\n", hwstat->rx_ok_pkt);
713 pr_debug("RX_CTL_FRM_CNT %-8x\n", hwstat->rx_ctl_frm);
714 pr_debug("RX_PAUSE_FRM_CNT %-8x\n", hwstat->rx_pause_frm);
715 pr_debug("RX_MULTICAST_CNT %-8x\n", hwstat->rx_multicast);
716 pr_debug("RX_BROADCAST_CNT %-8x\n", hwstat->rx_broadcast);
717 pr_debug("RX_VLAN_TAG_CNT %-8x\n", hwstat->rx_vlan_tag);
718 pr_debug("RX_PRE_SHRINK_CNT %-8x\n", hwstat->rx_pre_shrink);
719 pr_debug("RX_DRIB_NIB_CNT %-8x\n", hwstat->rx_drib_nib);
720 pr_debug("RX_UNSUP_OPCD_CNT %-8x\n", hwstat->rx_unsup_opcd);
721 pr_debug("RX_BYTE_CNT %-8x\n", hwstat->rx_byte);
722 pr_debug("----------------------------- TX statistics "
723 "-------------------------------\n");
724 pr_debug("TX_UNICAST_CNT %-8x\n", hwstat->tx_unicast);
725 pr_debug("TX_PAUSE_FRM_CNT %-8x\n", hwstat->tx_pause_frm);
726 pr_debug("TX_MULTICAST_CNT %-8x\n", hwstat->tx_multicast);
727 pr_debug("TX_BRDCAST_CNT %-8x\n", hwstat->tx_brdcast);
728 pr_debug("TX_VLAN_TAG_CNT %-8x\n", hwstat->tx_vlan_tag);
729 pr_debug("TX_BAD_FCS_CNT %-8x\n", hwstat->tx_bad_fcs);
730 pr_debug("TX_JUMBO_CNT %-8x\n", hwstat->tx_jumbo);
731 pr_debug("TX_BYTE_CNT %-8x\n", hwstat->tx_byte);
732 }
733
734 static struct net_device_stats *dnet_get_stats(struct net_device *dev)
735 {
736
737 struct dnet *bp = netdev_priv(dev);
738 struct net_device_stats *nstat = &dev->stats;
739 struct dnet_stats *hwstat = &bp->hw_stats;
740
741 /* read stats from hardware */
742 dnet_update_stats(bp);
743
744 /* Convert HW stats into netdevice stats */
745 nstat->rx_errors = (hwstat->rx_len_chk_err +
746 hwstat->rx_lng_frm + hwstat->rx_shrt_frm +
747 /* ignore IGP violation error
748 hwstat->rx_ipg_viol + */
749 hwstat->rx_crc_err +
750 hwstat->rx_pre_shrink +
751 hwstat->rx_drib_nib + hwstat->rx_unsup_opcd);
752 nstat->tx_errors = hwstat->tx_bad_fcs;
753 nstat->rx_length_errors = (hwstat->rx_len_chk_err +
754 hwstat->rx_lng_frm +
755 hwstat->rx_shrt_frm + hwstat->rx_pre_shrink);
756 nstat->rx_crc_errors = hwstat->rx_crc_err;
757 nstat->rx_frame_errors = hwstat->rx_pre_shrink + hwstat->rx_drib_nib;
758 nstat->rx_packets = hwstat->rx_ok_pkt;
759 nstat->tx_packets = (hwstat->tx_unicast +
760 hwstat->tx_multicast + hwstat->tx_brdcast);
761 nstat->rx_bytes = hwstat->rx_byte;
762 nstat->tx_bytes = hwstat->tx_byte;
763 nstat->multicast = hwstat->rx_multicast;
764 nstat->rx_missed_errors = hwstat->rx_pkt_ignr;
765
766 dnet_print_pretty_hwstats(hwstat);
767
768 return nstat;
769 }
770
771 static int dnet_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
772 {
773 struct dnet *bp = netdev_priv(dev);
774 struct phy_device *phydev = bp->phy_dev;
775
776 if (!phydev)
777 return -ENODEV;
778
779 return phy_ethtool_gset(phydev, cmd);
780 }
781
782 static int dnet_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
783 {
784 struct dnet *bp = netdev_priv(dev);
785 struct phy_device *phydev = bp->phy_dev;
786
787 if (!phydev)
788 return -ENODEV;
789
790 return phy_ethtool_sset(phydev, cmd);
791 }
792
793 static int dnet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
794 {
795 struct dnet *bp = netdev_priv(dev);
796 struct phy_device *phydev = bp->phy_dev;
797
798 if (!netif_running(dev))
799 return -EINVAL;
800
801 if (!phydev)
802 return -ENODEV;
803
804 return phy_mii_ioctl(phydev, if_mii(rq), cmd);
805 }
806
807 static void dnet_get_drvinfo(struct net_device *dev,
808 struct ethtool_drvinfo *info)
809 {
810 strcpy(info->driver, DRV_NAME);
811 strcpy(info->version, DRV_VERSION);
812 strcpy(info->bus_info, "0");
813 }
814
815 static const struct ethtool_ops dnet_ethtool_ops = {
816 .get_settings = dnet_get_settings,
817 .set_settings = dnet_set_settings,
818 .get_drvinfo = dnet_get_drvinfo,
819 .get_link = ethtool_op_get_link,
820 };
821
822 static const struct net_device_ops dnet_netdev_ops = {
823 .ndo_open = dnet_open,
824 .ndo_stop = dnet_close,
825 .ndo_get_stats = dnet_get_stats,
826 .ndo_start_xmit = dnet_start_xmit,
827 .ndo_do_ioctl = dnet_ioctl,
828 .ndo_set_mac_address = eth_mac_addr,
829 .ndo_validate_addr = eth_validate_addr,
830 .ndo_change_mtu = eth_change_mtu,
831 };
832
833 static int __devinit dnet_probe(struct platform_device *pdev)
834 {
835 struct resource *res;
836 struct net_device *dev;
837 struct dnet *bp;
838 struct phy_device *phydev;
839 int err = -ENXIO;
840 unsigned int mem_base, mem_size, irq;
841
842 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
843 if (!res) {
844 dev_err(&pdev->dev, "no mmio resource defined\n");
845 goto err_out;
846 }
847 mem_base = res->start;
848 mem_size = resource_size(res);
849 irq = platform_get_irq(pdev, 0);
850
851 if (!request_mem_region(mem_base, mem_size, DRV_NAME)) {
852 dev_err(&pdev->dev, "no memory region available\n");
853 err = -EBUSY;
854 goto err_out;
855 }
856
857 err = -ENOMEM;
858 dev = alloc_etherdev(sizeof(*bp));
859 if (!dev) {
860 dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
861 goto err_out;
862 }
863
864 /* TODO: Actually, we have some interesting features... */
865 dev->features |= 0;
866
867 bp = netdev_priv(dev);
868 bp->dev = dev;
869
870 SET_NETDEV_DEV(dev, &pdev->dev);
871
872 spin_lock_init(&bp->lock);
873
874 bp->regs = ioremap(mem_base, mem_size);
875 if (!bp->regs) {
876 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
877 err = -ENOMEM;
878 goto err_out_free_dev;
879 }
880
881 dev->irq = irq;
882 err = request_irq(dev->irq, dnet_interrupt, 0, DRV_NAME, dev);
883 if (err) {
884 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
885 irq, err);
886 goto err_out_iounmap;
887 }
888
889 dev->netdev_ops = &dnet_netdev_ops;
890 netif_napi_add(dev, &bp->napi, dnet_poll, 64);
891 dev->ethtool_ops = &dnet_ethtool_ops;
892
893 dev->base_addr = (unsigned long)bp->regs;
894
895 bp->capabilities = dnet_readl(bp, VERCAPS) & DNET_CAPS_MASK;
896
897 dnet_get_hwaddr(bp);
898
899 if (!is_valid_ether_addr(dev->dev_addr)) {
900 /* choose a random ethernet address */
901 random_ether_addr(dev->dev_addr);
902 __dnet_set_hwaddr(bp);
903 }
904
905 err = register_netdev(dev);
906 if (err) {
907 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
908 goto err_out_free_irq;
909 }
910
911 /* register the PHY board fixup (for Marvell 88E1111) */
912 err = phy_register_fixup_for_uid(0x01410cc0, 0xfffffff0,
913 dnet_phy_marvell_fixup);
914 /* we can live without it, so just issue a warning */
915 if (err)
916 dev_warn(&pdev->dev, "Cannot register PHY board fixup.\n");
917
918 if (dnet_mii_init(bp) != 0)
919 goto err_out_unregister_netdev;
920
921 dev_info(&pdev->dev, "Dave DNET at 0x%p (0x%08x) irq %d %pM\n",
922 bp->regs, mem_base, dev->irq, dev->dev_addr);
923 dev_info(&pdev->dev, "has %smdio, %sirq, %sgigabit, %sdma \n",
924 (bp->capabilities & DNET_HAS_MDIO) ? "" : "no ",
925 (bp->capabilities & DNET_HAS_IRQ) ? "" : "no ",
926 (bp->capabilities & DNET_HAS_GIGABIT) ? "" : "no ",
927 (bp->capabilities & DNET_HAS_DMA) ? "" : "no ");
928 phydev = bp->phy_dev;
929 dev_info(&pdev->dev, "attached PHY driver [%s] "
930 "(mii_bus:phy_addr=%s, irq=%d)\n",
931 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
932
933 return 0;
934
935 err_out_unregister_netdev:
936 unregister_netdev(dev);
937 err_out_free_irq:
938 free_irq(dev->irq, dev);
939 err_out_iounmap:
940 iounmap(bp->regs);
941 err_out_free_dev:
942 free_netdev(dev);
943 err_out:
944 return err;
945 }
946
947 static int __devexit dnet_remove(struct platform_device *pdev)
948 {
949
950 struct net_device *dev;
951 struct dnet *bp;
952
953 dev = platform_get_drvdata(pdev);
954
955 if (dev) {
956 bp = netdev_priv(dev);
957 if (bp->phy_dev)
958 phy_disconnect(bp->phy_dev);
959 mdiobus_unregister(bp->mii_bus);
960 kfree(bp->mii_bus->irq);
961 mdiobus_free(bp->mii_bus);
962 unregister_netdev(dev);
963 free_irq(dev->irq, dev);
964 iounmap(bp->regs);
965 free_netdev(dev);
966 }
967
968 return 0;
969 }
970
971 static struct platform_driver dnet_driver = {
972 .probe = dnet_probe,
973 .remove = __devexit_p(dnet_remove),
974 .driver = {
975 .name = "dnet",
976 },
977 };
978
979 static int __init dnet_init(void)
980 {
981 return platform_driver_register(&dnet_driver);
982 }
983
984 static void __exit dnet_exit(void)
985 {
986 platform_driver_unregister(&dnet_driver);
987 }
988
989 module_init(dnet_init);
990 module_exit(dnet_exit);
991
992 MODULE_LICENSE("GPL");
993 MODULE_DESCRIPTION("Dave DNET Ethernet driver");
994 MODULE_AUTHOR("Ilya Yanok <yanok@emcraft.com>, "
995 "Matteo Vit <matteo.vit@dave.eu>");
Nao low-level kernelspace/userspace library that runs on our robots, Nao-Team HTWK