2 * drivers/mtd/nand/pxa3xx_nand.c
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/delay.h>
17 #include <linux/clk.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/mtd/partitions.h>
22 #include <linux/irq.h>
25 #include <mach/pxa-regs.h>
26 #include <mach/pxa3xx_nand.h>
28 #define CHIP_DELAY_TIMEOUT (2 * HZ/10)
30 /* registers and bit definitions */
31 #define NDCR (0x00) /* Control register */
32 #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
33 #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
34 #define NDSR (0x14) /* Status Register */
35 #define NDPCR (0x18) /* Page Count Register */
36 #define NDBDR0 (0x1C) /* Bad Block Register 0 */
37 #define NDBDR1 (0x20) /* Bad Block Register 1 */
38 #define NDDB (0x40) /* Data Buffer */
39 #define NDCB0 (0x48) /* Command Buffer0 */
40 #define NDCB1 (0x4C) /* Command Buffer1 */
41 #define NDCB2 (0x50) /* Command Buffer2 */
43 #define NDCR_SPARE_EN (0x1 << 31)
44 #define NDCR_ECC_EN (0x1 << 30)
45 #define NDCR_DMA_EN (0x1 << 29)
46 #define NDCR_ND_RUN (0x1 << 28)
47 #define NDCR_DWIDTH_C (0x1 << 27)
48 #define NDCR_DWIDTH_M (0x1 << 26)
49 #define NDCR_PAGE_SZ (0x1 << 24)
50 #define NDCR_NCSX (0x1 << 23)
51 #define NDCR_ND_MODE (0x3 << 21)
52 #define NDCR_NAND_MODE (0x0)
53 #define NDCR_CLR_PG_CNT (0x1 << 20)
54 #define NDCR_CLR_ECC (0x1 << 19)
55 #define NDCR_RD_ID_CNT_MASK (0x7 << 16)
56 #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
58 #define NDCR_RA_START (0x1 << 15)
59 #define NDCR_PG_PER_BLK (0x1 << 14)
60 #define NDCR_ND_ARB_EN (0x1 << 12)
62 #define NDSR_MASK (0xfff)
63 #define NDSR_RDY (0x1 << 11)
64 #define NDSR_CS0_PAGED (0x1 << 10)
65 #define NDSR_CS1_PAGED (0x1 << 9)
66 #define NDSR_CS0_CMDD (0x1 << 8)
67 #define NDSR_CS1_CMDD (0x1 << 7)
68 #define NDSR_CS0_BBD (0x1 << 6)
69 #define NDSR_CS1_BBD (0x1 << 5)
70 #define NDSR_DBERR (0x1 << 4)
71 #define NDSR_SBERR (0x1 << 3)
72 #define NDSR_WRDREQ (0x1 << 2)
73 #define NDSR_RDDREQ (0x1 << 1)
74 #define NDSR_WRCMDREQ (0x1)
76 #define NDCB0_AUTO_RS (0x1 << 25)
77 #define NDCB0_CSEL (0x1 << 24)
78 #define NDCB0_CMD_TYPE_MASK (0x7 << 21)
79 #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
80 #define NDCB0_NC (0x1 << 20)
81 #define NDCB0_DBC (0x1 << 19)
82 #define NDCB0_ADDR_CYC_MASK (0x7 << 16)
83 #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
84 #define NDCB0_CMD2_MASK (0xff << 8)
85 #define NDCB0_CMD1_MASK (0xff)
86 #define NDCB0_ADDR_CYC_SHIFT (16)
88 /* dma-able I/O address for the NAND data and commands */
89 #define NDCB0_DMA_ADDR (0x43100048)
90 #define NDDB_DMA_ADDR (0x43100040)
92 /* macros for registers read/write */
93 #define nand_writel(info, off, val) \
94 __raw_writel((val), (info)->mmio_base + (off))
96 #define nand_readl(info, off) \
97 __raw_readl((info)->mmio_base + (off))
99 /* error code and state */
118 struct pxa3xx_nand_info
{
119 struct nand_chip nand_chip
;
121 struct platform_device
*pdev
;
122 const struct pxa3xx_nand_flash
*flash_info
;
125 void __iomem
*mmio_base
;
127 unsigned int buf_start
;
128 unsigned int buf_count
;
130 /* DMA information */
134 unsigned char *data_buff
;
135 dma_addr_t data_buff_phys
;
136 size_t data_buff_size
;
138 struct pxa_dma_desc
*data_desc
;
139 dma_addr_t data_desc_addr
;
143 /* saved column/page_addr during CMD_SEQIN */
147 /* relate to the command */
150 int use_ecc
; /* use HW ECC ? */
151 int use_dma
; /* use DMA ? */
153 size_t data_size
; /* data size in FIFO */
155 struct completion cmd_complete
;
157 /* generated NDCBx register values */
162 /* calculated from pxa3xx_nand_flash data */
164 size_t read_id_bytes
;
166 unsigned int col_addr_cycles
;
167 unsigned int row_addr_cycles
;
170 static int use_dma
= 1;
171 module_param(use_dma
, bool, 0444);
172 MODULE_PARM_DESC(use_dma
, "enable DMA for data transfering to/from NAND HW");
174 #ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
175 static struct pxa3xx_nand_cmdset smallpage_cmdset
= {
179 .read_status
= 0x0070,
185 .lock_status
= 0x007A,
188 static struct pxa3xx_nand_cmdset largepage_cmdset
= {
192 .read_status
= 0x0070,
198 .lock_status
= 0x007A,
201 static struct pxa3xx_nand_timing samsung512MbX16_timing
= {
213 static struct pxa3xx_nand_flash samsung512MbX16
= {
214 .timing
= &samsung512MbX16_timing
,
215 .cmdset
= &smallpage_cmdset
,
216 .page_per_block
= 32,
224 static struct pxa3xx_nand_timing micron_timing
= {
236 static struct pxa3xx_nand_flash micron1GbX8
= {
237 .timing
= µn_timing
,
238 .cmdset
= &largepage_cmdset
,
239 .page_per_block
= 64,
247 static struct pxa3xx_nand_flash micron1GbX16
= {
248 .timing
= µn_timing
,
249 .cmdset
= &largepage_cmdset
,
250 .page_per_block
= 64,
258 static struct pxa3xx_nand_timing stm2GbX16_timing
= {
270 static struct pxa3xx_nand_flash stm2GbX16
= {
271 .timing
= &stm2GbX16_timing
,
272 .cmdset
= &largepage_cmdset
,
273 .page_per_block
= 64,
281 static struct pxa3xx_nand_flash
*builtin_flash_types
[] = {
287 #endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */
289 #define NDTR0_tCH(c) (min((c), 7) << 19)
290 #define NDTR0_tCS(c) (min((c), 7) << 16)
291 #define NDTR0_tWH(c) (min((c), 7) << 11)
292 #define NDTR0_tWP(c) (min((c), 7) << 8)
293 #define NDTR0_tRH(c) (min((c), 7) << 3)
294 #define NDTR0_tRP(c) (min((c), 7) << 0)
296 #define NDTR1_tR(c) (min((c), 65535) << 16)
297 #define NDTR1_tWHR(c) (min((c), 15) << 4)
298 #define NDTR1_tAR(c) (min((c), 15) << 0)
300 /* convert nano-seconds to nand flash controller clock cycles */
301 #define ns2cycle(ns, clk) (int)(((ns) * (clk / 1000000) / 1000) - 1)
303 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info
*info
,
304 const struct pxa3xx_nand_timing
*t
)
306 unsigned long nand_clk
= clk_get_rate(info
->clk
);
307 uint32_t ndtr0
, ndtr1
;
309 ndtr0
= NDTR0_tCH(ns2cycle(t
->tCH
, nand_clk
)) |
310 NDTR0_tCS(ns2cycle(t
->tCS
, nand_clk
)) |
311 NDTR0_tWH(ns2cycle(t
->tWH
, nand_clk
)) |
312 NDTR0_tWP(ns2cycle(t
->tWP
, nand_clk
)) |
313 NDTR0_tRH(ns2cycle(t
->tRH
, nand_clk
)) |
314 NDTR0_tRP(ns2cycle(t
->tRP
, nand_clk
));
316 ndtr1
= NDTR1_tR(ns2cycle(t
->tR
, nand_clk
)) |
317 NDTR1_tWHR(ns2cycle(t
->tWHR
, nand_clk
)) |
318 NDTR1_tAR(ns2cycle(t
->tAR
, nand_clk
));
320 nand_writel(info
, NDTR0CS0
, ndtr0
);
321 nand_writel(info
, NDTR1CS0
, ndtr1
);
324 #define WAIT_EVENT_TIMEOUT 10
326 static int wait_for_event(struct pxa3xx_nand_info
*info
, uint32_t event
)
328 int timeout
= WAIT_EVENT_TIMEOUT
;
332 ndsr
= nand_readl(info
, NDSR
) & NDSR_MASK
;
334 nand_writel(info
, NDSR
, ndsr
);
343 static int prepare_read_prog_cmd(struct pxa3xx_nand_info
*info
,
344 uint16_t cmd
, int column
, int page_addr
)
346 const struct pxa3xx_nand_flash
*f
= info
->flash_info
;
347 const struct pxa3xx_nand_cmdset
*cmdset
= f
->cmdset
;
349 /* calculate data size */
350 switch (f
->page_size
) {
352 info
->data_size
= (info
->use_ecc
) ? 2088 : 2112;
355 info
->data_size
= (info
->use_ecc
) ? 520 : 528;
361 /* generate values for NDCBx registers */
362 info
->ndcb0
= cmd
| ((cmd
& 0xff00) ? NDCB0_DBC
: 0);
365 info
->ndcb0
|= NDCB0_ADDR_CYC(info
->row_addr_cycles
+ info
->col_addr_cycles
);
367 if (info
->col_addr_cycles
== 2) {
368 /* large block, 2 cycles for column address
369 * row address starts from 3rd cycle
371 info
->ndcb1
|= page_addr
<< 16;
372 if (info
->row_addr_cycles
== 3)
373 info
->ndcb2
= (page_addr
>> 16) & 0xff;
375 /* small block, 1 cycles for column address
376 * row address starts from 2nd cycle
378 info
->ndcb1
= page_addr
<< 8;
380 if (cmd
== cmdset
->program
)
381 info
->ndcb0
|= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS
;
386 static int prepare_erase_cmd(struct pxa3xx_nand_info
*info
,
387 uint16_t cmd
, int page_addr
)
389 info
->ndcb0
= cmd
| ((cmd
& 0xff00) ? NDCB0_DBC
: 0);
390 info
->ndcb0
|= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS
| NDCB0_ADDR_CYC(3);
391 info
->ndcb1
= page_addr
;
396 static int prepare_other_cmd(struct pxa3xx_nand_info
*info
, uint16_t cmd
)
398 const struct pxa3xx_nand_cmdset
*cmdset
= info
->flash_info
->cmdset
;
400 info
->ndcb0
= cmd
| ((cmd
& 0xff00) ? NDCB0_DBC
: 0);
404 if (cmd
== cmdset
->read_id
) {
405 info
->ndcb0
|= NDCB0_CMD_TYPE(3);
407 } else if (cmd
== cmdset
->read_status
) {
408 info
->ndcb0
|= NDCB0_CMD_TYPE(4);
410 } else if (cmd
== cmdset
->reset
|| cmd
== cmdset
->lock
||
411 cmd
== cmdset
->unlock
) {
412 info
->ndcb0
|= NDCB0_CMD_TYPE(5);
419 static void enable_int(struct pxa3xx_nand_info
*info
, uint32_t int_mask
)
423 ndcr
= nand_readl(info
, NDCR
);
424 nand_writel(info
, NDCR
, ndcr
& ~int_mask
);
427 static void disable_int(struct pxa3xx_nand_info
*info
, uint32_t int_mask
)
431 ndcr
= nand_readl(info
, NDCR
);
432 nand_writel(info
, NDCR
, ndcr
| int_mask
);
435 /* NOTE: it is a must to set ND_RUN firstly, then write command buffer
436 * otherwise, it does not work
438 static int write_cmd(struct pxa3xx_nand_info
*info
)
442 /* clear status bits and run */
443 nand_writel(info
, NDSR
, NDSR_MASK
);
445 ndcr
= info
->reg_ndcr
;
447 ndcr
|= info
->use_ecc
? NDCR_ECC_EN
: 0;
448 ndcr
|= info
->use_dma
? NDCR_DMA_EN
: 0;
451 nand_writel(info
, NDCR
, ndcr
);
453 if (wait_for_event(info
, NDSR_WRCMDREQ
)) {
454 printk(KERN_ERR
"timed out writing command\n");
458 nand_writel(info
, NDCB0
, info
->ndcb0
);
459 nand_writel(info
, NDCB0
, info
->ndcb1
);
460 nand_writel(info
, NDCB0
, info
->ndcb2
);
464 static int handle_data_pio(struct pxa3xx_nand_info
*info
)
466 int ret
, timeout
= CHIP_DELAY_TIMEOUT
;
468 switch (info
->state
) {
469 case STATE_PIO_WRITING
:
470 __raw_writesl(info
->mmio_base
+ NDDB
, info
->data_buff
,
471 info
->data_size
<< 2);
473 enable_int(info
, NDSR_CS0_BBD
| NDSR_CS0_CMDD
);
475 ret
= wait_for_completion_timeout(&info
->cmd_complete
, timeout
);
477 printk(KERN_ERR
"program command time out\n");
481 case STATE_PIO_READING
:
482 __raw_readsl(info
->mmio_base
+ NDDB
, info
->data_buff
,
483 info
->data_size
<< 2);
486 printk(KERN_ERR
"%s: invalid state %d\n", __func__
,
491 info
->state
= STATE_READY
;
495 static void start_data_dma(struct pxa3xx_nand_info
*info
, int dir_out
)
497 struct pxa_dma_desc
*desc
= info
->data_desc
;
498 int dma_len
= ALIGN(info
->data_size
, 32);
500 desc
->ddadr
= DDADR_STOP
;
501 desc
->dcmd
= DCMD_ENDIRQEN
| DCMD_WIDTH4
| DCMD_BURST32
| dma_len
;
504 desc
->dsadr
= info
->data_buff_phys
;
505 desc
->dtadr
= NDDB_DMA_ADDR
;
506 desc
->dcmd
|= DCMD_INCSRCADDR
| DCMD_FLOWTRG
;
508 desc
->dtadr
= info
->data_buff_phys
;
509 desc
->dsadr
= NDDB_DMA_ADDR
;
510 desc
->dcmd
|= DCMD_INCTRGADDR
| DCMD_FLOWSRC
;
513 DRCMR(info
->drcmr_dat
) = DRCMR_MAPVLD
| info
->data_dma_ch
;
514 DDADR(info
->data_dma_ch
) = info
->data_desc_addr
;
515 DCSR(info
->data_dma_ch
) |= DCSR_RUN
;
518 static void pxa3xx_nand_data_dma_irq(int channel
, void *data
)
520 struct pxa3xx_nand_info
*info
= data
;
523 dcsr
= DCSR(channel
);
524 DCSR(channel
) = dcsr
;
526 if (dcsr
& DCSR_BUSERR
) {
527 info
->retcode
= ERR_DMABUSERR
;
528 complete(&info
->cmd_complete
);
531 if (info
->state
== STATE_DMA_WRITING
) {
532 info
->state
= STATE_DMA_DONE
;
533 enable_int(info
, NDSR_CS0_BBD
| NDSR_CS0_CMDD
);
535 info
->state
= STATE_READY
;
536 complete(&info
->cmd_complete
);
540 static irqreturn_t
pxa3xx_nand_irq(int irq
, void *devid
)
542 struct pxa3xx_nand_info
*info
= devid
;
545 status
= nand_readl(info
, NDSR
);
547 if (status
& (NDSR_RDDREQ
| NDSR_DBERR
)) {
548 if (status
& NDSR_DBERR
)
549 info
->retcode
= ERR_DBERR
;
551 disable_int(info
, NDSR_RDDREQ
| NDSR_DBERR
);
554 info
->state
= STATE_DMA_READING
;
555 start_data_dma(info
, 0);
557 info
->state
= STATE_PIO_READING
;
558 complete(&info
->cmd_complete
);
560 } else if (status
& NDSR_WRDREQ
) {
561 disable_int(info
, NDSR_WRDREQ
);
563 info
->state
= STATE_DMA_WRITING
;
564 start_data_dma(info
, 1);
566 info
->state
= STATE_PIO_WRITING
;
567 complete(&info
->cmd_complete
);
569 } else if (status
& (NDSR_CS0_BBD
| NDSR_CS0_CMDD
)) {
570 if (status
& NDSR_CS0_BBD
)
571 info
->retcode
= ERR_BBERR
;
573 disable_int(info
, NDSR_CS0_BBD
| NDSR_CS0_CMDD
);
574 info
->state
= STATE_READY
;
575 complete(&info
->cmd_complete
);
577 nand_writel(info
, NDSR
, status
);
581 static int pxa3xx_nand_do_cmd(struct pxa3xx_nand_info
*info
, uint32_t event
)
584 int ret
, timeout
= CHIP_DELAY_TIMEOUT
;
586 if (write_cmd(info
)) {
587 info
->retcode
= ERR_SENDCMD
;
591 info
->state
= STATE_CMD_HANDLE
;
593 enable_int(info
, event
);
595 ret
= wait_for_completion_timeout(&info
->cmd_complete
, timeout
);
597 printk(KERN_ERR
"command execution timed out\n");
598 info
->retcode
= ERR_SENDCMD
;
602 if (info
->use_dma
== 0 && info
->data_size
> 0)
603 if (handle_data_pio(info
))
609 ndcr
= nand_readl(info
, NDCR
);
610 nand_writel(info
, NDCR
, ndcr
& ~NDCR_ND_RUN
);
615 static int pxa3xx_nand_dev_ready(struct mtd_info
*mtd
)
617 struct pxa3xx_nand_info
*info
= mtd
->priv
;
618 return (nand_readl(info
, NDSR
) & NDSR_RDY
) ? 1 : 0;
621 static inline int is_buf_blank(uint8_t *buf
, size_t len
)
623 for (; len
> 0; len
--)
629 static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd
, unsigned command
,
630 int column
, int page_addr
)
632 struct pxa3xx_nand_info
*info
= mtd
->priv
;
633 const struct pxa3xx_nand_flash
*flash_info
= info
->flash_info
;
634 const struct pxa3xx_nand_cmdset
*cmdset
= flash_info
->cmdset
;
637 info
->use_dma
= (use_dma
) ? 1 : 0;
640 info
->state
= STATE_READY
;
642 init_completion(&info
->cmd_complete
);
645 case NAND_CMD_READOOB
:
646 /* disable HW ECC to get all the OOB data */
647 info
->buf_count
= mtd
->writesize
+ mtd
->oobsize
;
648 info
->buf_start
= mtd
->writesize
+ column
;
650 if (prepare_read_prog_cmd(info
, cmdset
->read1
, column
, page_addr
))
653 pxa3xx_nand_do_cmd(info
, NDSR_RDDREQ
| NDSR_DBERR
);
655 /* We only are OOB, so if the data has error, does not matter */
656 if (info
->retcode
== ERR_DBERR
)
657 info
->retcode
= ERR_NONE
;
662 info
->retcode
= ERR_NONE
;
663 info
->buf_start
= column
;
664 info
->buf_count
= mtd
->writesize
+ mtd
->oobsize
;
665 memset(info
->data_buff
, 0xFF, info
->buf_count
);
667 if (prepare_read_prog_cmd(info
, cmdset
->read1
, column
, page_addr
))
670 pxa3xx_nand_do_cmd(info
, NDSR_RDDREQ
| NDSR_DBERR
);
672 if (info
->retcode
== ERR_DBERR
) {
673 /* for blank page (all 0xff), HW will calculate its ECC as
674 * 0, which is different from the ECC information within
675 * OOB, ignore such double bit errors
677 if (is_buf_blank(info
->data_buff
, mtd
->writesize
))
678 info
->retcode
= ERR_NONE
;
682 info
->buf_start
= column
;
683 info
->buf_count
= mtd
->writesize
+ mtd
->oobsize
;
684 memset(info
->data_buff
, 0xff, info
->buf_count
);
686 /* save column/page_addr for next CMD_PAGEPROG */
687 info
->seqin_column
= column
;
688 info
->seqin_page_addr
= page_addr
;
690 case NAND_CMD_PAGEPROG
:
691 info
->use_ecc
= (info
->seqin_column
>= mtd
->writesize
) ? 0 : 1;
693 if (prepare_read_prog_cmd(info
, cmdset
->program
,
694 info
->seqin_column
, info
->seqin_page_addr
))
697 pxa3xx_nand_do_cmd(info
, NDSR_WRDREQ
);
699 case NAND_CMD_ERASE1
:
700 if (prepare_erase_cmd(info
, cmdset
->erase
, page_addr
))
703 pxa3xx_nand_do_cmd(info
, NDSR_CS0_BBD
| NDSR_CS0_CMDD
);
705 case NAND_CMD_ERASE2
:
707 case NAND_CMD_READID
:
708 case NAND_CMD_STATUS
:
709 info
->use_dma
= 0; /* force PIO read */
711 info
->buf_count
= (command
== NAND_CMD_READID
) ?
712 info
->read_id_bytes
: 1;
714 if (prepare_other_cmd(info
, (command
== NAND_CMD_READID
) ?
715 cmdset
->read_id
: cmdset
->read_status
))
718 pxa3xx_nand_do_cmd(info
, NDSR_RDDREQ
);
721 if (prepare_other_cmd(info
, cmdset
->reset
))
724 ret
= pxa3xx_nand_do_cmd(info
, NDSR_CS0_CMDD
);
730 if (nand_readl(info
, NDSR
) & NDSR_RDY
)
735 ndcr
= nand_readl(info
, NDCR
);
736 nand_writel(info
, NDCR
, ndcr
& ~NDCR_ND_RUN
);
740 printk(KERN_ERR
"non-supported command.\n");
744 if (info
->retcode
== ERR_DBERR
) {
745 printk(KERN_ERR
"double bit error @ page %08x\n", page_addr
);
746 info
->retcode
= ERR_NONE
;
750 static uint8_t pxa3xx_nand_read_byte(struct mtd_info
*mtd
)
752 struct pxa3xx_nand_info
*info
= mtd
->priv
;
755 if (info
->buf_start
< info
->buf_count
)
756 /* Has just send a new command? */
757 retval
= info
->data_buff
[info
->buf_start
++];
762 static u16
pxa3xx_nand_read_word(struct mtd_info
*mtd
)
764 struct pxa3xx_nand_info
*info
= mtd
->priv
;
767 if (!(info
->buf_start
& 0x01) && info
->buf_start
< info
->buf_count
) {
768 retval
= *((u16
*)(info
->data_buff
+info
->buf_start
));
769 info
->buf_start
+= 2;
774 static void pxa3xx_nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
776 struct pxa3xx_nand_info
*info
= mtd
->priv
;
777 int real_len
= min_t(size_t, len
, info
->buf_count
- info
->buf_start
);
779 memcpy(buf
, info
->data_buff
+ info
->buf_start
, real_len
);
780 info
->buf_start
+= real_len
;
783 static void pxa3xx_nand_write_buf(struct mtd_info
*mtd
,
784 const uint8_t *buf
, int len
)
786 struct pxa3xx_nand_info
*info
= mtd
->priv
;
787 int real_len
= min_t(size_t, len
, info
->buf_count
- info
->buf_start
);
789 memcpy(info
->data_buff
+ info
->buf_start
, buf
, real_len
);
790 info
->buf_start
+= real_len
;
793 static int pxa3xx_nand_verify_buf(struct mtd_info
*mtd
,
794 const uint8_t *buf
, int len
)
799 static void pxa3xx_nand_select_chip(struct mtd_info
*mtd
, int chip
)
804 static int pxa3xx_nand_waitfunc(struct mtd_info
*mtd
, struct nand_chip
*this)
806 struct pxa3xx_nand_info
*info
= mtd
->priv
;
808 /* pxa3xx_nand_send_command has waited for command complete */
809 if (this->state
== FL_WRITING
|| this->state
== FL_ERASING
) {
810 if (info
->retcode
== ERR_NONE
)
814 * any error make it return 0x01 which will tell
815 * the caller the erase and write fail
824 static void pxa3xx_nand_ecc_hwctl(struct mtd_info
*mtd
, int mode
)
829 static int pxa3xx_nand_ecc_calculate(struct mtd_info
*mtd
,
830 const uint8_t *dat
, uint8_t *ecc_code
)
835 static int pxa3xx_nand_ecc_correct(struct mtd_info
*mtd
,
836 uint8_t *dat
, uint8_t *read_ecc
, uint8_t *calc_ecc
)
838 struct pxa3xx_nand_info
*info
= mtd
->priv
;
840 * Any error include ERR_SEND_CMD, ERR_DBERR, ERR_BUSERR, we
841 * consider it as a ecc error which will tell the caller the
842 * read fail We have distinguish all the errors, but the
843 * nand_read_ecc only check this function return value
845 if (info
->retcode
!= ERR_NONE
)
851 static int __readid(struct pxa3xx_nand_info
*info
, uint32_t *id
)
853 const struct pxa3xx_nand_flash
*f
= info
->flash_info
;
854 const struct pxa3xx_nand_cmdset
*cmdset
= f
->cmdset
;
858 if (prepare_other_cmd(info
, cmdset
->read_id
)) {
859 printk(KERN_ERR
"failed to prepare command\n");
867 /* Wait for CMDDM(command done successfully) */
868 if (wait_for_event(info
, NDSR_RDDREQ
))
871 __raw_readsl(info
->mmio_base
+ NDDB
, id_buff
, 2);
872 *id
= id_buff
[0] | (id_buff
[1] << 8);
876 ndcr
= nand_readl(info
, NDCR
);
877 nand_writel(info
, NDCR
, ndcr
& ~NDCR_ND_RUN
);
882 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info
*info
,
883 const struct pxa3xx_nand_flash
*f
)
885 struct platform_device
*pdev
= info
->pdev
;
886 struct pxa3xx_nand_platform_data
*pdata
= pdev
->dev
.platform_data
;
887 uint32_t ndcr
= 0x00000FFF; /* disable all interrupts */
889 if (f
->page_size
!= 2048 && f
->page_size
!= 512)
892 if (f
->flash_width
!= 16 && f
->flash_width
!= 8)
895 /* calculate flash information */
896 info
->oob_size
= (f
->page_size
== 2048) ? 64 : 16;
897 info
->read_id_bytes
= (f
->page_size
== 2048) ? 4 : 2;
899 /* calculate addressing information */
900 info
->col_addr_cycles
= (f
->page_size
== 2048) ? 2 : 1;
902 if (f
->num_blocks
* f
->page_per_block
> 65536)
903 info
->row_addr_cycles
= 3;
905 info
->row_addr_cycles
= 2;
907 ndcr
|= (pdata
->enable_arbiter
) ? NDCR_ND_ARB_EN
: 0;
908 ndcr
|= (info
->col_addr_cycles
== 2) ? NDCR_RA_START
: 0;
909 ndcr
|= (f
->page_per_block
== 64) ? NDCR_PG_PER_BLK
: 0;
910 ndcr
|= (f
->page_size
== 2048) ? NDCR_PAGE_SZ
: 0;
911 ndcr
|= (f
->flash_width
== 16) ? NDCR_DWIDTH_M
: 0;
912 ndcr
|= (f
->dfc_width
== 16) ? NDCR_DWIDTH_C
: 0;
914 ndcr
|= NDCR_RD_ID_CNT(info
->read_id_bytes
);
915 ndcr
|= NDCR_SPARE_EN
; /* enable spare by default */
917 info
->reg_ndcr
= ndcr
;
919 pxa3xx_nand_set_timing(info
, f
->timing
);
920 info
->flash_info
= f
;
924 static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info
*info
,
925 const struct pxa3xx_nand_platform_data
*pdata
)
927 const struct pxa3xx_nand_flash
*f
;
931 for (i
= 0; i
<pdata
->num_flash
; ++i
) {
932 f
= pdata
->flash
+ i
;
934 if (pxa3xx_nand_config_flash(info
, f
))
937 if (__readid(info
, &id
))
940 if (id
== f
->chip_id
)
944 #ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
945 for (i
= 0; i
< ARRAY_SIZE(builtin_flash_types
); i
++) {
947 f
= builtin_flash_types
[i
];
949 if (pxa3xx_nand_config_flash(info
, f
))
952 if (__readid(info
, &id
))
955 if (id
== f
->chip_id
)
960 dev_warn(&info
->pdev
->dev
,
961 "failed to detect configured nand flash; found %04x instead of\n",
966 /* the maximum possible buffer size for large page with OOB data
967 * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
968 * data buffer and the DMA descriptor
970 #define MAX_BUFF_SIZE PAGE_SIZE
972 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info
*info
)
974 struct platform_device
*pdev
= info
->pdev
;
975 int data_desc_offset
= MAX_BUFF_SIZE
- sizeof(struct pxa_dma_desc
);
978 info
->data_buff
= kmalloc(MAX_BUFF_SIZE
, GFP_KERNEL
);
979 if (info
->data_buff
== NULL
)
984 info
->data_buff
= dma_alloc_coherent(&pdev
->dev
, MAX_BUFF_SIZE
,
985 &info
->data_buff_phys
, GFP_KERNEL
);
986 if (info
->data_buff
== NULL
) {
987 dev_err(&pdev
->dev
, "failed to allocate dma buffer\n");
991 info
->data_buff_size
= MAX_BUFF_SIZE
;
992 info
->data_desc
= (void *)info
->data_buff
+ data_desc_offset
;
993 info
->data_desc_addr
= info
->data_buff_phys
+ data_desc_offset
;
995 info
->data_dma_ch
= pxa_request_dma("nand-data", DMA_PRIO_LOW
,
996 pxa3xx_nand_data_dma_irq
, info
);
997 if (info
->data_dma_ch
< 0) {
998 dev_err(&pdev
->dev
, "failed to request data dma\n");
999 dma_free_coherent(&pdev
->dev
, info
->data_buff_size
,
1000 info
->data_buff
, info
->data_buff_phys
);
1001 return info
->data_dma_ch
;
1007 static struct nand_ecclayout hw_smallpage_ecclayout
= {
1009 .eccpos
= {8, 9, 10, 11, 12, 13 },
1010 .oobfree
= { {2, 6} }
1013 static struct nand_ecclayout hw_largepage_ecclayout
= {
1016 40, 41, 42, 43, 44, 45, 46, 47,
1017 48, 49, 50, 51, 52, 53, 54, 55,
1018 56, 57, 58, 59, 60, 61, 62, 63},
1019 .oobfree
= { {2, 38} }
1022 static void pxa3xx_nand_init_mtd(struct mtd_info
*mtd
,
1023 struct pxa3xx_nand_info
*info
)
1025 const struct pxa3xx_nand_flash
*f
= info
->flash_info
;
1026 struct nand_chip
*this = &info
->nand_chip
;
1028 this->options
= (f
->flash_width
== 16) ? NAND_BUSWIDTH_16
: 0;
1030 this->waitfunc
= pxa3xx_nand_waitfunc
;
1031 this->select_chip
= pxa3xx_nand_select_chip
;
1032 this->dev_ready
= pxa3xx_nand_dev_ready
;
1033 this->cmdfunc
= pxa3xx_nand_cmdfunc
;
1034 this->read_word
= pxa3xx_nand_read_word
;
1035 this->read_byte
= pxa3xx_nand_read_byte
;
1036 this->read_buf
= pxa3xx_nand_read_buf
;
1037 this->write_buf
= pxa3xx_nand_write_buf
;
1038 this->verify_buf
= pxa3xx_nand_verify_buf
;
1040 this->ecc
.mode
= NAND_ECC_HW
;
1041 this->ecc
.hwctl
= pxa3xx_nand_ecc_hwctl
;
1042 this->ecc
.calculate
= pxa3xx_nand_ecc_calculate
;
1043 this->ecc
.correct
= pxa3xx_nand_ecc_correct
;
1044 this->ecc
.size
= f
->page_size
;
1046 if (f
->page_size
== 2048)
1047 this->ecc
.layout
= &hw_largepage_ecclayout
;
1049 this->ecc
.layout
= &hw_smallpage_ecclayout
;
1051 this->chip_delay
= 25;
1054 static int pxa3xx_nand_probe(struct platform_device
*pdev
)
1056 struct pxa3xx_nand_platform_data
*pdata
;
1057 struct pxa3xx_nand_info
*info
;
1058 struct nand_chip
*this;
1059 struct mtd_info
*mtd
;
1063 pdata
= pdev
->dev
.platform_data
;
1066 dev_err(&pdev
->dev
, "no platform data defined\n");
1070 mtd
= kzalloc(sizeof(struct mtd_info
) + sizeof(struct pxa3xx_nand_info
),
1073 dev_err(&pdev
->dev
, "failed to allocate memory\n");
1077 info
= (struct pxa3xx_nand_info
*)(&mtd
[1]);
1080 this = &info
->nand_chip
;
1083 info
->clk
= clk_get(&pdev
->dev
, NULL
);
1084 if (IS_ERR(info
->clk
)) {
1085 dev_err(&pdev
->dev
, "failed to get nand clock\n");
1086 ret
= PTR_ERR(info
->clk
);
1089 clk_enable(info
->clk
);
1091 r
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
1093 dev_err(&pdev
->dev
, "no resource defined for data DMA\n");
1097 info
->drcmr_dat
= r
->start
;
1099 r
= platform_get_resource(pdev
, IORESOURCE_DMA
, 1);
1101 dev_err(&pdev
->dev
, "no resource defined for command DMA\n");
1105 info
->drcmr_cmd
= r
->start
;
1107 irq
= platform_get_irq(pdev
, 0);
1109 dev_err(&pdev
->dev
, "no IRQ resource defined\n");
1114 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1116 dev_err(&pdev
->dev
, "no IO memory resource defined\n");
1121 r
= request_mem_region(r
->start
, r
->end
- r
->start
+ 1, pdev
->name
);
1123 dev_err(&pdev
->dev
, "failed to request memory resource\n");
1128 info
->mmio_base
= ioremap(r
->start
, r
->end
- r
->start
+ 1);
1129 if (info
->mmio_base
== NULL
) {
1130 dev_err(&pdev
->dev
, "ioremap() failed\n");
1135 ret
= pxa3xx_nand_init_buff(info
);
1139 ret
= request_irq(IRQ_NAND
, pxa3xx_nand_irq
, IRQF_DISABLED
,
1142 dev_err(&pdev
->dev
, "failed to request IRQ\n");
1146 ret
= pxa3xx_nand_detect_flash(info
, pdata
);
1148 dev_err(&pdev
->dev
, "failed to detect flash\n");
1153 pxa3xx_nand_init_mtd(mtd
, info
);
1155 platform_set_drvdata(pdev
, mtd
);
1157 if (nand_scan(mtd
, 1)) {
1158 dev_err(&pdev
->dev
, "failed to scan nand\n");
1163 return add_mtd_partitions(mtd
, pdata
->parts
, pdata
->nr_parts
);
1166 free_irq(IRQ_NAND
, info
);
1169 pxa_free_dma(info
->data_dma_ch
);
1170 dma_free_coherent(&pdev
->dev
, info
->data_buff_size
,
1171 info
->data_buff
, info
->data_buff_phys
);
1173 kfree(info
->data_buff
);
1175 iounmap(info
->mmio_base
);
1177 release_mem_region(r
->start
, r
->end
- r
->start
+ 1);
1179 clk_disable(info
->clk
);
1186 static int pxa3xx_nand_remove(struct platform_device
*pdev
)
1188 struct mtd_info
*mtd
= platform_get_drvdata(pdev
);
1189 struct pxa3xx_nand_info
*info
= mtd
->priv
;
1191 platform_set_drvdata(pdev
, NULL
);
1193 del_mtd_device(mtd
);
1194 del_mtd_partitions(mtd
);
1195 free_irq(IRQ_NAND
, info
);
1197 pxa_free_dma(info
->data_dma_ch
);
1198 dma_free_writecombine(&pdev
->dev
, info
->data_buff_size
,
1199 info
->data_buff
, info
->data_buff_phys
);
1201 kfree(info
->data_buff
);
1207 static int pxa3xx_nand_suspend(struct platform_device
*pdev
, pm_message_t state
)
1209 struct mtd_info
*mtd
= (struct mtd_info
*)platform_get_drvdata(pdev
);
1210 struct pxa3xx_nand_info
*info
= mtd
->priv
;
1212 if (info
->state
!= STATE_READY
) {
1213 dev_err(&pdev
->dev
, "driver busy, state = %d\n", info
->state
);
1220 static int pxa3xx_nand_resume(struct platform_device
*pdev
)
1222 struct mtd_info
*mtd
= (struct mtd_info
*)platform_get_drvdata(pdev
);
1223 struct pxa3xx_nand_info
*info
= mtd
->priv
;
1225 clk_enable(info
->clk
);
1227 return pxa3xx_nand_config_flash(info
, info
->flash_info
);
1230 #define pxa3xx_nand_suspend NULL
1231 #define pxa3xx_nand_resume NULL
1234 static struct platform_driver pxa3xx_nand_driver
= {
1236 .name
= "pxa3xx-nand",
1238 .probe
= pxa3xx_nand_probe
,
1239 .remove
= pxa3xx_nand_remove
,
1240 .suspend
= pxa3xx_nand_suspend
,
1241 .resume
= pxa3xx_nand_resume
,
1244 static int __init
pxa3xx_nand_init(void)
1246 return platform_driver_register(&pxa3xx_nand_driver
);
1248 module_init(pxa3xx_nand_init
);
1250 static void __exit
pxa3xx_nand_exit(void)
1252 platform_driver_unregister(&pxa3xx_nand_driver
);
1254 module_exit(pxa3xx_nand_exit
);
1256 MODULE_LICENSE("GPL");
1257 MODULE_DESCRIPTION("PXA3xx NAND controller driver");