kernel/2.6.29.6-aldebaran-rt/drivers/i2c/busses/i2c-davinci.c

   1 /*
   2  * TI DAVINCI I2C adapter driver.
   3  *
   4  * Copyright (C) 2006 Texas Instruments.
   5  * Copyright (C) 2007 MontaVista Software Inc.
   6  *
   7  * Updated by Vinod & Sudhakar Feb 2005
   8  *
   9  * ----------------------------------------------------------------------------
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  * ----------------------------------------------------------------------------
  25  *
  26  */
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/i2c.h>
  31 #include <linux/clk.h>
  32 #include <linux/errno.h>
  33 #include <linux/sched.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/io.h>
  38
  39 #include <mach/hardware.h>
  40
  41 #include <mach/i2c.h>
  42
  43 /* ----- global defines ----------------------------------------------- */
  44
  45 #define DAVINCI_I2C_TIMEOUT     (1*HZ)
  46 #define I2C_DAVINCI_INTR_ALL    (DAVINCI_I2C_IMR_AAS | \
  47                                  DAVINCI_I2C_IMR_SCD | \
  48                                  DAVINCI_I2C_IMR_ARDY | \
  49                                  DAVINCI_I2C_IMR_NACK | \
  50                                  DAVINCI_I2C_IMR_AL)
  51
  52 #define DAVINCI_I2C_OAR_REG     0x00
  53 #define DAVINCI_I2C_IMR_REG     0x04
  54 #define DAVINCI_I2C_STR_REG     0x08
  55 #define DAVINCI_I2C_CLKL_REG    0x0c
  56 #define DAVINCI_I2C_CLKH_REG    0x10
  57 #define DAVINCI_I2C_CNT_REG     0x14
  58 #define DAVINCI_I2C_DRR_REG     0x18
  59 #define DAVINCI_I2C_SAR_REG     0x1c
  60 #define DAVINCI_I2C_DXR_REG     0x20
  61 #define DAVINCI_I2C_MDR_REG     0x24
  62 #define DAVINCI_I2C_IVR_REG     0x28
  63 #define DAVINCI_I2C_EMDR_REG    0x2c
  64 #define DAVINCI_I2C_PSC_REG     0x30
  65
  66 #define DAVINCI_I2C_IVR_AAS     0x07
  67 #define DAVINCI_I2C_IVR_SCD     0x06
  68 #define DAVINCI_I2C_IVR_XRDY    0x05
  69 #define DAVINCI_I2C_IVR_RDR     0x04
  70 #define DAVINCI_I2C_IVR_ARDY    0x03
  71 #define DAVINCI_I2C_IVR_NACK    0x02
  72 #define DAVINCI_I2C_IVR_AL      0x01
  73
  74 #define DAVINCI_I2C_STR_BB      (1 << 12)
  75 #define DAVINCI_I2C_STR_RSFULL  (1 << 11)
  76 #define DAVINCI_I2C_STR_SCD     (1 << 5)
  77 #define DAVINCI_I2C_STR_ARDY    (1 << 2)
  78 #define DAVINCI_I2C_STR_NACK    (1 << 1)
  79 #define DAVINCI_I2C_STR_AL      (1 << 0)
  80
  81 #define DAVINCI_I2C_MDR_NACK    (1 << 15)
  82 #define DAVINCI_I2C_MDR_STT     (1 << 13)
  83 #define DAVINCI_I2C_MDR_STP     (1 << 11)
  84 #define DAVINCI_I2C_MDR_MST     (1 << 10)
  85 #define DAVINCI_I2C_MDR_TRX     (1 << 9)
  86 #define DAVINCI_I2C_MDR_XA      (1 << 8)
  87 #define DAVINCI_I2C_MDR_RM      (1 << 7)
  88 #define DAVINCI_I2C_MDR_IRS     (1 << 5)
  89
  90 #define DAVINCI_I2C_IMR_AAS     (1 << 6)
  91 #define DAVINCI_I2C_IMR_SCD     (1 << 5)
  92 #define DAVINCI_I2C_IMR_XRDY    (1 << 4)
  93 #define DAVINCI_I2C_IMR_RRDY    (1 << 3)
  94 #define DAVINCI_I2C_IMR_ARDY    (1 << 2)
  95 #define DAVINCI_I2C_IMR_NACK    (1 << 1)
  96 #define DAVINCI_I2C_IMR_AL      (1 << 0)
  97
  98 #define MOD_REG_BIT(val, mask, set) do { \
  99         if (set) { \
 100                 val |= mask; \
 101         } else { \
 102                 val &= ~mask; \
 103         } \
 104 } while (0)
 105
 106 struct davinci_i2c_dev {
 107         struct device           *dev;
 108         void __iomem            *base;
 109         struct completion       cmd_complete;
 110         struct clk              *clk;
 111         int                     cmd_err;
 112         u8                      *buf;
 113         size_t                  buf_len;
 114         int                     irq;
 115         u8                      terminate;
 116         struct i2c_adapter      adapter;
 117 };
 118
 119 /* default platform data to use if not supplied in the platform_device */
 120 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
 121         .bus_freq       = 100,
 122         .bus_delay      = 0,
 123 };
 124
 125 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
 126                                          int reg, u16 val)
 127 {
 128         __raw_writew(val, i2c_dev->base + reg);
 129 }
 130
 131 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
 132 {
 133         return __raw_readw(i2c_dev->base + reg);
 134 }
 135
 136 /*
 137  * This functions configures I2C and brings I2C out of reset.
 138  * This function is called during I2C init function. This function
 139  * also gets called if I2C encounters any errors.
 140  */
 141 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
 142 {
 143         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
 144         u16 psc;
 145         u32 clk;
 146         u32 d;
 147         u32 clkh;
 148         u32 clkl;
 149         u32 input_clock = clk_get_rate(dev->clk);
 150         u16 w;
 151
 152         if (!pdata)
 153                 pdata = &davinci_i2c_platform_data_default;
 154
 155         /* put I2C into reset */
 156         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 157         MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 0);
 158         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 159
 160         /* NOTE: I2C Clock divider programming info
 161          * As per I2C specs the following formulas provide prescaler
 162          * and low/high divider values
 163          * input clk --> PSC Div -----------> ICCL/H Div --> output clock
 164          *                       module clk
 165          *
 166          * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
 167          *
 168          * Thus,
 169          * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
 170          *
 171          * where if PSC == 0, d = 7,
 172          *       if PSC == 1, d = 6
 173          *       if PSC > 1 , d = 5
 174          */
 175
 176         /* get minimum of 7 MHz clock, but max of 12 MHz */
 177         psc = (input_clock / 7000000) - 1;
 178         if ((input_clock / (psc + 1)) > 12000000)
 179                 psc++;  /* better to run under spec than over */
 180         d = (psc >= 2) ? 5 : 7 - psc;
 181
 182         clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
 183         clkh = clk >> 1;
 184         clkl = clk - clkh;
 185
 186         davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
 187         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
 188         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
 189
 190         dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
 191         dev_dbg(dev->dev, "PSC  = %d\n",
 192                 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
 193         dev_dbg(dev->dev, "CLKL = %d\n",
 194                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
 195         dev_dbg(dev->dev, "CLKH = %d\n",
 196                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
 197         dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
 198                 pdata->bus_freq, pdata->bus_delay);
 199
 200         /* Take the I2C module out of reset: */
 201         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 202         MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 1);
 203         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 204
 205         /* Enable interrupts */
 206         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
 207
 208         return 0;
 209 }
 210
 211 /*
 212  * Waiting for bus not busy
 213  */
 214 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
 215                                          char allow_sleep)
 216 {
 217         unsigned long timeout;
 218
 219         timeout = jiffies + DAVINCI_I2C_TIMEOUT;
 220         while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
 221                & DAVINCI_I2C_STR_BB) {
 222                 if (time_after(jiffies, timeout)) {
 223                         dev_warn(dev->dev,
 224                                  "timeout waiting for bus ready\n");
 225                         return -ETIMEDOUT;
 226                 }
 227                 if (allow_sleep)
 228                         schedule_timeout(1);
 229         }
 230
 231         return 0;
 232 }
 233
 234 /*
 235  * Low level master read/write transaction. This function is called
 236  * from i2c_davinci_xfer.
 237  */
 238 static int
 239 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
 240 {
 241         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 242         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
 243         u32 flag;
 244         u16 w;
 245         int r;
 246
 247         if (msg->len == 0)
 248                 return -EINVAL;
 249
 250         if (!pdata)
 251                 pdata = &davinci_i2c_platform_data_default;
 252         /* Introduce a delay, required for some boards (e.g Davinci EVM) */
 253         if (pdata->bus_delay)
 254                 udelay(pdata->bus_delay);
 255
 256         /* set the slave address */
 257         davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
 258
 259         dev->buf = msg->buf;
 260         dev->buf_len = msg->len;
 261
 262         davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
 263
 264         INIT_COMPLETION(dev->cmd_complete);
 265         dev->cmd_err = 0;
 266
 267         /* Take I2C out of reset, configure it as master and set the
 268          * start bit */
 269         flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST | DAVINCI_I2C_MDR_STT;
 270
 271         /* if the slave address is ten bit address, enable XA bit */
 272         if (msg->flags & I2C_M_TEN)
 273                 flag |= DAVINCI_I2C_MDR_XA;
 274         if (!(msg->flags & I2C_M_RD))
 275                 flag |= DAVINCI_I2C_MDR_TRX;
 276         if (stop)
 277                 flag |= DAVINCI_I2C_MDR_STP;
 278
 279         /* Enable receive or transmit interrupts */
 280         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
 281         if (msg->flags & I2C_M_RD)
 282                 MOD_REG_BIT(w, DAVINCI_I2C_IMR_RRDY, 1);
 283         else
 284                 MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 1);
 285         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
 286
 287         dev->terminate = 0;
 288         /* write the data into mode register */
 289         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 290
 291         r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
 292                                                       DAVINCI_I2C_TIMEOUT);
 293         if (r == 0) {
 294                 dev_err(dev->dev, "controller timed out\n");
 295                 i2c_davinci_init(dev);
 296                 dev->buf_len = 0;
 297                 return -ETIMEDOUT;
 298         }
 299         if (dev->buf_len) {
 300                 /* This should be 0 if all bytes were transferred
 301                  * or dev->cmd_err denotes an error.
 302                  * A signal may have aborted the transfer.
 303                  */
 304                 if (r >= 0) {
 305                         dev_err(dev->dev, "abnormal termination buf_len=%i\n",
 306                                 dev->buf_len);
 307                         r = -EREMOTEIO;
 308                 }
 309                 dev->terminate = 1;
 310                 wmb();
 311                 dev->buf_len = 0;
 312         }
 313         if (r < 0)
 314                 return r;
 315
 316         /* no error */
 317         if (likely(!dev->cmd_err))
 318                 return msg->len;
 319
 320         /* We have an error */
 321         if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
 322                 i2c_davinci_init(dev);
 323                 return -EIO;
 324         }
 325
 326         if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
 327                 if (msg->flags & I2C_M_IGNORE_NAK)
 328                         return msg->len;
 329                 if (stop) {
 330                         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 331                         MOD_REG_BIT(w, DAVINCI_I2C_MDR_STP, 1);
 332                         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 333                 }
 334                 return -EREMOTEIO;
 335         }
 336         return -EIO;
 337 }
 338
 339 /*
 340  * Prepare controller for a transaction and call i2c_davinci_xfer_msg
 341  */
 342 static int
 343 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 344 {
 345         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 346         int i;
 347         int ret;
 348
 349         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 350
 351         ret = i2c_davinci_wait_bus_not_busy(dev, 1);
 352         if (ret < 0) {
 353                 dev_warn(dev->dev, "timeout waiting for bus ready\n");
 354                 return ret;
 355         }
 356
 357         for (i = 0; i < num; i++) {
 358                 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 359                 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
 360                         ret);
 361                 if (ret < 0)
 362                         return ret;
 363         }
 364         return num;
 365 }
 366
 367 static u32 i2c_davinci_func(struct i2c_adapter *adap)
 368 {
 369         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 370 }
 371
 372 static void terminate_read(struct davinci_i2c_dev *dev)
 373 {
 374         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 375         w |= DAVINCI_I2C_MDR_NACK;
 376         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 377
 378         /* Throw away data */
 379         davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
 380         if (!dev->terminate)
 381                 dev_err(dev->dev, "RDR IRQ while no data requested\n");
 382 }
 383 static void terminate_write(struct davinci_i2c_dev *dev)
 384 {
 385         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 386         w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
 387         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 388
 389         if (!dev->terminate)
 390                 dev_err(dev->dev, "TDR IRQ while no data to send\n");
 391 }
 392
 393 /*
 394  * Interrupt service routine. This gets called whenever an I2C interrupt
 395  * occurs.
 396  */
 397 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
 398 {
 399         struct davinci_i2c_dev *dev = dev_id;
 400         u32 stat;
 401         int count = 0;
 402         u16 w;
 403
 404         while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
 405                 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
 406                 if (count++ == 100) {
 407                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 408                         break;
 409                 }
 410
 411                 switch (stat) {
 412                 case DAVINCI_I2C_IVR_AL:
 413                         /* Arbitration lost, must retry */
 414                         dev->cmd_err |= DAVINCI_I2C_STR_AL;
 415                         dev->buf_len = 0;
 416                         complete(&dev->cmd_complete);
 417                         break;
 418
 419                 case DAVINCI_I2C_IVR_NACK:
 420                         dev->cmd_err |= DAVINCI_I2C_STR_NACK;
 421                         dev->buf_len = 0;
 422                         complete(&dev->cmd_complete);
 423                         break;
 424
 425                 case DAVINCI_I2C_IVR_ARDY:
 426                         davinci_i2c_write_reg(dev,
 427                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
 428                         complete(&dev->cmd_complete);
 429                         break;
 430
 431                 case DAVINCI_I2C_IVR_RDR:
 432                         if (dev->buf_len) {
 433                                 *dev->buf++ =
 434                                     davinci_i2c_read_reg(dev,
 435                                                          DAVINCI_I2C_DRR_REG);
 436                                 dev->buf_len--;
 437                                 if (dev->buf_len)
 438                                         continue;
 439
 440                                 davinci_i2c_write_reg(dev,
 441                                         DAVINCI_I2C_STR_REG,
 442                                         DAVINCI_I2C_IMR_RRDY);
 443                         } else {
 444                                 /* signal can terminate transfer */
 445                                 terminate_read(dev);
 446                         }
 447                         break;
 448
 449                 case DAVINCI_I2C_IVR_XRDY:
 450                         if (dev->buf_len) {
 451                                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
 452                                                       *dev->buf++);
 453                                 dev->buf_len--;
 454                                 if (dev->buf_len)
 455                                         continue;
 456
 457                                 w = davinci_i2c_read_reg(dev,
 458                                                          DAVINCI_I2C_IMR_REG);
 459                                 MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 0);
 460                                 davinci_i2c_write_reg(dev,
 461                                                       DAVINCI_I2C_IMR_REG,
 462                                                       w);
 463                         } else {
 464                                 /* signal can terminate transfer */
 465                                 terminate_write(dev);
 466                         }
 467                         break;
 468
 469                 case DAVINCI_I2C_IVR_SCD:
 470                         davinci_i2c_write_reg(dev,
 471                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
 472                         complete(&dev->cmd_complete);
 473                         break;
 474
 475                 case DAVINCI_I2C_IVR_AAS:
 476                         dev_warn(dev->dev, "Address as slave interrupt\n");
 477                 }/* switch */
 478         }/* while */
 479
 480         return count ? IRQ_HANDLED : IRQ_NONE;
 481 }
 482
 483 static struct i2c_algorithm i2c_davinci_algo = {
 484         .master_xfer    = i2c_davinci_xfer,
 485         .functionality  = i2c_davinci_func,
 486 };
 487
 488 static int davinci_i2c_probe(struct platform_device *pdev)
 489 {
 490         struct davinci_i2c_dev *dev;
 491         struct i2c_adapter *adap;
 492         struct resource *mem, *irq, *ioarea;
 493         int r;
 494
 495         /* NOTE: driver uses the static register mapping */
 496         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 497         if (!mem) {
 498                 dev_err(&pdev->dev, "no mem resource?\n");
 499                 return -ENODEV;
 500         }
 501
 502         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 503         if (!irq) {
 504                 dev_err(&pdev->dev, "no irq resource?\n");
 505                 return -ENODEV;
 506         }
 507
 508         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 509                                     pdev->name);
 510         if (!ioarea) {
 511                 dev_err(&pdev->dev, "I2C region already claimed\n");
 512                 return -EBUSY;
 513         }
 514
 515         dev = kzalloc(sizeof(struct davinci_i2c_dev), GFP_KERNEL);
 516         if (!dev) {
 517                 r = -ENOMEM;
 518                 goto err_release_region;
 519         }
 520
 521         init_completion(&dev->cmd_complete);
 522         dev->dev = get_device(&pdev->dev);
 523         dev->irq = irq->start;
 524         platform_set_drvdata(pdev, dev);
 525
 526         dev->clk = clk_get(&pdev->dev, "I2CCLK");
 527         if (IS_ERR(dev->clk)) {
 528                 r = -ENODEV;
 529                 goto err_free_mem;
 530         }
 531         clk_enable(dev->clk);
 532
 533         dev->base = (void __iomem *)IO_ADDRESS(mem->start);
 534         i2c_davinci_init(dev);
 535
 536         r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev);
 537         if (r) {
 538                 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
 539                 goto err_unuse_clocks;
 540         }
 541
 542         adap = &dev->adapter;
 543         i2c_set_adapdata(adap, dev);
 544         adap->owner = THIS_MODULE;
 545         adap->class = I2C_CLASS_HWMON;
 546         strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
 547         adap->algo = &i2c_davinci_algo;
 548         adap->dev.parent = &pdev->dev;
 549
 550         /* FIXME */
 551         adap->timeout = 1;
 552
 553         adap->nr = pdev->id;
 554         r = i2c_add_numbered_adapter(adap);
 555         if (r) {
 556                 dev_err(&pdev->dev, "failure adding adapter\n");
 557                 goto err_free_irq;
 558         }
 559
 560         return 0;
 561
 562 err_free_irq:
 563         free_irq(dev->irq, dev);
 564 err_unuse_clocks:
 565         clk_disable(dev->clk);
 566         clk_put(dev->clk);
 567         dev->clk = NULL;
 568 err_free_mem:
 569         platform_set_drvdata(pdev, NULL);
 570         put_device(&pdev->dev);
 571         kfree(dev);
 572 err_release_region:
 573         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 574
 575         return r;
 576 }
 577
 578 static int davinci_i2c_remove(struct platform_device *pdev)
 579 {
 580         struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
 581         struct resource *mem;
 582
 583         platform_set_drvdata(pdev, NULL);
 584         i2c_del_adapter(&dev->adapter);
 585         put_device(&pdev->dev);
 586
 587         clk_disable(dev->clk);
 588         clk_put(dev->clk);
 589         dev->clk = NULL;
 590
 591         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
 592         free_irq(IRQ_I2C, dev);
 593         kfree(dev);
 594
 595         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 596         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 597         return 0;
 598 }
 599
 600 /* work with hotplug and coldplug */
 601 MODULE_ALIAS("platform:i2c_davinci");
 602
 603 static struct platform_driver davinci_i2c_driver = {
 604         .probe          = davinci_i2c_probe,
 605         .remove         = davinci_i2c_remove,
 606         .driver         = {
 607                 .name   = "i2c_davinci",
 608                 .owner  = THIS_MODULE,
 609         },
 610 };
 611
 612 /* I2C may be needed to bring up other drivers */
 613 static int __init davinci_i2c_init_driver(void)
 614 {
 615         return platform_driver_register(&davinci_i2c_driver);
 616 }
 617 subsys_initcall(davinci_i2c_init_driver);
 618
 619 static void __exit davinci_i2c_exit_driver(void)
 620 {
 621         platform_driver_unregister(&davinci_i2c_driver);
 622 }
 623 module_exit(davinci_i2c_exit_driver);
 624
 625 MODULE_AUTHOR("Texas Instruments India");
 626 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
 627 MODULE_LICENSE("GPL");