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added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / drivers / gpu / drm / i915 / intel_sdvo.c
blobfbe6f3931b1b116cb022daa2238ee78d2e7c359c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28 #include <linux/i2c.h>
29 #include <linux/delay.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "intel_sdvo_regs.h"
37
38 #undef SDVO_DEBUG
39
40 struct intel_sdvo_priv {
41 struct intel_i2c_chan *i2c_bus;
42 int slaveaddr;
43
44 /* Register for the SDVO device: SDVOB or SDVOC */
45 int output_device;
46
47 /* Active outputs controlled by this SDVO output */
48 uint16_t controlled_output;
49
50 /*
51 * Capabilities of the SDVO device returned by
52 * i830_sdvo_get_capabilities()
53 */
54 struct intel_sdvo_caps caps;
55
56 /* Pixel clock limitations reported by the SDVO device, in kHz */
57 int pixel_clock_min, pixel_clock_max;
58
59 /**
60 * This is set if we're going to treat the device as TV-out.
61 *
62 * While we have these nice friendly flags for output types that ought
63 * to decide this for us, the S-Video output on our HDMI+S-Video card
64 * shows up as RGB1 (VGA).
65 */
66 bool is_tv;
67
68 /**
69 * This is set if we treat the device as HDMI, instead of DVI.
70 */
71 bool is_hdmi;
72
73 /**
74 * Returned SDTV resolutions allowed for the current format, if the
75 * device reported it.
76 */
77 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
78
79 /**
80 * Current selected TV format.
81 *
82 * This is stored in the same structure that's passed to the device, for
83 * convenience.
84 */
85 struct intel_sdvo_tv_format tv_format;
86
87 /*
88 * supported encoding mode, used to determine whether HDMI is
89 * supported
90 */
91 struct intel_sdvo_encode encode;
92
93 /* DDC bus used by this SDVO output */
94 uint8_t ddc_bus;
95
96 int save_sdvo_mult;
97 u16 save_active_outputs;
98 struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
99 struct intel_sdvo_dtd save_output_dtd[16];
100 u32 save_SDVOX;
101 };
102
103 /**
104 * Writes the SDVOB or SDVOC with the given value, but always writes both
105 * SDVOB and SDVOC to work around apparent hardware issues (according to
106 * comments in the BIOS).
107 */
108 static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
109 {
110 struct drm_device *dev = intel_output->base.dev;
111 struct drm_i915_private *dev_priv = dev->dev_private;
112 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
113 u32 bval = val, cval = val;
114 int i;
115
116 if (sdvo_priv->output_device == SDVOB) {
117 cval = I915_READ(SDVOC);
118 } else {
119 bval = I915_READ(SDVOB);
120 }
121 /*
122 * Write the registers twice for luck. Sometimes,
123 * writing them only once doesn't appear to 'stick'.
124 * The BIOS does this too. Yay, magic
125 */
126 for (i = 0; i < 2; i++)
127 {
128 I915_WRITE(SDVOB, bval);
129 I915_READ(SDVOB);
130 I915_WRITE(SDVOC, cval);
131 I915_READ(SDVOC);
132 }
133 }
134
135 static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
136 u8 *ch)
137 {
138 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
139 u8 out_buf[2];
140 u8 buf[2];
141 int ret;
142
143 struct i2c_msg msgs[] = {
144 {
145 .addr = sdvo_priv->i2c_bus->slave_addr,
146 .flags = 0,
147 .len = 1,
148 .buf = out_buf,
149 },
150 {
151 .addr = sdvo_priv->i2c_bus->slave_addr,
152 .flags = I2C_M_RD,
153 .len = 1,
154 .buf = buf,
155 }
156 };
157
158 out_buf[0] = addr;
159 out_buf[1] = 0;
160
161 if ((ret = i2c_transfer(&sdvo_priv->i2c_bus->adapter, msgs, 2)) == 2)
162 {
163 *ch = buf[0];
164 return true;
165 }
166
167 DRM_DEBUG("i2c transfer returned %d\n", ret);
168 return false;
169 }
170
171 static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
172 u8 ch)
173 {
174 u8 out_buf[2];
175 struct i2c_msg msgs[] = {
176 {
177 .addr = intel_output->i2c_bus->slave_addr,
178 .flags = 0,
179 .len = 2,
180 .buf = out_buf,
181 }
182 };
183
184 out_buf[0] = addr;
185 out_buf[1] = ch;
186
187 if (i2c_transfer(&intel_output->i2c_bus->adapter, msgs, 1) == 1)
188 {
189 return true;
190 }
191 return false;
192 }
193
194 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
195 /** Mapping of command numbers to names, for debug output */
196 static const struct _sdvo_cmd_name {
197 u8 cmd;
198 char *name;
199 } sdvo_cmd_names[] = {
200 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
201 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
202 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
203 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
204 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
205 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
206 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
207 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
208 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
209 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
210 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
211 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
212 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
213 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
214 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
215 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
216 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
217 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
218 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
219 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
220 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
221 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
222 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
223 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
224 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
225 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
226 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
227 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
228 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
229 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
230 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
231 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
232 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
233 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
234 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
235 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
236 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
237 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
238 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
239 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
240 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
241 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
242 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
243 /* HDMI op code */
244 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
245 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
246 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
247 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
248 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
249 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
250 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
251 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
252 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
253 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
254 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
255 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
256 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
257 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
258 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
259 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
260 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
261 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
262 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
263 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
264 };
265
266 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
267 #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
268
269 #ifdef SDVO_DEBUG
270 static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
271 void *args, int args_len)
272 {
273 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
274 int i;
275
276 DRM_DEBUG("%s: W: %02X ", SDVO_NAME(sdvo_priv), cmd);
277 for (i = 0; i < args_len; i++)
278 printk("%02X ", ((u8 *)args)[i]);
279 for (; i < 8; i++)
280 printk(" ");
281 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
282 if (cmd == sdvo_cmd_names[i].cmd) {
283 printk("(%s)", sdvo_cmd_names[i].name);
284 break;
285 }
286 }
287 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
288 printk("(%02X)",cmd);
289 printk("\n");
290 }
291 #else
292 #define intel_sdvo_debug_write(o, c, a, l)
293 #endif
294
295 static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
296 void *args, int args_len)
297 {
298 int i;
299
300 intel_sdvo_debug_write(intel_output, cmd, args, args_len);
301
302 for (i = 0; i < args_len; i++) {
303 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
304 ((u8*)args)[i]);
305 }
306
307 intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
308 }
309
310 #ifdef SDVO_DEBUG
311 static const char *cmd_status_names[] = {
312 "Power on",
313 "Success",
314 "Not supported",
315 "Invalid arg",
316 "Pending",
317 "Target not specified",
318 "Scaling not supported"
319 };
320
321 static void intel_sdvo_debug_response(struct intel_output *intel_output,
322 void *response, int response_len,
323 u8 status)
324 {
325 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
326
327 DRM_DEBUG("%s: R: ", SDVO_NAME(sdvo_priv));
328 for (i = 0; i < response_len; i++)
329 printk("%02X ", ((u8 *)response)[i]);
330 for (; i < 8; i++)
331 printk(" ");
332 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
333 printk("(%s)", cmd_status_names[status]);
334 else
335 printk("(??? %d)", status);
336 printk("\n");
337 }
338 #else
339 #define intel_sdvo_debug_response(o, r, l, s)
340 #endif
341
342 static u8 intel_sdvo_read_response(struct intel_output *intel_output,
343 void *response, int response_len)
344 {
345 int i;
346 u8 status;
347 u8 retry = 50;
348
349 while (retry--) {
350 /* Read the command response */
351 for (i = 0; i < response_len; i++) {
352 intel_sdvo_read_byte(intel_output,
353 SDVO_I2C_RETURN_0 + i,
354 &((u8 *)response)[i]);
355 }
356
357 /* read the return status */
358 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
359 &status);
360
361 intel_sdvo_debug_response(intel_output, response, response_len,
362 status);
363 if (status != SDVO_CMD_STATUS_PENDING)
364 return status;
365
366 mdelay(50);
367 }
368
369 return status;
370 }
371
372 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
373 {
374 if (mode->clock >= 100000)
375 return 1;
376 else if (mode->clock >= 50000)
377 return 2;
378 else
379 return 4;
380 }
381
382 /**
383 * Don't check status code from this as it switches the bus back to the
384 * SDVO chips which defeats the purpose of doing a bus switch in the first
385 * place.
386 */
387 static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
388 u8 target)
389 {
390 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
391 }
392
393 static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
394 {
395 struct intel_sdvo_set_target_input_args targets = {0};
396 u8 status;
397
398 if (target_0 && target_1)
399 return SDVO_CMD_STATUS_NOTSUPP;
400
401 if (target_1)
402 targets.target_1 = 1;
403
404 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
405 sizeof(targets));
406
407 status = intel_sdvo_read_response(intel_output, NULL, 0);
408
409 return (status == SDVO_CMD_STATUS_SUCCESS);
410 }
411
412 /**
413 * Return whether each input is trained.
414 *
415 * This function is making an assumption about the layout of the response,
416 * which should be checked against the docs.
417 */
418 static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
419 {
420 struct intel_sdvo_get_trained_inputs_response response;
421 u8 status;
422
423 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
424 status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
425 if (status != SDVO_CMD_STATUS_SUCCESS)
426 return false;
427
428 *input_1 = response.input0_trained;
429 *input_2 = response.input1_trained;
430 return true;
431 }
432
433 static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
434 u16 *outputs)
435 {
436 u8 status;
437
438 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
439 status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
440
441 return (status == SDVO_CMD_STATUS_SUCCESS);
442 }
443
444 static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
445 u16 outputs)
446 {
447 u8 status;
448
449 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
450 sizeof(outputs));
451 status = intel_sdvo_read_response(intel_output, NULL, 0);
452 return (status == SDVO_CMD_STATUS_SUCCESS);
453 }
454
455 static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
456 int mode)
457 {
458 u8 status, state = SDVO_ENCODER_STATE_ON;
459
460 switch (mode) {
461 case DRM_MODE_DPMS_ON:
462 state = SDVO_ENCODER_STATE_ON;
463 break;
464 case DRM_MODE_DPMS_STANDBY:
465 state = SDVO_ENCODER_STATE_STANDBY;
466 break;
467 case DRM_MODE_DPMS_SUSPEND:
468 state = SDVO_ENCODER_STATE_SUSPEND;
469 break;
470 case DRM_MODE_DPMS_OFF:
471 state = SDVO_ENCODER_STATE_OFF;
472 break;
473 }
474
475 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
476 sizeof(state));
477 status = intel_sdvo_read_response(intel_output, NULL, 0);
478
479 return (status == SDVO_CMD_STATUS_SUCCESS);
480 }
481
482 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
483 int *clock_min,
484 int *clock_max)
485 {
486 struct intel_sdvo_pixel_clock_range clocks;
487 u8 status;
488
489 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
490 NULL, 0);
491
492 status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
493
494 if (status != SDVO_CMD_STATUS_SUCCESS)
495 return false;
496
497 /* Convert the values from units of 10 kHz to kHz. */
498 *clock_min = clocks.min * 10;
499 *clock_max = clocks.max * 10;
500
501 return true;
502 }
503
504 static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
505 u16 outputs)
506 {
507 u8 status;
508
509 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
510 sizeof(outputs));
511
512 status = intel_sdvo_read_response(intel_output, NULL, 0);
513 return (status == SDVO_CMD_STATUS_SUCCESS);
514 }
515
516 static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
517 struct intel_sdvo_dtd *dtd)
518 {
519 u8 status;
520
521 intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
522 status = intel_sdvo_read_response(intel_output, &dtd->part1,
523 sizeof(dtd->part1));
524 if (status != SDVO_CMD_STATUS_SUCCESS)
525 return false;
526
527 intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
528 status = intel_sdvo_read_response(intel_output, &dtd->part2,
529 sizeof(dtd->part2));
530 if (status != SDVO_CMD_STATUS_SUCCESS)
531 return false;
532
533 return true;
534 }
535
536 static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
537 struct intel_sdvo_dtd *dtd)
538 {
539 return intel_sdvo_get_timing(intel_output,
540 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
541 }
542
543 static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
544 struct intel_sdvo_dtd *dtd)
545 {
546 return intel_sdvo_get_timing(intel_output,
547 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
548 }
549
550 static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
551 struct intel_sdvo_dtd *dtd)
552 {
553 u8 status;
554
555 intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
556 status = intel_sdvo_read_response(intel_output, NULL, 0);
557 if (status != SDVO_CMD_STATUS_SUCCESS)
558 return false;
559
560 intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
561 status = intel_sdvo_read_response(intel_output, NULL, 0);
562 if (status != SDVO_CMD_STATUS_SUCCESS)
563 return false;
564
565 return true;
566 }
567
568 static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
569 struct intel_sdvo_dtd *dtd)
570 {
571 return intel_sdvo_set_timing(intel_output,
572 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
573 }
574
575 static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
576 struct intel_sdvo_dtd *dtd)
577 {
578 return intel_sdvo_set_timing(intel_output,
579 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
580 }
581
582 static bool
583 intel_sdvo_create_preferred_input_timing(struct intel_output *output,
584 uint16_t clock,
585 uint16_t width,
586 uint16_t height)
587 {
588 struct intel_sdvo_preferred_input_timing_args args;
589 uint8_t status;
590
591 args.clock = clock;
592 args.width = width;
593 args.height = height;
594 intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
595 &args, sizeof(args));
596 status = intel_sdvo_read_response(output, NULL, 0);
597 if (status != SDVO_CMD_STATUS_SUCCESS)
598 return false;
599
600 return true;
601 }
602
603 static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
604 struct intel_sdvo_dtd *dtd)
605 {
606 bool status;
607
608 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
609 NULL, 0);
610
611 status = intel_sdvo_read_response(output, &dtd->part1,
612 sizeof(dtd->part1));
613 if (status != SDVO_CMD_STATUS_SUCCESS)
614 return false;
615
616 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
617 NULL, 0);
618
619 status = intel_sdvo_read_response(output, &dtd->part2,
620 sizeof(dtd->part2));
621 if (status != SDVO_CMD_STATUS_SUCCESS)
622 return false;
623
624 return false;
625 }
626
627 static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
628 {
629 u8 response, status;
630
631 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
632 status = intel_sdvo_read_response(intel_output, &response, 1);
633
634 if (status != SDVO_CMD_STATUS_SUCCESS) {
635 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
636 return SDVO_CLOCK_RATE_MULT_1X;
637 } else {
638 DRM_DEBUG("Current clock rate multiplier: %d\n", response);
639 }
640
641 return response;
642 }
643
644 static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
645 {
646 u8 status;
647
648 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
649 status = intel_sdvo_read_response(intel_output, NULL, 0);
650 if (status != SDVO_CMD_STATUS_SUCCESS)
651 return false;
652
653 return true;
654 }
655
656 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
657 struct drm_display_mode *mode)
658 {
659 uint16_t width, height;
660 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
661 uint16_t h_sync_offset, v_sync_offset;
662
663 width = mode->crtc_hdisplay;
664 height = mode->crtc_vdisplay;
665
666 /* do some mode translations */
667 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
668 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
669
670 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
671 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
672
673 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
674 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
675
676 dtd->part1.clock = mode->clock / 10;
677 dtd->part1.h_active = width & 0xff;
678 dtd->part1.h_blank = h_blank_len & 0xff;
679 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
680 ((h_blank_len >> 8) & 0xf);
681 dtd->part1.v_active = height & 0xff;
682 dtd->part1.v_blank = v_blank_len & 0xff;
683 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
684 ((v_blank_len >> 8) & 0xf);
685
686 dtd->part2.h_sync_off = h_sync_offset;
687 dtd->part2.h_sync_width = h_sync_len & 0xff;
688 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
689 (v_sync_len & 0xf);
690 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
691 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
692 ((v_sync_len & 0x30) >> 4);
693
694 dtd->part2.dtd_flags = 0x18;
695 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
696 dtd->part2.dtd_flags |= 0x2;
697 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
698 dtd->part2.dtd_flags |= 0x4;
699
700 dtd->part2.sdvo_flags = 0;
701 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
702 dtd->part2.reserved = 0;
703 }
704
705 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
706 struct intel_sdvo_dtd *dtd)
707 {
708 uint16_t width, height;
709 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
710 uint16_t h_sync_offset, v_sync_offset;
711
712 width = mode->crtc_hdisplay;
713 height = mode->crtc_vdisplay;
714
715 /* do some mode translations */
716 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
717 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
718
719 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
720 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
721
722 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
723 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
724
725 mode->hdisplay = dtd->part1.h_active;
726 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
727 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
728 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xa0) << 2;
729 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
730 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
731 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
732 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
733
734 mode->vdisplay = dtd->part1.v_active;
735 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
736 mode->vsync_start = mode->vdisplay;
737 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
738 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0a) << 2;
739 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
740 mode->vsync_end = mode->vsync_start +
741 (dtd->part2.v_sync_off_width & 0xf);
742 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
743 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
744 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
745
746 mode->clock = dtd->part1.clock * 10;
747
748 mode->flags &= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
749 if (dtd->part2.dtd_flags & 0x2)
750 mode->flags |= DRM_MODE_FLAG_PHSYNC;
751 if (dtd->part2.dtd_flags & 0x4)
752 mode->flags |= DRM_MODE_FLAG_PVSYNC;
753 }
754
755 static bool intel_sdvo_get_supp_encode(struct intel_output *output,
756 struct intel_sdvo_encode *encode)
757 {
758 uint8_t status;
759
760 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
761 status = intel_sdvo_read_response(output, encode, sizeof(*encode));
762 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
763 memset(encode, 0, sizeof(*encode));
764 return false;
765 }
766
767 return true;
768 }
769
770 static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
771 {
772 uint8_t status;
773
774 intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
775 status = intel_sdvo_read_response(output, NULL, 0);
776
777 return (status == SDVO_CMD_STATUS_SUCCESS);
778 }
779
780 static bool intel_sdvo_set_colorimetry(struct intel_output *output,
781 uint8_t mode)
782 {
783 uint8_t status;
784
785 intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
786 status = intel_sdvo_read_response(output, NULL, 0);
787
788 return (status == SDVO_CMD_STATUS_SUCCESS);
789 }
790
791 #if 0
792 static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
793 {
794 int i, j;
795 uint8_t set_buf_index[2];
796 uint8_t av_split;
797 uint8_t buf_size;
798 uint8_t buf[48];
799 uint8_t *pos;
800
801 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
802 intel_sdvo_read_response(output, &av_split, 1);
803
804 for (i = 0; i <= av_split; i++) {
805 set_buf_index[0] = i; set_buf_index[1] = 0;
806 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
807 set_buf_index, 2);
808 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
809 intel_sdvo_read_response(output, &buf_size, 1);
810
811 pos = buf;
812 for (j = 0; j <= buf_size; j += 8) {
813 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
814 NULL, 0);
815 intel_sdvo_read_response(output, pos, 8);
816 pos += 8;
817 }
818 }
819 }
820 #endif
821
822 static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
823 uint8_t *data, int8_t size, uint8_t tx_rate)
824 {
825 uint8_t set_buf_index[2];
826
827 set_buf_index[0] = index;
828 set_buf_index[1] = 0;
829
830 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
831
832 for (; size > 0; size -= 8) {
833 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
834 data += 8;
835 }
836
837 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
838 }
839
840 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
841 {
842 uint8_t csum = 0;
843 int i;
844
845 for (i = 0; i < size; i++)
846 csum += data[i];
847
848 return 0x100 - csum;
849 }
850
851 #define DIP_TYPE_AVI 0x82
852 #define DIP_VERSION_AVI 0x2
853 #define DIP_LEN_AVI 13
854
855 struct dip_infoframe {
856 uint8_t type;
857 uint8_t version;
858 uint8_t len;
859 uint8_t checksum;
860 union {
861 struct {
862 /* Packet Byte #1 */
863 uint8_t S:2;
864 uint8_t B:2;
865 uint8_t A:1;
866 uint8_t Y:2;
867 uint8_t rsvd1:1;
868 /* Packet Byte #2 */
869 uint8_t R:4;
870 uint8_t M:2;
871 uint8_t C:2;
872 /* Packet Byte #3 */
873 uint8_t SC:2;
874 uint8_t Q:2;
875 uint8_t EC:3;
876 uint8_t ITC:1;
877 /* Packet Byte #4 */
878 uint8_t VIC:7;
879 uint8_t rsvd2:1;
880 /* Packet Byte #5 */
881 uint8_t PR:4;
882 uint8_t rsvd3:4;
883 /* Packet Byte #6~13 */
884 uint16_t top_bar_end;
885 uint16_t bottom_bar_start;
886 uint16_t left_bar_end;
887 uint16_t right_bar_start;
888 } avi;
889 struct {
890 /* Packet Byte #1 */
891 uint8_t channel_count:3;
892 uint8_t rsvd1:1;
893 uint8_t coding_type:4;
894 /* Packet Byte #2 */
895 uint8_t sample_size:2; /* SS0, SS1 */
896 uint8_t sample_frequency:3;
897 uint8_t rsvd2:3;
898 /* Packet Byte #3 */
899 uint8_t coding_type_private:5;
900 uint8_t rsvd3:3;
901 /* Packet Byte #4 */
902 uint8_t channel_allocation;
903 /* Packet Byte #5 */
904 uint8_t rsvd4:3;
905 uint8_t level_shift:4;
906 uint8_t downmix_inhibit:1;
907 } audio;
908 uint8_t payload[28];
909 } __attribute__ ((packed)) u;
910 } __attribute__((packed));
911
912 static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
913 struct drm_display_mode * mode)
914 {
915 struct dip_infoframe avi_if = {
916 .type = DIP_TYPE_AVI,
917 .version = DIP_VERSION_AVI,
918 .len = DIP_LEN_AVI,
919 };
920
921 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
922 4 + avi_if.len);
923 intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
924 SDVO_HBUF_TX_VSYNC);
925 }
926
927 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
928 struct drm_display_mode *mode,
929 struct drm_display_mode *adjusted_mode)
930 {
931 struct intel_output *output = enc_to_intel_output(encoder);
932 struct intel_sdvo_priv *dev_priv = output->dev_priv;
933
934 if (!dev_priv->is_tv) {
935 /* Make the CRTC code factor in the SDVO pixel multiplier. The
936 * SDVO device will be told of the multiplier during mode_set.
937 */
938 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
939 } else {
940 struct intel_sdvo_dtd output_dtd;
941 bool success;
942
943 /* We need to construct preferred input timings based on our
944 * output timings. To do that, we have to set the output
945 * timings, even though this isn't really the right place in
946 * the sequence to do it. Oh well.
947 */
948
949
950 /* Set output timings */
951 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
952 intel_sdvo_set_target_output(output,
953 dev_priv->controlled_output);
954 intel_sdvo_set_output_timing(output, &output_dtd);
955
956 /* Set the input timing to the screen. Assume always input 0. */
957 intel_sdvo_set_target_input(output, true, false);
958
959
960 success = intel_sdvo_create_preferred_input_timing(output,
961 mode->clock / 10,
962 mode->hdisplay,
963 mode->vdisplay);
964 if (success) {
965 struct intel_sdvo_dtd input_dtd;
966
967 intel_sdvo_get_preferred_input_timing(output,
968 &input_dtd);
969 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
970
971 } else {
972 return false;
973 }
974 }
975 return true;
976 }
977
978 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
979 struct drm_display_mode *mode,
980 struct drm_display_mode *adjusted_mode)
981 {
982 struct drm_device *dev = encoder->dev;
983 struct drm_i915_private *dev_priv = dev->dev_private;
984 struct drm_crtc *crtc = encoder->crtc;
985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
986 struct intel_output *output = enc_to_intel_output(encoder);
987 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
988 u32 sdvox = 0;
989 int sdvo_pixel_multiply;
990 struct intel_sdvo_in_out_map in_out;
991 struct intel_sdvo_dtd input_dtd;
992 u8 status;
993
994 if (!mode)
995 return;
996
997 /* First, set the input mapping for the first input to our controlled
998 * output. This is only correct if we're a single-input device, in
999 * which case the first input is the output from the appropriate SDVO
1000 * channel on the motherboard. In a two-input device, the first input
1001 * will be SDVOB and the second SDVOC.
1002 */
1003 in_out.in0 = sdvo_priv->controlled_output;
1004 in_out.in1 = 0;
1005
1006 intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
1007 &in_out, sizeof(in_out));
1008 status = intel_sdvo_read_response(output, NULL, 0);
1009
1010 if (sdvo_priv->is_hdmi) {
1011 intel_sdvo_set_avi_infoframe(output, mode);
1012 sdvox |= SDVO_AUDIO_ENABLE;
1013 }
1014
1015 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1016
1017 /* If it's a TV, we already set the output timing in mode_fixup.
1018 * Otherwise, the output timing is equal to the input timing.
1019 */
1020 if (!sdvo_priv->is_tv) {
1021 /* Set the output timing to the screen */
1022 intel_sdvo_set_target_output(output,
1023 sdvo_priv->controlled_output);
1024 intel_sdvo_set_output_timing(output, &input_dtd);
1025 }
1026
1027 /* Set the input timing to the screen. Assume always input 0. */
1028 intel_sdvo_set_target_input(output, true, false);
1029
1030 /* We would like to use intel_sdvo_create_preferred_input_timing() to
1031 * provide the device with a timing it can support, if it supports that
1032 * feature. However, presumably we would need to adjust the CRTC to
1033 * output the preferred timing, and we don't support that currently.
1034 */
1035 #if 0
1036 success = intel_sdvo_create_preferred_input_timing(output, clock,
1037 width, height);
1038 if (success) {
1039 struct intel_sdvo_dtd *input_dtd;
1040
1041 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
1042 intel_sdvo_set_input_timing(output, &input_dtd);
1043 }
1044 #else
1045 intel_sdvo_set_input_timing(output, &input_dtd);
1046 #endif
1047
1048 switch (intel_sdvo_get_pixel_multiplier(mode)) {
1049 case 1:
1050 intel_sdvo_set_clock_rate_mult(output,
1051 SDVO_CLOCK_RATE_MULT_1X);
1052 break;
1053 case 2:
1054 intel_sdvo_set_clock_rate_mult(output,
1055 SDVO_CLOCK_RATE_MULT_2X);
1056 break;
1057 case 4:
1058 intel_sdvo_set_clock_rate_mult(output,
1059 SDVO_CLOCK_RATE_MULT_4X);
1060 break;
1061 }
1062
1063 /* Set the SDVO control regs. */
1064 if (IS_I965G(dev)) {
1065 sdvox |= SDVO_BORDER_ENABLE |
1066 SDVO_VSYNC_ACTIVE_HIGH |
1067 SDVO_HSYNC_ACTIVE_HIGH;
1068 } else {
1069 sdvox |= I915_READ(sdvo_priv->output_device);
1070 switch (sdvo_priv->output_device) {
1071 case SDVOB:
1072 sdvox &= SDVOB_PRESERVE_MASK;
1073 break;
1074 case SDVOC:
1075 sdvox &= SDVOC_PRESERVE_MASK;
1076 break;
1077 }
1078 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1079 }
1080 if (intel_crtc->pipe == 1)
1081 sdvox |= SDVO_PIPE_B_SELECT;
1082
1083 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1084 if (IS_I965G(dev)) {
1085 /* done in crtc_mode_set as the dpll_md reg must be written early */
1086 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1087 /* done in crtc_mode_set as it lives inside the dpll register */
1088 } else {
1089 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1090 }
1091
1092 intel_sdvo_write_sdvox(output, sdvox);
1093 }
1094
1095 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1096 {
1097 struct drm_device *dev = encoder->dev;
1098 struct drm_i915_private *dev_priv = dev->dev_private;
1099 struct intel_output *intel_output = enc_to_intel_output(encoder);
1100 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1101 u32 temp;
1102
1103 if (mode != DRM_MODE_DPMS_ON) {
1104 intel_sdvo_set_active_outputs(intel_output, 0);
1105 if (0)
1106 intel_sdvo_set_encoder_power_state(intel_output, mode);
1107
1108 if (mode == DRM_MODE_DPMS_OFF) {
1109 temp = I915_READ(sdvo_priv->output_device);
1110 if ((temp & SDVO_ENABLE) != 0) {
1111 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
1112 }
1113 }
1114 } else {
1115 bool input1, input2;
1116 int i;
1117 u8 status;
1118
1119 temp = I915_READ(sdvo_priv->output_device);
1120 if ((temp & SDVO_ENABLE) == 0)
1121 intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
1122 for (i = 0; i < 2; i++)
1123 intel_wait_for_vblank(dev);
1124
1125 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
1126 &input2);
1127
1128
1129 /* Warn if the device reported failure to sync.
1130 * A lot of SDVO devices fail to notify of sync, but it's
1131 * a given it the status is a success, we succeeded.
1132 */
1133 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1134 DRM_DEBUG("First %s output reported failure to sync\n",
1135 SDVO_NAME(sdvo_priv));
1136 }
1137
1138 if (0)
1139 intel_sdvo_set_encoder_power_state(intel_output, mode);
1140 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
1141 }
1142 return;
1143 }
1144
1145 static void intel_sdvo_save(struct drm_connector *connector)
1146 {
1147 struct drm_device *dev = connector->dev;
1148 struct drm_i915_private *dev_priv = dev->dev_private;
1149 struct intel_output *intel_output = to_intel_output(connector);
1150 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1151 int o;
1152
1153 sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
1154 intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
1155
1156 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1157 intel_sdvo_set_target_input(intel_output, true, false);
1158 intel_sdvo_get_input_timing(intel_output,
1159 &sdvo_priv->save_input_dtd_1);
1160 }
1161
1162 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1163 intel_sdvo_set_target_input(intel_output, false, true);
1164 intel_sdvo_get_input_timing(intel_output,
1165 &sdvo_priv->save_input_dtd_2);
1166 }
1167
1168 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1169 {
1170 u16 this_output = (1 << o);
1171 if (sdvo_priv->caps.output_flags & this_output)
1172 {
1173 intel_sdvo_set_target_output(intel_output, this_output);
1174 intel_sdvo_get_output_timing(intel_output,
1175 &sdvo_priv->save_output_dtd[o]);
1176 }
1177 }
1178 if (sdvo_priv->is_tv) {
1179 /* XXX: Save TV format/enhancements. */
1180 }
1181
1182 sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
1183 }
1184
1185 static void intel_sdvo_restore(struct drm_connector *connector)
1186 {
1187 struct drm_device *dev = connector->dev;
1188 struct intel_output *intel_output = to_intel_output(connector);
1189 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1190 int o;
1191 int i;
1192 bool input1, input2;
1193 u8 status;
1194
1195 intel_sdvo_set_active_outputs(intel_output, 0);
1196
1197 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1198 {
1199 u16 this_output = (1 << o);
1200 if (sdvo_priv->caps.output_flags & this_output) {
1201 intel_sdvo_set_target_output(intel_output, this_output);
1202 intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
1203 }
1204 }
1205
1206 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1207 intel_sdvo_set_target_input(intel_output, true, false);
1208 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
1209 }
1210
1211 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1212 intel_sdvo_set_target_input(intel_output, false, true);
1213 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
1214 }
1215
1216 intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
1217
1218 if (sdvo_priv->is_tv) {
1219 /* XXX: Restore TV format/enhancements. */
1220 }
1221
1222 intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
1223
1224 if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1225 {
1226 for (i = 0; i < 2; i++)
1227 intel_wait_for_vblank(dev);
1228 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1229 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1230 DRM_DEBUG("First %s output reported failure to sync\n",
1231 SDVO_NAME(sdvo_priv));
1232 }
1233
1234 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
1235 }
1236
1237 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1238 struct drm_display_mode *mode)
1239 {
1240 struct intel_output *intel_output = to_intel_output(connector);
1241 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1242
1243 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1244 return MODE_NO_DBLESCAN;
1245
1246 if (sdvo_priv->pixel_clock_min > mode->clock)
1247 return MODE_CLOCK_LOW;
1248
1249 if (sdvo_priv->pixel_clock_max < mode->clock)
1250 return MODE_CLOCK_HIGH;
1251
1252 return MODE_OK;
1253 }
1254
1255 static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
1256 {
1257 u8 status;
1258
1259 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1260 status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
1261 if (status != SDVO_CMD_STATUS_SUCCESS)
1262 return false;
1263
1264 return true;
1265 }
1266
1267 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1268 {
1269 struct drm_connector *connector = NULL;
1270 struct intel_output *iout = NULL;
1271 struct intel_sdvo_priv *sdvo;
1272
1273 /* find the sdvo connector */
1274 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1275 iout = to_intel_output(connector);
1276
1277 if (iout->type != INTEL_OUTPUT_SDVO)
1278 continue;
1279
1280 sdvo = iout->dev_priv;
1281
1282 if (sdvo->output_device == SDVOB && sdvoB)
1283 return connector;
1284
1285 if (sdvo->output_device == SDVOC && !sdvoB)
1286 return connector;
1287
1288 }
1289
1290 return NULL;
1291 }
1292
1293 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1294 {
1295 u8 response[2];
1296 u8 status;
1297 struct intel_output *intel_output;
1298 DRM_DEBUG("\n");
1299
1300 if (!connector)
1301 return 0;
1302
1303 intel_output = to_intel_output(connector);
1304
1305 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1306 status = intel_sdvo_read_response(intel_output, &response, 2);
1307
1308 if (response[0] !=0)
1309 return 1;
1310
1311 return 0;
1312 }
1313
1314 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1315 {
1316 u8 response[2];
1317 u8 status;
1318 struct intel_output *intel_output = to_intel_output(connector);
1319
1320 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1321 intel_sdvo_read_response(intel_output, &response, 2);
1322
1323 if (on) {
1324 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1325 status = intel_sdvo_read_response(intel_output, &response, 2);
1326
1327 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1328 } else {
1329 response[0] = 0;
1330 response[1] = 0;
1331 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1332 }
1333
1334 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1335 intel_sdvo_read_response(intel_output, &response, 2);
1336 }
1337
1338 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1339 {
1340 u8 response[2];
1341 u8 status;
1342 struct intel_output *intel_output = to_intel_output(connector);
1343
1344 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1345 status = intel_sdvo_read_response(intel_output, &response, 2);
1346
1347 DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]);
1348
1349 if (status != SDVO_CMD_STATUS_SUCCESS)
1350 return connector_status_unknown;
1351
1352 if ((response[0] != 0) || (response[1] != 0))
1353 return connector_status_connected;
1354 else
1355 return connector_status_disconnected;
1356 }
1357
1358 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1359 {
1360 struct intel_output *intel_output = to_intel_output(connector);
1361 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1362
1363 /* set the bus switch and get the modes */
1364 intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
1365 intel_ddc_get_modes(intel_output);
1366
1367 #if 0
1368 struct drm_device *dev = encoder->dev;
1369 struct drm_i915_private *dev_priv = dev->dev_private;
1370 /* Mac mini hack. On this device, I get DDC through the analog, which
1371 * load-detects as disconnected. I fail to DDC through the SDVO DDC,
1372 * but it does load-detect as connected. So, just steal the DDC bits
1373 * from analog when we fail at finding it the right way.
1374 */
1375 crt = xf86_config->output[0];
1376 intel_output = crt->driver_private;
1377 if (intel_output->type == I830_OUTPUT_ANALOG &&
1378 crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
1379 I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A");
1380 edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
1381 xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true);
1382 }
1383 if (edid_mon) {
1384 xf86OutputSetEDID(output, edid_mon);
1385 modes = xf86OutputGetEDIDModes(output);
1386 }
1387 #endif
1388 }
1389
1390 /**
1391 * This function checks the current TV format, and chooses a default if
1392 * it hasn't been set.
1393 */
1394 static void
1395 intel_sdvo_check_tv_format(struct intel_output *output)
1396 {
1397 struct intel_sdvo_priv *dev_priv = output->dev_priv;
1398 struct intel_sdvo_tv_format format, unset;
1399 uint8_t status;
1400
1401 intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0);
1402 status = intel_sdvo_read_response(output, &format, sizeof(format));
1403 if (status != SDVO_CMD_STATUS_SUCCESS)
1404 return;
1405
1406 memset(&unset, 0, sizeof(unset));
1407 if (memcmp(&format, &unset, sizeof(format))) {
1408 DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n",
1409 SDVO_NAME(dev_priv));
1410
1411 format.ntsc_m = true;
1412 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, NULL, 0);
1413 status = intel_sdvo_read_response(output, NULL, 0);
1414 }
1415 }
1416
1417 /*
1418 * Set of SDVO TV modes.
1419 * Note! This is in reply order (see loop in get_tv_modes).
1420 * XXX: all 60Hz refresh?
1421 */
1422 struct drm_display_mode sdvo_tv_modes[] = {
1423 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815680, 321, 384, 416,
1424 200, 0, 232, 201, 233, 4196112, 0,
1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1426 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814080, 321, 384, 416,
1427 240, 0, 272, 241, 273, 4196112, 0,
1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1429 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910080, 401, 464, 496,
1430 300, 0, 332, 301, 333, 4196112, 0,
1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1432 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913280, 641, 704, 736,
1433 350, 0, 382, 351, 383, 4196112, 0,
1434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1435 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121280, 641, 704, 736,
1436 400, 0, 432, 401, 433, 4196112, 0,
1437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1438 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121280, 641, 704, 736,
1439 400, 0, 432, 401, 433, 4196112, 0,
1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1441 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624000, 705, 768, 800,
1442 480, 0, 512, 481, 513, 4196112, 0,
1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1444 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232000, 705, 768, 800,
1445 576, 0, 608, 577, 609, 4196112, 0,
1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1447 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751680, 721, 784, 816,
1448 350, 0, 382, 351, 383, 4196112, 0,
1449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1450 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199680, 721, 784, 816,
1451 400, 0, 432, 401, 433, 4196112, 0,
1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1453 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116480, 721, 784, 816,
1454 480, 0, 512, 481, 513, 4196112, 0,
1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1456 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054080, 721, 784, 816,
1457 540, 0, 572, 541, 573, 4196112, 0,
1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1459 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816640, 721, 784, 816,
1460 576, 0, 608, 577, 609, 4196112, 0,
1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1462 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570560, 769, 832, 864,
1463 576, 0, 608, 577, 609, 4196112, 0,
1464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1465 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030080, 801, 864, 896,
1466 600, 0, 632, 601, 633, 4196112, 0,
1467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1468 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581760, 833, 896, 928,
1469 624, 0, 656, 625, 657, 4196112, 0,
1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1471 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707040, 921, 984, 1016,
1472 766, 0, 798, 767, 799, 4196112, 0,
1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1474 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827200, 1025, 1088, 1120,
1475 768, 0, 800, 769, 801, 4196112, 0,
1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1477 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265920, 1281, 1344, 1376,
1478 1024, 0, 1056, 1025, 1057, 4196112, 0,
1479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1480 };
1481
1482 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1483 {
1484 struct intel_output *output = to_intel_output(connector);
1485 uint32_t reply = 0;
1486 uint8_t status;
1487 int i = 0;
1488
1489 intel_sdvo_check_tv_format(output);
1490
1491 /* Read the list of supported input resolutions for the selected TV
1492 * format.
1493 */
1494 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1495 NULL, 0);
1496 status = intel_sdvo_read_response(output, &reply, 3);
1497 if (status != SDVO_CMD_STATUS_SUCCESS)
1498 return;
1499
1500 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1501 if (reply & (1 << i))
1502 drm_mode_probed_add(connector, &sdvo_tv_modes[i]);
1503 }
1504
1505 static int intel_sdvo_get_modes(struct drm_connector *connector)
1506 {
1507 struct intel_output *output = to_intel_output(connector);
1508 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1509
1510 if (sdvo_priv->is_tv)
1511 intel_sdvo_get_tv_modes(connector);
1512 else
1513 intel_sdvo_get_ddc_modes(connector);
1514
1515 if (list_empty(&connector->probed_modes))
1516 return 0;
1517 return 1;
1518 }
1519
1520 static void intel_sdvo_destroy(struct drm_connector *connector)
1521 {
1522 struct intel_output *intel_output = to_intel_output(connector);
1523
1524 if (intel_output->i2c_bus)
1525 intel_i2c_destroy(intel_output->i2c_bus);
1526 drm_sysfs_connector_remove(connector);
1527 drm_connector_cleanup(connector);
1528 kfree(intel_output);
1529 }
1530
1531 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1532 .dpms = intel_sdvo_dpms,
1533 .mode_fixup = intel_sdvo_mode_fixup,
1534 .prepare = intel_encoder_prepare,
1535 .mode_set = intel_sdvo_mode_set,
1536 .commit = intel_encoder_commit,
1537 };
1538
1539 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
1540 .save = intel_sdvo_save,
1541 .restore = intel_sdvo_restore,
1542 .detect = intel_sdvo_detect,
1543 .fill_modes = drm_helper_probe_single_connector_modes,
1544 .destroy = intel_sdvo_destroy,
1545 };
1546
1547 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1548 .get_modes = intel_sdvo_get_modes,
1549 .mode_valid = intel_sdvo_mode_valid,
1550 .best_encoder = intel_best_encoder,
1551 };
1552
1553 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
1554 {
1555 drm_encoder_cleanup(encoder);
1556 }
1557
1558 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1559 .destroy = intel_sdvo_enc_destroy,
1560 };
1561
1562
1563 /**
1564 * Choose the appropriate DDC bus for control bus switch command for this
1565 * SDVO output based on the controlled output.
1566 *
1567 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1568 * outputs, then LVDS outputs.
1569 */
1570 static void
1571 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
1572 {
1573 uint16_t mask = 0;
1574 unsigned int num_bits;
1575
1576 /* Make a mask of outputs less than or equal to our own priority in the
1577 * list.
1578 */
1579 switch (dev_priv->controlled_output) {
1580 case SDVO_OUTPUT_LVDS1:
1581 mask |= SDVO_OUTPUT_LVDS1;
1582 case SDVO_OUTPUT_LVDS0:
1583 mask |= SDVO_OUTPUT_LVDS0;
1584 case SDVO_OUTPUT_TMDS1:
1585 mask |= SDVO_OUTPUT_TMDS1;
1586 case SDVO_OUTPUT_TMDS0:
1587 mask |= SDVO_OUTPUT_TMDS0;
1588 case SDVO_OUTPUT_RGB1:
1589 mask |= SDVO_OUTPUT_RGB1;
1590 case SDVO_OUTPUT_RGB0:
1591 mask |= SDVO_OUTPUT_RGB0;
1592 break;
1593 }
1594
1595 /* Count bits to find what number we are in the priority list. */
1596 mask &= dev_priv->caps.output_flags;
1597 num_bits = hweight16(mask);
1598 if (num_bits > 3) {
1599 /* if more than 3 outputs, default to DDC bus 3 for now */
1600 num_bits = 3;
1601 }
1602
1603 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1604 dev_priv->ddc_bus = 1 << num_bits;
1605 }
1606
1607 static bool
1608 intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
1609 {
1610 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1611 uint8_t status;
1612
1613 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1614
1615 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
1616 status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
1617 if (status != SDVO_CMD_STATUS_SUCCESS)
1618 return false;
1619 return true;
1620 }
1621
1622 bool intel_sdvo_init(struct drm_device *dev, int output_device)
1623 {
1624 struct drm_connector *connector;
1625 struct intel_output *intel_output;
1626 struct intel_sdvo_priv *sdvo_priv;
1627 struct intel_i2c_chan *i2cbus = NULL;
1628 int connector_type;
1629 u8 ch[0x40];
1630 int i;
1631 int encoder_type, output_id;
1632
1633 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
1634 if (!intel_output) {
1635 return false;
1636 }
1637
1638 connector = &intel_output->base;
1639
1640 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
1641 DRM_MODE_CONNECTOR_Unknown);
1642 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
1643 sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
1644 intel_output->type = INTEL_OUTPUT_SDVO;
1645
1646 connector->interlace_allowed = 0;
1647 connector->doublescan_allowed = 0;
1648
1649 /* setup the DDC bus. */
1650 if (output_device == SDVOB)
1651 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
1652 else
1653 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
1654
1655 if (!i2cbus)
1656 goto err_connector;
1657
1658 sdvo_priv->i2c_bus = i2cbus;
1659
1660 if (output_device == SDVOB) {
1661 output_id = 1;
1662 sdvo_priv->i2c_bus->slave_addr = 0x38;
1663 } else {
1664 output_id = 2;
1665 sdvo_priv->i2c_bus->slave_addr = 0x39;
1666 }
1667
1668 sdvo_priv->output_device = output_device;
1669 intel_output->i2c_bus = i2cbus;
1670 intel_output->dev_priv = sdvo_priv;
1671
1672
1673 /* Read the regs to test if we can talk to the device */
1674 for (i = 0; i < 0x40; i++) {
1675 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
1676 DRM_DEBUG("No SDVO device found on SDVO%c\n",
1677 output_device == SDVOB ? 'B' : 'C');
1678 goto err_i2c;
1679 }
1680 }
1681
1682 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
1683
1684 if (sdvo_priv->caps.output_flags &
1685 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1686 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
1687 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
1688 else
1689 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
1690
1691 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1692 encoder_type = DRM_MODE_ENCODER_TMDS;
1693 connector_type = DRM_MODE_CONNECTOR_DVID;
1694
1695 if (intel_sdvo_get_supp_encode(intel_output,
1696 &sdvo_priv->encode) &&
1697 intel_sdvo_get_digital_encoding_mode(intel_output) &&
1698 sdvo_priv->is_hdmi) {
1699 /* enable hdmi encoding mode if supported */
1700 intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
1701 intel_sdvo_set_colorimetry(intel_output,
1702 SDVO_COLORIMETRY_RGB256);
1703 connector_type = DRM_MODE_CONNECTOR_HDMIA;
1704 }
1705 }
1706 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_SVID0)
1707 {
1708 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
1709 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1710 encoder_type = DRM_MODE_ENCODER_TVDAC;
1711 connector_type = DRM_MODE_CONNECTOR_SVIDEO;
1712 sdvo_priv->is_tv = true;
1713 intel_output->needs_tv_clock = true;
1714 }
1715 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0)
1716 {
1717 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
1718 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1719 encoder_type = DRM_MODE_ENCODER_DAC;
1720 connector_type = DRM_MODE_CONNECTOR_VGA;
1721 }
1722 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1)
1723 {
1724 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
1725 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1726 encoder_type = DRM_MODE_ENCODER_DAC;
1727 connector_type = DRM_MODE_CONNECTOR_VGA;
1728 }
1729 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS0)
1730 {
1731 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
1732 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1733 encoder_type = DRM_MODE_ENCODER_LVDS;
1734 connector_type = DRM_MODE_CONNECTOR_LVDS;
1735 }
1736 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS1)
1737 {
1738 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
1739 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1740 encoder_type = DRM_MODE_ENCODER_LVDS;
1741 connector_type = DRM_MODE_CONNECTOR_LVDS;
1742 }
1743 else
1744 {
1745 unsigned char bytes[2];
1746
1747 sdvo_priv->controlled_output = 0;
1748 memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
1749 DRM_DEBUG("%s: Unknown SDVO output type (0x%02x%02x)\n",
1750 SDVO_NAME(sdvo_priv),
1751 bytes[0], bytes[1]);
1752 encoder_type = DRM_MODE_ENCODER_NONE;
1753 connector_type = DRM_MODE_CONNECTOR_Unknown;
1754 goto err_i2c;
1755 }
1756
1757 drm_encoder_init(dev, &intel_output->enc, &intel_sdvo_enc_funcs, encoder_type);
1758 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
1759 connector->connector_type = connector_type;
1760
1761 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
1762 drm_sysfs_connector_add(connector);
1763
1764 intel_sdvo_select_ddc_bus(sdvo_priv);
1765
1766 /* Set the input timing to the screen. Assume always input 0. */
1767 intel_sdvo_set_target_input(intel_output, true, false);
1768
1769 intel_sdvo_get_input_pixel_clock_range(intel_output,
1770 &sdvo_priv->pixel_clock_min,
1771 &sdvo_priv->pixel_clock_max);
1772
1773
1774 DRM_DEBUG("%s device VID/DID: %02X:%02X.%02X, "
1775 "clock range %dMHz - %dMHz, "
1776 "input 1: %c, input 2: %c, "
1777 "output 1: %c, output 2: %c\n",
1778 SDVO_NAME(sdvo_priv),
1779 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
1780 sdvo_priv->caps.device_rev_id,
1781 sdvo_priv->pixel_clock_min / 1000,
1782 sdvo_priv->pixel_clock_max / 1000,
1783 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
1784 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
1785 /* check currently supported outputs */
1786 sdvo_priv->caps.output_flags &
1787 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
1788 sdvo_priv->caps.output_flags &
1789 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
1790
1791 intel_output->ddc_bus = i2cbus;
1792
1793 return true;
1794
1795 err_i2c:
1796 intel_i2c_destroy(intel_output->i2c_bus);
1797 err_connector:
1798 drm_connector_cleanup(connector);
1799 kfree(intel_output);
1800
1801 return false;
1802 }
Nao low-level kernelspace/userspace library that runs on our robots, Nao-Team HTWK