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added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / drivers / gpu / drm / i915 / i915_dma.c
blob908d24e4a23e6bd1271dc70f1b0d94986884ac5e
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "intel_drv.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35
36 /* Really want an OS-independent resettable timer. Would like to have
37 * this loop run for (eg) 3 sec, but have the timer reset every time
38 * the head pointer changes, so that EBUSY only happens if the ring
39 * actually stalls for (eg) 3 seconds.
40 */
41 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
42 {
43 drm_i915_private_t *dev_priv = dev->dev_private;
44 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
45 u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
46 u32 last_acthd = I915_READ(acthd_reg);
47 u32 acthd;
48 u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
49 int i;
50
51 for (i = 0; i < 100000; i++) {
52 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
53 acthd = I915_READ(acthd_reg);
54 ring->space = ring->head - (ring->tail + 8);
55 if (ring->space < 0)
56 ring->space += ring->Size;
57 if (ring->space >= n)
58 return 0;
59
60 if (dev->primary->master) {
61 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
62 if (master_priv->sarea_priv)
63 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
64 }
65
66
67 if (ring->head != last_head)
68 i = 0;
69 if (acthd != last_acthd)
70 i = 0;
71
72 last_head = ring->head;
73 last_acthd = acthd;
74 msleep_interruptible(10);
75
76 }
77
78 return -EBUSY;
79 }
80
81 /**
82 * Sets up the hardware status page for devices that need a physical address
83 * in the register.
84 */
85 static int i915_init_phys_hws(struct drm_device *dev)
86 {
87 drm_i915_private_t *dev_priv = dev->dev_private;
88 /* Program Hardware Status Page */
89 dev_priv->status_page_dmah =
90 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
91
92 if (!dev_priv->status_page_dmah) {
93 DRM_ERROR("Can not allocate hardware status page\n");
94 return -ENOMEM;
95 }
96 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
97 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
98
99 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
100
101 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
102 DRM_DEBUG("Enabled hardware status page\n");
103 return 0;
104 }
105
106 /**
107 * Frees the hardware status page, whether it's a physical address or a virtual
108 * address set up by the X Server.
109 */
110 static void i915_free_hws(struct drm_device *dev)
111 {
112 drm_i915_private_t *dev_priv = dev->dev_private;
113 if (dev_priv->status_page_dmah) {
114 drm_pci_free(dev, dev_priv->status_page_dmah);
115 dev_priv->status_page_dmah = NULL;
116 }
117
118 if (dev_priv->status_gfx_addr) {
119 dev_priv->status_gfx_addr = 0;
120 drm_core_ioremapfree(&dev_priv->hws_map, dev);
121 }
122
123 /* Need to rewrite hardware status page */
124 I915_WRITE(HWS_PGA, 0x1ffff000);
125 }
126
127 void i915_kernel_lost_context(struct drm_device * dev)
128 {
129 drm_i915_private_t *dev_priv = dev->dev_private;
130 struct drm_i915_master_private *master_priv;
131 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
132
133 /*
134 * We should never lose context on the ring with modesetting
135 * as we don't expose it to userspace
136 */
137 if (drm_core_check_feature(dev, DRIVER_MODESET))
138 return;
139
140 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
141 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
142 ring->space = ring->head - (ring->tail + 8);
143 if (ring->space < 0)
144 ring->space += ring->Size;
145
146 if (!dev->primary->master)
147 return;
148
149 master_priv = dev->primary->master->driver_priv;
150 if (ring->head == ring->tail && master_priv->sarea_priv)
151 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
152 }
153
154 static int i915_dma_cleanup(struct drm_device * dev)
155 {
156 drm_i915_private_t *dev_priv = dev->dev_private;
157 /* Make sure interrupts are disabled here because the uninstall ioctl
158 * may not have been called from userspace and after dev_private
159 * is freed, it's too late.
160 */
161 if (dev->irq_enabled)
162 drm_irq_uninstall(dev);
163
164 if (dev_priv->ring.virtual_start) {
165 drm_core_ioremapfree(&dev_priv->ring.map, dev);
166 dev_priv->ring.virtual_start = NULL;
167 dev_priv->ring.map.handle = NULL;
168 dev_priv->ring.map.size = 0;
169 }
170
171 /* Clear the HWS virtual address at teardown */
172 if (I915_NEED_GFX_HWS(dev))
173 i915_free_hws(dev);
174
175 return 0;
176 }
177
178 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
179 {
180 drm_i915_private_t *dev_priv = dev->dev_private;
181 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
182
183 master_priv->sarea = drm_getsarea(dev);
184 if (master_priv->sarea) {
185 master_priv->sarea_priv = (drm_i915_sarea_t *)
186 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
187 } else {
188 DRM_DEBUG("sarea not found assuming DRI2 userspace\n");
189 }
190
191 if (init->ring_size != 0) {
192 if (dev_priv->ring.ring_obj != NULL) {
193 i915_dma_cleanup(dev);
194 DRM_ERROR("Client tried to initialize ringbuffer in "
195 "GEM mode\n");
196 return -EINVAL;
197 }
198
199 dev_priv->ring.Size = init->ring_size;
200 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
201
202 dev_priv->ring.map.offset = init->ring_start;
203 dev_priv->ring.map.size = init->ring_size;
204 dev_priv->ring.map.type = 0;
205 dev_priv->ring.map.flags = 0;
206 dev_priv->ring.map.mtrr = 0;
207
208 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
209
210 if (dev_priv->ring.map.handle == NULL) {
211 i915_dma_cleanup(dev);
212 DRM_ERROR("can not ioremap virtual address for"
213 " ring buffer\n");
214 return -ENOMEM;
215 }
216 }
217
218 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
219
220 dev_priv->cpp = init->cpp;
221 dev_priv->back_offset = init->back_offset;
222 dev_priv->front_offset = init->front_offset;
223 dev_priv->current_page = 0;
224 if (master_priv->sarea_priv)
225 master_priv->sarea_priv->pf_current_page = 0;
226
227 /* Allow hardware batchbuffers unless told otherwise.
228 */
229 dev_priv->allow_batchbuffer = 1;
230
231 return 0;
232 }
233
234 static int i915_dma_resume(struct drm_device * dev)
235 {
236 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
237
238 DRM_DEBUG("%s\n", __func__);
239
240 if (dev_priv->ring.map.handle == NULL) {
241 DRM_ERROR("can not ioremap virtual address for"
242 " ring buffer\n");
243 return -ENOMEM;
244 }
245
246 /* Program Hardware Status Page */
247 if (!dev_priv->hw_status_page) {
248 DRM_ERROR("Can not find hardware status page\n");
249 return -EINVAL;
250 }
251 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
252
253 if (dev_priv->status_gfx_addr != 0)
254 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
255 else
256 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
257 DRM_DEBUG("Enabled hardware status page\n");
258
259 return 0;
260 }
261
262 static int i915_dma_init(struct drm_device *dev, void *data,
263 struct drm_file *file_priv)
264 {
265 drm_i915_init_t *init = data;
266 int retcode = 0;
267
268 switch (init->func) {
269 case I915_INIT_DMA:
270 retcode = i915_initialize(dev, init);
271 break;
272 case I915_CLEANUP_DMA:
273 retcode = i915_dma_cleanup(dev);
274 break;
275 case I915_RESUME_DMA:
276 retcode = i915_dma_resume(dev);
277 break;
278 default:
279 retcode = -EINVAL;
280 break;
281 }
282
283 return retcode;
284 }
285
286 /* Implement basically the same security restrictions as hardware does
287 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
288 *
289 * Most of the calculations below involve calculating the size of a
290 * particular instruction. It's important to get the size right as
291 * that tells us where the next instruction to check is. Any illegal
292 * instruction detected will be given a size of zero, which is a
293 * signal to abort the rest of the buffer.
294 */
295 static int do_validate_cmd(int cmd)
296 {
297 switch (((cmd >> 29) & 0x7)) {
298 case 0x0:
299 switch ((cmd >> 23) & 0x3f) {
300 case 0x0:
301 return 1; /* MI_NOOP */
302 case 0x4:
303 return 1; /* MI_FLUSH */
304 default:
305 return 0; /* disallow everything else */
306 }
307 break;
308 case 0x1:
309 return 0; /* reserved */
310 case 0x2:
311 return (cmd & 0xff) + 2; /* 2d commands */
312 case 0x3:
313 if (((cmd >> 24) & 0x1f) <= 0x18)
314 return 1;
315
316 switch ((cmd >> 24) & 0x1f) {
317 case 0x1c:
318 return 1;
319 case 0x1d:
320 switch ((cmd >> 16) & 0xff) {
321 case 0x3:
322 return (cmd & 0x1f) + 2;
323 case 0x4:
324 return (cmd & 0xf) + 2;
325 default:
326 return (cmd & 0xffff) + 2;
327 }
328 case 0x1e:
329 if (cmd & (1 << 23))
330 return (cmd & 0xffff) + 1;
331 else
332 return 1;
333 case 0x1f:
334 if ((cmd & (1 << 23)) == 0) /* inline vertices */
335 return (cmd & 0x1ffff) + 2;
336 else if (cmd & (1 << 17)) /* indirect random */
337 if ((cmd & 0xffff) == 0)
338 return 0; /* unknown length, too hard */
339 else
340 return (((cmd & 0xffff) + 1) / 2) + 1;
341 else
342 return 2; /* indirect sequential */
343 default:
344 return 0;
345 }
346 default:
347 return 0;
348 }
349
350 return 0;
351 }
352
353 static int validate_cmd(int cmd)
354 {
355 int ret = do_validate_cmd(cmd);
356
357 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
358
359 return ret;
360 }
361
362 static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords)
363 {
364 drm_i915_private_t *dev_priv = dev->dev_private;
365 int i;
366 RING_LOCALS;
367
368 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
369 return -EINVAL;
370
371 BEGIN_LP_RING((dwords+1)&~1);
372
373 for (i = 0; i < dwords;) {
374 int cmd, sz;
375
376 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
377 return -EINVAL;
378
379 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
380 return -EINVAL;
381
382 OUT_RING(cmd);
383
384 while (++i, --sz) {
385 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
386 sizeof(cmd))) {
387 return -EINVAL;
388 }
389 OUT_RING(cmd);
390 }
391 }
392
393 if (dwords & 1)
394 OUT_RING(0);
395
396 ADVANCE_LP_RING();
397
398 return 0;
399 }
400
401 int
402 i915_emit_box(struct drm_device *dev,
403 struct drm_clip_rect __user *boxes,
404 int i, int DR1, int DR4)
405 {
406 drm_i915_private_t *dev_priv = dev->dev_private;
407 struct drm_clip_rect box;
408 RING_LOCALS;
409
410 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
411 return -EFAULT;
412 }
413
414 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
415 DRM_ERROR("Bad box %d,%d..%d,%d\n",
416 box.x1, box.y1, box.x2, box.y2);
417 return -EINVAL;
418 }
419
420 if (IS_I965G(dev)) {
421 BEGIN_LP_RING(4);
422 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
423 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
424 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
425 OUT_RING(DR4);
426 ADVANCE_LP_RING();
427 } else {
428 BEGIN_LP_RING(6);
429 OUT_RING(GFX_OP_DRAWRECT_INFO);
430 OUT_RING(DR1);
431 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
432 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
433 OUT_RING(DR4);
434 OUT_RING(0);
435 ADVANCE_LP_RING();
436 }
437
438 return 0;
439 }
440
441 /* XXX: Emitting the counter should really be moved to part of the IRQ
442 * emit. For now, do it in both places:
443 */
444
445 static void i915_emit_breadcrumb(struct drm_device *dev)
446 {
447 drm_i915_private_t *dev_priv = dev->dev_private;
448 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
449 RING_LOCALS;
450
451 dev_priv->counter++;
452 if (dev_priv->counter > 0x7FFFFFFFUL)
453 dev_priv->counter = 0;
454 if (master_priv->sarea_priv)
455 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
456
457 BEGIN_LP_RING(4);
458 OUT_RING(MI_STORE_DWORD_INDEX);
459 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
460 OUT_RING(dev_priv->counter);
461 OUT_RING(0);
462 ADVANCE_LP_RING();
463 }
464
465 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
466 drm_i915_cmdbuffer_t * cmd)
467 {
468 int nbox = cmd->num_cliprects;
469 int i = 0, count, ret;
470
471 if (cmd->sz & 0x3) {
472 DRM_ERROR("alignment");
473 return -EINVAL;
474 }
475
476 i915_kernel_lost_context(dev);
477
478 count = nbox ? nbox : 1;
479
480 for (i = 0; i < count; i++) {
481 if (i < nbox) {
482 ret = i915_emit_box(dev, cmd->cliprects, i,
483 cmd->DR1, cmd->DR4);
484 if (ret)
485 return ret;
486 }
487
488 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
489 if (ret)
490 return ret;
491 }
492
493 i915_emit_breadcrumb(dev);
494 return 0;
495 }
496
497 static int i915_dispatch_batchbuffer(struct drm_device * dev,
498 drm_i915_batchbuffer_t * batch)
499 {
500 drm_i915_private_t *dev_priv = dev->dev_private;
501 struct drm_clip_rect __user *boxes = batch->cliprects;
502 int nbox = batch->num_cliprects;
503 int i = 0, count;
504 RING_LOCALS;
505
506 if ((batch->start | batch->used) & 0x7) {
507 DRM_ERROR("alignment");
508 return -EINVAL;
509 }
510
511 i915_kernel_lost_context(dev);
512
513 count = nbox ? nbox : 1;
514
515 for (i = 0; i < count; i++) {
516 if (i < nbox) {
517 int ret = i915_emit_box(dev, boxes, i,
518 batch->DR1, batch->DR4);
519 if (ret)
520 return ret;
521 }
522
523 if (!IS_I830(dev) && !IS_845G(dev)) {
524 BEGIN_LP_RING(2);
525 if (IS_I965G(dev)) {
526 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
527 OUT_RING(batch->start);
528 } else {
529 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
530 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
531 }
532 ADVANCE_LP_RING();
533 } else {
534 BEGIN_LP_RING(4);
535 OUT_RING(MI_BATCH_BUFFER);
536 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
537 OUT_RING(batch->start + batch->used - 4);
538 OUT_RING(0);
539 ADVANCE_LP_RING();
540 }
541 }
542
543 i915_emit_breadcrumb(dev);
544
545 return 0;
546 }
547
548 static int i915_dispatch_flip(struct drm_device * dev)
549 {
550 drm_i915_private_t *dev_priv = dev->dev_private;
551 struct drm_i915_master_private *master_priv =
552 dev->primary->master->driver_priv;
553 RING_LOCALS;
554
555 if (!master_priv->sarea_priv)
556 return -EINVAL;
557
558 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
559 __func__,
560 dev_priv->current_page,
561 master_priv->sarea_priv->pf_current_page);
562
563 i915_kernel_lost_context(dev);
564
565 BEGIN_LP_RING(2);
566 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
567 OUT_RING(0);
568 ADVANCE_LP_RING();
569
570 BEGIN_LP_RING(6);
571 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
572 OUT_RING(0);
573 if (dev_priv->current_page == 0) {
574 OUT_RING(dev_priv->back_offset);
575 dev_priv->current_page = 1;
576 } else {
577 OUT_RING(dev_priv->front_offset);
578 dev_priv->current_page = 0;
579 }
580 OUT_RING(0);
581 ADVANCE_LP_RING();
582
583 BEGIN_LP_RING(2);
584 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
585 OUT_RING(0);
586 ADVANCE_LP_RING();
587
588 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
589
590 BEGIN_LP_RING(4);
591 OUT_RING(MI_STORE_DWORD_INDEX);
592 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
593 OUT_RING(dev_priv->counter);
594 OUT_RING(0);
595 ADVANCE_LP_RING();
596
597 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
598 return 0;
599 }
600
601 static int i915_quiescent(struct drm_device * dev)
602 {
603 drm_i915_private_t *dev_priv = dev->dev_private;
604
605 i915_kernel_lost_context(dev);
606 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
607 }
608
609 static int i915_flush_ioctl(struct drm_device *dev, void *data,
610 struct drm_file *file_priv)
611 {
612 int ret;
613
614 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
615
616 mutex_lock(&dev->struct_mutex);
617 ret = i915_quiescent(dev);
618 mutex_unlock(&dev->struct_mutex);
619
620 return ret;
621 }
622
623 static int i915_batchbuffer(struct drm_device *dev, void *data,
624 struct drm_file *file_priv)
625 {
626 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
627 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
628 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
629 master_priv->sarea_priv;
630 drm_i915_batchbuffer_t *batch = data;
631 int ret;
632
633 if (!dev_priv->allow_batchbuffer) {
634 DRM_ERROR("Batchbuffer ioctl disabled\n");
635 return -EINVAL;
636 }
637
638 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
639 batch->start, batch->used, batch->num_cliprects);
640
641 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
642
643 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
644 batch->num_cliprects *
645 sizeof(struct drm_clip_rect)))
646 return -EFAULT;
647
648 mutex_lock(&dev->struct_mutex);
649 ret = i915_dispatch_batchbuffer(dev, batch);
650 mutex_unlock(&dev->struct_mutex);
651
652 if (sarea_priv)
653 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
654 return ret;
655 }
656
657 static int i915_cmdbuffer(struct drm_device *dev, void *data,
658 struct drm_file *file_priv)
659 {
660 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
661 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
662 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
663 master_priv->sarea_priv;
664 drm_i915_cmdbuffer_t *cmdbuf = data;
665 int ret;
666
667 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
668 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
669
670 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
671
672 if (cmdbuf->num_cliprects &&
673 DRM_VERIFYAREA_READ(cmdbuf->cliprects,
674 cmdbuf->num_cliprects *
675 sizeof(struct drm_clip_rect))) {
676 DRM_ERROR("Fault accessing cliprects\n");
677 return -EFAULT;
678 }
679
680 mutex_lock(&dev->struct_mutex);
681 ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
682 mutex_unlock(&dev->struct_mutex);
683 if (ret) {
684 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
685 return ret;
686 }
687
688 if (sarea_priv)
689 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
690 return 0;
691 }
692
693 static int i915_flip_bufs(struct drm_device *dev, void *data,
694 struct drm_file *file_priv)
695 {
696 int ret;
697
698 DRM_DEBUG("%s\n", __func__);
699
700 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
701
702 mutex_lock(&dev->struct_mutex);
703 ret = i915_dispatch_flip(dev);
704 mutex_unlock(&dev->struct_mutex);
705
706 return ret;
707 }
708
709 static int i915_getparam(struct drm_device *dev, void *data,
710 struct drm_file *file_priv)
711 {
712 drm_i915_private_t *dev_priv = dev->dev_private;
713 drm_i915_getparam_t *param = data;
714 int value;
715
716 if (!dev_priv) {
717 DRM_ERROR("called with no initialization\n");
718 return -EINVAL;
719 }
720
721 switch (param->param) {
722 case I915_PARAM_IRQ_ACTIVE:
723 value = dev->pdev->irq ? 1 : 0;
724 break;
725 case I915_PARAM_ALLOW_BATCHBUFFER:
726 value = dev_priv->allow_batchbuffer ? 1 : 0;
727 break;
728 case I915_PARAM_LAST_DISPATCH:
729 value = READ_BREADCRUMB(dev_priv);
730 break;
731 case I915_PARAM_CHIPSET_ID:
732 value = dev->pci_device;
733 break;
734 case I915_PARAM_HAS_GEM:
735 value = dev_priv->has_gem;
736 break;
737 case I915_PARAM_NUM_FENCES_AVAIL:
738 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
739 break;
740 default:
741 DRM_DEBUG("Unknown parameter %d\n", param->param);
742 return -EINVAL;
743 }
744
745 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
746 DRM_ERROR("DRM_COPY_TO_USER failed\n");
747 return -EFAULT;
748 }
749
750 return 0;
751 }
752
753 static int i915_setparam(struct drm_device *dev, void *data,
754 struct drm_file *file_priv)
755 {
756 drm_i915_private_t *dev_priv = dev->dev_private;
757 drm_i915_setparam_t *param = data;
758
759 if (!dev_priv) {
760 DRM_ERROR("called with no initialization\n");
761 return -EINVAL;
762 }
763
764 switch (param->param) {
765 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
766 break;
767 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
768 dev_priv->tex_lru_log_granularity = param->value;
769 break;
770 case I915_SETPARAM_ALLOW_BATCHBUFFER:
771 dev_priv->allow_batchbuffer = param->value;
772 break;
773 case I915_SETPARAM_NUM_USED_FENCES:
774 if (param->value > dev_priv->num_fence_regs ||
775 param->value < 0)
776 return -EINVAL;
777 /* Userspace can use first N regs */
778 dev_priv->fence_reg_start = param->value;
779 break;
780 default:
781 DRM_DEBUG("unknown parameter %d\n", param->param);
782 return -EINVAL;
783 }
784
785 return 0;
786 }
787
788 static int i915_set_status_page(struct drm_device *dev, void *data,
789 struct drm_file *file_priv)
790 {
791 drm_i915_private_t *dev_priv = dev->dev_private;
792 drm_i915_hws_addr_t *hws = data;
793
794 if (!I915_NEED_GFX_HWS(dev))
795 return -EINVAL;
796
797 if (!dev_priv) {
798 DRM_ERROR("called with no initialization\n");
799 return -EINVAL;
800 }
801
802 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
803 WARN(1, "tried to set status page when mode setting active\n");
804 return 0;
805 }
806
807 printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr);
808
809 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
810
811 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
812 dev_priv->hws_map.size = 4*1024;
813 dev_priv->hws_map.type = 0;
814 dev_priv->hws_map.flags = 0;
815 dev_priv->hws_map.mtrr = 0;
816
817 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
818 if (dev_priv->hws_map.handle == NULL) {
819 i915_dma_cleanup(dev);
820 dev_priv->status_gfx_addr = 0;
821 DRM_ERROR("can not ioremap virtual address for"
822 " G33 hw status page\n");
823 return -ENOMEM;
824 }
825 dev_priv->hw_status_page = dev_priv->hws_map.handle;
826
827 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
828 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
829 DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
830 dev_priv->status_gfx_addr);
831 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
832 return 0;
833 }
834
835 /**
836 * i915_probe_agp - get AGP bootup configuration
837 * @pdev: PCI device
838 * @aperture_size: returns AGP aperture configured size
839 * @preallocated_size: returns size of BIOS preallocated AGP space
840 *
841 * Since Intel integrated graphics are UMA, the BIOS has to set aside
842 * some RAM for the framebuffer at early boot. This code figures out
843 * how much was set aside so we can use it for our own purposes.
844 */
845 static int i915_probe_agp(struct drm_device *dev, unsigned long *aperture_size,
846 unsigned long *preallocated_size)
847 {
848 struct pci_dev *bridge_dev;
849 u16 tmp = 0;
850 unsigned long overhead;
851 unsigned long stolen;
852
853 bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
854 if (!bridge_dev) {
855 DRM_ERROR("bridge device not found\n");
856 return -1;
857 }
858
859 /* Get the fb aperture size and "stolen" memory amount. */
860 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
861 pci_dev_put(bridge_dev);
862
863 *aperture_size = 1024 * 1024;
864 *preallocated_size = 1024 * 1024;
865
866 switch (dev->pdev->device) {
867 case PCI_DEVICE_ID_INTEL_82830_CGC:
868 case PCI_DEVICE_ID_INTEL_82845G_IG:
869 case PCI_DEVICE_ID_INTEL_82855GM_IG:
870 case PCI_DEVICE_ID_INTEL_82865_IG:
871 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
872 *aperture_size *= 64;
873 else
874 *aperture_size *= 128;
875 break;
876 default:
877 /* 9xx supports large sizes, just look at the length */
878 *aperture_size = pci_resource_len(dev->pdev, 2);
879 break;
880 }
881
882 /*
883 * Some of the preallocated space is taken by the GTT
884 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
885 */
886 if (IS_G4X(dev))
887 overhead = 4096;
888 else
889 overhead = (*aperture_size / 1024) + 4096;
890
891 switch (tmp & INTEL_GMCH_GMS_MASK) {
892 case INTEL_855_GMCH_GMS_DISABLED:
893 DRM_ERROR("video memory is disabled\n");
894 return -1;
895 case INTEL_855_GMCH_GMS_STOLEN_1M:
896 stolen = 1 * 1024 * 1024;
897 break;
898 case INTEL_855_GMCH_GMS_STOLEN_4M:
899 stolen = 4 * 1024 * 1024;
900 break;
901 case INTEL_855_GMCH_GMS_STOLEN_8M:
902 stolen = 8 * 1024 * 1024;
903 break;
904 case INTEL_855_GMCH_GMS_STOLEN_16M:
905 stolen = 16 * 1024 * 1024;
906 break;
907 case INTEL_855_GMCH_GMS_STOLEN_32M:
908 stolen = 32 * 1024 * 1024;
909 break;
910 case INTEL_915G_GMCH_GMS_STOLEN_48M:
911 stolen = 48 * 1024 * 1024;
912 break;
913 case INTEL_915G_GMCH_GMS_STOLEN_64M:
914 stolen = 64 * 1024 * 1024;
915 break;
916 case INTEL_GMCH_GMS_STOLEN_128M:
917 stolen = 128 * 1024 * 1024;
918 break;
919 case INTEL_GMCH_GMS_STOLEN_256M:
920 stolen = 256 * 1024 * 1024;
921 break;
922 case INTEL_GMCH_GMS_STOLEN_96M:
923 stolen = 96 * 1024 * 1024;
924 break;
925 case INTEL_GMCH_GMS_STOLEN_160M:
926 stolen = 160 * 1024 * 1024;
927 break;
928 case INTEL_GMCH_GMS_STOLEN_224M:
929 stolen = 224 * 1024 * 1024;
930 break;
931 case INTEL_GMCH_GMS_STOLEN_352M:
932 stolen = 352 * 1024 * 1024;
933 break;
934 default:
935 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
936 tmp & INTEL_GMCH_GMS_MASK);
937 return -1;
938 }
939 *preallocated_size = stolen - overhead;
940
941 return 0;
942 }
943
944 static int i915_load_modeset_init(struct drm_device *dev)
945 {
946 struct drm_i915_private *dev_priv = dev->dev_private;
947 unsigned long agp_size, prealloc_size;
948 int fb_bar = IS_I9XX(dev) ? 2 : 0;
949 int ret = 0;
950
951 dev->devname = kstrdup(DRIVER_NAME, GFP_KERNEL);
952 if (!dev->devname) {
953 ret = -ENOMEM;
954 goto out;
955 }
956
957 dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
958 0xff000000;
959
960 if (IS_MOBILE(dev) || IS_I9XX(dev))
961 dev_priv->cursor_needs_physical = true;
962 else
963 dev_priv->cursor_needs_physical = false;
964
965 if (IS_I965G(dev) || IS_G33(dev))
966 dev_priv->cursor_needs_physical = false;
967
968 ret = i915_probe_agp(dev, &agp_size, &prealloc_size);
969 if (ret)
970 goto kfree_devname;
971
972 /* Basic memrange allocator for stolen space (aka vram) */
973 drm_mm_init(&dev_priv->vram, 0, prealloc_size);
974
975 /* Let GEM Manage from end of prealloc space to end of aperture */
976 i915_gem_do_init(dev, prealloc_size, agp_size);
977
978 ret = i915_gem_init_ringbuffer(dev);
979 if (ret)
980 goto kfree_devname;
981
982 /* Allow hardware batchbuffers unless told otherwise.
983 */
984 dev_priv->allow_batchbuffer = 1;
985
986 ret = intel_init_bios(dev);
987 if (ret)
988 DRM_INFO("failed to find VBIOS tables\n");
989
990 ret = drm_irq_install(dev);
991 if (ret)
992 goto destroy_ringbuffer;
993
994 /* FIXME: re-add hotplug support */
995 #if 0
996 ret = drm_hotplug_init(dev);
997 if (ret)
998 goto destroy_ringbuffer;
999 #endif
1000
1001 /* Always safe in the mode setting case. */
1002 /* FIXME: do pre/post-mode set stuff in core KMS code */
1003 dev->vblank_disable_allowed = 1;
1004
1005 /*
1006 * Initialize the hardware status page IRQ location.
1007 */
1008
1009 I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1010
1011 intel_modeset_init(dev);
1012
1013 drm_helper_initial_config(dev, false);
1014
1015 return 0;
1016
1017 destroy_ringbuffer:
1018 i915_gem_cleanup_ringbuffer(dev);
1019 kfree_devname:
1020 kfree(dev->devname);
1021 out:
1022 return ret;
1023 }
1024
1025 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1026 {
1027 struct drm_i915_master_private *master_priv;
1028
1029 master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
1030 if (!master_priv)
1031 return -ENOMEM;
1032
1033 master->driver_priv = master_priv;
1034 return 0;
1035 }
1036
1037 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1038 {
1039 struct drm_i915_master_private *master_priv = master->driver_priv;
1040
1041 if (!master_priv)
1042 return;
1043
1044 drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
1045
1046 master->driver_priv = NULL;
1047 }
1048
1049 /**
1050 * i915_driver_load - setup chip and create an initial config
1051 * @dev: DRM device
1052 * @flags: startup flags
1053 *
1054 * The driver load routine has to do several things:
1055 * - drive output discovery via intel_modeset_init()
1056 * - initialize the memory manager
1057 * - allocate initial config memory
1058 * - setup the DRM framebuffer with the allocated memory
1059 */
1060 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1061 {
1062 struct drm_i915_private *dev_priv = dev->dev_private;
1063 unsigned long base, size;
1064 int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
1065
1066 /* i915 has 4 more counters */
1067 dev->counters += 4;
1068 dev->types[6] = _DRM_STAT_IRQ;
1069 dev->types[7] = _DRM_STAT_PRIMARY;
1070 dev->types[8] = _DRM_STAT_SECONDARY;
1071 dev->types[9] = _DRM_STAT_DMA;
1072
1073 dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
1074 if (dev_priv == NULL)
1075 return -ENOMEM;
1076
1077 memset(dev_priv, 0, sizeof(drm_i915_private_t));
1078
1079 dev->dev_private = (void *)dev_priv;
1080 dev_priv->dev = dev;
1081
1082 /* Add register map (needed for suspend/resume) */
1083 base = drm_get_resource_start(dev, mmio_bar);
1084 size = drm_get_resource_len(dev, mmio_bar);
1085
1086 dev_priv->regs = ioremap(base, size);
1087 if (!dev_priv->regs) {
1088 DRM_ERROR("failed to map registers\n");
1089 ret = -EIO;
1090 goto free_priv;
1091 }
1092
1093 dev_priv->mm.gtt_mapping =
1094 io_mapping_create_wc(dev->agp->base,
1095 dev->agp->agp_info.aper_size * 1024*1024);
1096 if (dev_priv->mm.gtt_mapping == NULL) {
1097 ret = -EIO;
1098 goto out_rmmap;
1099 }
1100
1101 /* Set up a WC MTRR for non-PAT systems. This is more common than
1102 * one would think, because the kernel disables PAT on first
1103 * generation Core chips because WC PAT gets overridden by a UC
1104 * MTRR if present. Even if a UC MTRR isn't present.
1105 */
1106 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1107 dev->agp->agp_info.aper_size *
1108 1024 * 1024,
1109 MTRR_TYPE_WRCOMB, 1);
1110 if (dev_priv->mm.gtt_mtrr < 0) {
1111 DRM_INFO("MTRR allocation failed. Graphics "
1112 "performance may suffer.\n");
1113 }
1114
1115 #ifdef CONFIG_HIGHMEM64G
1116 /* don't enable GEM on PAE - needs agp + set_memory_* interface fixes */
1117 dev_priv->has_gem = 0;
1118 #else
1119 /* enable GEM by default */
1120 dev_priv->has_gem = 1;
1121 #endif
1122
1123 dev->driver->get_vblank_counter = i915_get_vblank_counter;
1124 if (IS_GM45(dev))
1125 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1126
1127 i915_gem_load(dev);
1128
1129 /* Init HWS */
1130 if (!I915_NEED_GFX_HWS(dev)) {
1131 ret = i915_init_phys_hws(dev);
1132 if (ret != 0)
1133 goto out_iomapfree;
1134 }
1135
1136 /* On the 945G/GM, the chipset reports the MSI capability on the
1137 * integrated graphics even though the support isn't actually there
1138 * according to the published specs. It doesn't appear to function
1139 * correctly in testing on 945G.
1140 * This may be a side effect of MSI having been made available for PEG
1141 * and the registers being closely associated.
1142 *
1143 * According to chipset errata, on the 965GM, MSI interrupts may
1144 * be lost or delayed, but we use them anyways to avoid
1145 * stuck interrupts on some machines.
1146 */
1147 if (!IS_I945G(dev) && !IS_I945GM(dev))
1148 pci_enable_msi(dev->pdev);
1149
1150 intel_opregion_init(dev);
1151
1152 spin_lock_init(&dev_priv->user_irq_lock);
1153 dev_priv->user_irq_refcount = 0;
1154
1155 ret = drm_vblank_init(dev, I915_NUM_PIPE);
1156
1157 if (ret) {
1158 (void) i915_driver_unload(dev);
1159 return ret;
1160 }
1161
1162 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1163 ret = i915_load_modeset_init(dev);
1164 if (ret < 0) {
1165 DRM_ERROR("failed to init modeset\n");
1166 goto out_rmmap;
1167 }
1168 }
1169
1170 return 0;
1171
1172 out_iomapfree:
1173 io_mapping_free(dev_priv->mm.gtt_mapping);
1174 out_rmmap:
1175 iounmap(dev_priv->regs);
1176 free_priv:
1177 drm_free(dev_priv, sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
1178 return ret;
1179 }
1180
1181 int i915_driver_unload(struct drm_device *dev)
1182 {
1183 struct drm_i915_private *dev_priv = dev->dev_private;
1184
1185 io_mapping_free(dev_priv->mm.gtt_mapping);
1186 if (dev_priv->mm.gtt_mtrr >= 0) {
1187 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1188 dev->agp->agp_info.aper_size * 1024 * 1024);
1189 dev_priv->mm.gtt_mtrr = -1;
1190 }
1191
1192 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1193 drm_irq_uninstall(dev);
1194 }
1195
1196 if (dev->pdev->msi_enabled)
1197 pci_disable_msi(dev->pdev);
1198
1199 if (dev_priv->regs != NULL)
1200 iounmap(dev_priv->regs);
1201
1202 intel_opregion_free(dev);
1203
1204 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1205 intel_modeset_cleanup(dev);
1206
1207 i915_gem_free_all_phys_object(dev);
1208
1209 mutex_lock(&dev->struct_mutex);
1210 i915_gem_cleanup_ringbuffer(dev);
1211 mutex_unlock(&dev->struct_mutex);
1212 drm_mm_takedown(&dev_priv->vram);
1213 i915_gem_lastclose(dev);
1214 }
1215
1216 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
1217 DRM_MEM_DRIVER);
1218
1219 return 0;
1220 }
1221
1222 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1223 {
1224 struct drm_i915_file_private *i915_file_priv;
1225
1226 DRM_DEBUG("\n");
1227 i915_file_priv = (struct drm_i915_file_private *)
1228 drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
1229
1230 if (!i915_file_priv)
1231 return -ENOMEM;
1232
1233 file_priv->driver_priv = i915_file_priv;
1234
1235 i915_file_priv->mm.last_gem_seqno = 0;
1236 i915_file_priv->mm.last_gem_throttle_seqno = 0;
1237
1238 return 0;
1239 }
1240
1241 /**
1242 * i915_driver_lastclose - clean up after all DRM clients have exited
1243 * @dev: DRM device
1244 *
1245 * Take care of cleaning up after all DRM clients have exited. In the
1246 * mode setting case, we want to restore the kernel's initial mode (just
1247 * in case the last client left us in a bad state).
1248 *
1249 * Additionally, in the non-mode setting case, we'll tear down the AGP
1250 * and DMA structures, since the kernel won't be using them, and clea
1251 * up any GEM state.
1252 */
1253 void i915_driver_lastclose(struct drm_device * dev)
1254 {
1255 drm_i915_private_t *dev_priv = dev->dev_private;
1256
1257 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1258 intelfb_restore();
1259 return;
1260 }
1261
1262 i915_gem_lastclose(dev);
1263
1264 if (dev_priv->agp_heap)
1265 i915_mem_takedown(&(dev_priv->agp_heap));
1266
1267 i915_dma_cleanup(dev);
1268 }
1269
1270 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1271 {
1272 drm_i915_private_t *dev_priv = dev->dev_private;
1273 if (!drm_core_check_feature(dev, DRIVER_MODESET))
1274 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1275 }
1276
1277 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1278 {
1279 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1280
1281 drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
1282 }
1283
1284 struct drm_ioctl_desc i915_ioctls[] = {
1285 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1286 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1287 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1288 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1289 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1290 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1291 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1292 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1293 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1294 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1295 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1296 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1297 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1298 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1299 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1300 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1301 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1302 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1303 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1304 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1305 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1306 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1307 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1308 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1309 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1310 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1311 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1312 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1313 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1314 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0),
1315 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1316 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1317 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1318 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1319 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
1320 };
1321
1322 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1323
1324 /**
1325 * Determine if the device really is AGP or not.
1326 *
1327 * All Intel graphics chipsets are treated as AGP, even if they are really
1328 * PCI-e.
1329 *
1330 * \param dev The device to be tested.
1331 *
1332 * \returns
1333 * A value of 1 is always retured to indictate every i9x5 is AGP.
1334 */
1335 int i915_driver_device_is_agp(struct drm_device * dev)
1336 {
1337 return 1;
1338 }
Nao low-level kernelspace/userspace library that runs on our robots, Nao-Team HTWK