kernel/2.6.29.6-aldebaran-rt/arch/x86/kernel/irqinit_32.c

   1 #include <linux/errno.h>
   2 #include <linux/signal.h>
   3 #include <linux/sched.h>
   4 #include <linux/ioport.h>
   5 #include <linux/interrupt.h>
   6 #include <linux/slab.h>
   7 #include <linux/random.h>
   8 #include <linux/init.h>
   9 #include <linux/kernel_stat.h>
  10 #include <linux/sysdev.h>
  11 #include <linux/bitops.h>
  12 #include <linux/io.h>
  13 #include <linux/delay.h>
  14
  15 #include <asm/atomic.h>
  16 #include <asm/system.h>
  17 #include <asm/timer.h>
  18 #include <asm/pgtable.h>
  19 #include <asm/desc.h>
  20 #include <asm/apic.h>
  21 #include <asm/setup.h>
  22 #include <asm/i8259.h>
  23 #include <asm/traps.h>
  24
  25
  26 /*
  27  * Note that on a 486, we don't want to do a SIGFPE on an irq13
  28  * as the irq is unreliable, and exception 16 works correctly
  29  * (ie as explained in the intel literature). On a 386, you
  30  * can't use exception 16 due to bad IBM design, so we have to
  31  * rely on the less exact irq13.
  32  *
  33  * Careful.. Not only is IRQ13 unreliable, but it is also
  34  * leads to races. IBM designers who came up with it should
  35  * be shot.
  36  */
  37
  38 static irqreturn_t math_error_irq(int cpl, void *dev_id)
  39 {
  40         outb(0, 0xF0);
  41         if (ignore_fpu_irq || !boot_cpu_data.hard_math)
  42                 return IRQ_NONE;
  43         math_error((void __user *)get_irq_regs()->ip);
  44         return IRQ_HANDLED;
  45 }
  46
  47 /*
  48  * New motherboards sometimes make IRQ 13 be a PCI interrupt,
  49  * so allow interrupt sharing.
  50  */
  51 static struct irqaction fpu_irq = {
  52         .handler = math_error_irq,
  53         .flags = IRQF_NODELAY,
  54         .mask = CPU_MASK_NONE,
  55         .name = "fpu",
  56 };
  57
  58 void __init init_ISA_irqs(void)
  59 {
  60         int i;
  61
  62 #ifdef CONFIG_X86_LOCAL_APIC
  63         init_bsp_APIC();
  64 #endif
  65         init_8259A(0);
  66
  67         /*
  68          * 16 old-style INTA-cycle interrupts:
  69          */
  70         for (i = 0; i < NR_IRQS_LEGACY; i++) {
  71                 struct irq_desc *desc = irq_to_desc(i);
  72
  73                 desc->status = IRQ_DISABLED;
  74                 desc->action = NULL;
  75                 desc->depth = 1;
  76
  77                 set_irq_chip_and_handler_name(i, &i8259A_chip,
  78                                               handle_level_irq, "XT");
  79         }
  80 }
  81
  82 /*
  83  * IRQ2 is cascade interrupt to second interrupt controller
  84  */
  85 static struct irqaction irq2 = {
  86         .handler = no_action,
  87         .flags = IRQF_NODELAY,
  88         .mask = CPU_MASK_NONE,
  89         .name = "cascade",
  90 };
  91
  92 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
  93         [0 ... IRQ0_VECTOR - 1] = -1,
  94         [IRQ0_VECTOR] = 0,
  95         [IRQ1_VECTOR] = 1,
  96         [IRQ2_VECTOR] = 2,
  97         [IRQ3_VECTOR] = 3,
  98         [IRQ4_VECTOR] = 4,
  99         [IRQ5_VECTOR] = 5,
 100         [IRQ6_VECTOR] = 6,
 101         [IRQ7_VECTOR] = 7,
 102         [IRQ8_VECTOR] = 8,
 103         [IRQ9_VECTOR] = 9,
 104         [IRQ10_VECTOR] = 10,
 105         [IRQ11_VECTOR] = 11,
 106         [IRQ12_VECTOR] = 12,
 107         [IRQ13_VECTOR] = 13,
 108         [IRQ14_VECTOR] = 14,
 109         [IRQ15_VECTOR] = 15,
 110         [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
 111 };
 112
 113 int vector_used_by_percpu_irq(unsigned int vector)
 114 {
 115         int cpu;
 116
 117         for_each_online_cpu(cpu) {
 118                 if (per_cpu(vector_irq, cpu)[vector] != -1)
 119                         return 1;
 120         }
 121
 122         return 0;
 123 }
 124
 125 static void __init smp_intr_init(void)
 126 {
 127 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_SMP)
 128         /*
 129          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 130          * IPI, driven by wakeup.
 131          */
 132         alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 133
 134         /* IPIs for invalidation */
 135         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
 136         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
 137         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
 138         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
 139         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
 140         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
 141         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
 142         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
 143
 144         /* IPI for generic function call */
 145         alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 146
 147         /* IPI for single call function */
 148         alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
 149                                  call_function_single_interrupt);
 150
 151         /* Low priority IPI to cleanup after moving an irq */
 152         set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
 153         set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);
 154 #endif
 155 }
 156
 157 static void __init apic_intr_init(void)
 158 {
 159         smp_intr_init();
 160
 161 #ifdef CONFIG_X86_LOCAL_APIC
 162         /* self generated IPI for local APIC timer */
 163         alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 164
 165         /* generic IPI for platform specific use */
 166         alloc_intr_gate(GENERIC_INTERRUPT_VECTOR, generic_interrupt);
 167
 168         /* IPI vectors for APIC spurious and error interrupts */
 169         alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 170         alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 171 # ifdef CONFIG_PERF_COUNTERS
 172         alloc_intr_gate(LOCAL_PERF_VECTOR, perf_counter_interrupt);
 173 # endif
 174
 175 # ifdef CONFIG_X86_MCE_P4THERMAL
 176         /* thermal monitor LVT interrupt */
 177         alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 178 # endif
 179 #endif
 180 }
 181
 182 /* Overridden in paravirt.c */
 183 void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
 184
 185 void __init native_init_IRQ(void)
 186 {
 187         int i;
 188
 189         /* Execute any quirks before the call gates are initialised: */
 190         x86_quirk_pre_intr_init();
 191
 192         apic_intr_init();
 193
 194         /*
 195          * Cover the whole vector space, no vector can escape
 196          * us. (some of these will be overridden and become
 197          * 'special' SMP interrupts)
 198          */
 199         for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
 200                 int vector = FIRST_EXTERNAL_VECTOR + i;
 201                 /* SYSCALL_VECTOR was reserved in trap_init. */
 202                 if (!test_bit(vector, used_vectors))
 203                         set_intr_gate(vector, interrupt[i]);
 204         }
 205
 206         if (!acpi_ioapic)
 207                 setup_irq(2, &irq2);
 208
 209         /*
 210          * Call quirks after call gates are initialised (usually add in
 211          * the architecture specific gates):
 212          */
 213         x86_quirk_intr_init();
 214
 215         /*
 216          * External FPU? Set up irq13 if so, for
 217          * original braindamaged IBM FERR coupling.
 218          */
 219         if (boot_cpu_data.hard_math && !cpu_has_fpu)
 220                 setup_irq(FPU_IRQ, &fpu_irq);
 221
 222         irq_ctx_init(smp_processor_id());
 223 }