1 #include <linux/linkage.h>
2 #include <linux/errno.h>
3 #include <linux/signal.h>
4 #include <linux/sched.h>
5 #include <linux/ioport.h>
6 #include <linux/interrupt.h>
7 #include <linux/timex.h>
8 #include <linux/slab.h>
9 #include <linux/random.h>
10 #include <linux/init.h>
11 #include <linux/kernel_stat.h>
12 #include <linux/sysdev.h>
13 #include <linux/bitops.h>
14 #include <linux/acpi.h>
16 #include <linux/delay.h>
18 #include <asm/atomic.h>
19 #include <asm/system.h>
20 #include <asm/timer.h>
21 #include <asm/hw_irq.h>
22 #include <asm/pgtable.h>
25 #include <asm/i8259.h>
28 * This is the 'legacy' 8259A Programmable Interrupt Controller,
29 * present in the majority of PC/AT boxes.
30 * plus some generic x86 specific things if generic specifics makes
34 static int i8259A_auto_eoi
;
35 static void mask_and_ack_8259A(unsigned int);
36 DEFINE_RAW_SPINLOCK(i8259A_lock
);
38 struct irq_chip i8259A_chip
= {
40 .mask
= disable_8259A_irq
,
41 .disable
= disable_8259A_irq
,
42 .unmask
= enable_8259A_irq
,
43 .mask_ack
= mask_and_ack_8259A
,
47 * 8259A PIC functions to handle ISA devices:
51 * This contains the irq mask for both 8259A irq controllers,
53 unsigned int cached_irq_mask
= 0xffff;
56 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
57 * boards the timer interrupt is not really connected to any IO-APIC pin,
58 * it's fed to the master 8259A's IR0 line only.
60 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
61 * this 'mixed mode' IRQ handling costs nothing because it's only used
64 unsigned long io_apic_irqs
;
66 void disable_8259A_irq(unsigned int irq
)
68 unsigned int mask
= 1 << irq
;
71 spin_lock_irqsave(&i8259A_lock
, flags
);
72 cached_irq_mask
|= mask
;
74 outb(cached_slave_mask
, PIC_SLAVE_IMR
);
76 outb(cached_master_mask
, PIC_MASTER_IMR
);
77 spin_unlock_irqrestore(&i8259A_lock
, flags
);
80 void enable_8259A_irq(unsigned int irq
)
82 unsigned int mask
= ~(1 << irq
);
85 spin_lock_irqsave(&i8259A_lock
, flags
);
86 cached_irq_mask
&= mask
;
88 outb(cached_slave_mask
, PIC_SLAVE_IMR
);
90 outb(cached_master_mask
, PIC_MASTER_IMR
);
91 spin_unlock_irqrestore(&i8259A_lock
, flags
);
94 int i8259A_irq_pending(unsigned int irq
)
96 unsigned int mask
= 1<<irq
;
100 spin_lock_irqsave(&i8259A_lock
, flags
);
102 ret
= inb(PIC_MASTER_CMD
) & mask
;
104 ret
= inb(PIC_SLAVE_CMD
) & (mask
>> 8);
105 spin_unlock_irqrestore(&i8259A_lock
, flags
);
110 void make_8259A_irq(unsigned int irq
)
112 disable_irq_nosync(irq
);
113 io_apic_irqs
&= ~(1<<irq
);
114 set_irq_chip_and_handler_name(irq
, &i8259A_chip
, handle_level_irq
,
120 * This function assumes to be called rarely. Switching between
121 * 8259A registers is slow.
122 * This has to be protected by the irq controller spinlock
123 * before being called.
125 static inline int i8259A_irq_real(unsigned int irq
)
128 int irqmask
= 1<<irq
;
131 outb(0x0B, PIC_MASTER_CMD
); /* ISR register */
132 value
= inb(PIC_MASTER_CMD
) & irqmask
;
133 outb(0x0A, PIC_MASTER_CMD
); /* back to the IRR register */
136 outb(0x0B, PIC_SLAVE_CMD
); /* ISR register */
137 value
= inb(PIC_SLAVE_CMD
) & (irqmask
>> 8);
138 outb(0x0A, PIC_SLAVE_CMD
); /* back to the IRR register */
143 * Careful! The 8259A is a fragile beast, it pretty
144 * much _has_ to be done exactly like this (mask it
145 * first, _then_ send the EOI, and the order of EOI
146 * to the two 8259s is important!
148 static void mask_and_ack_8259A(unsigned int irq
)
150 unsigned int irqmask
= 1 << irq
;
153 spin_lock_irqsave(&i8259A_lock
, flags
);
155 * Lightweight spurious IRQ detection. We do not want
156 * to overdo spurious IRQ handling - it's usually a sign
157 * of hardware problems, so we only do the checks we can
158 * do without slowing down good hardware unnecessarily.
160 * Note that IRQ7 and IRQ15 (the two spurious IRQs
161 * usually resulting from the 8259A-1|2 PICs) occur
162 * even if the IRQ is masked in the 8259A. Thus we
163 * can check spurious 8259A IRQs without doing the
164 * quite slow i8259A_irq_real() call for every IRQ.
165 * This does not cover 100% of spurious interrupts,
166 * but should be enough to warn the user that there
167 * is something bad going on ...
169 if (cached_irq_mask
& irqmask
)
170 goto spurious_8259A_irq
;
172 outb(0x60+(irq
&7), PIC_SLAVE_CMD
); /* 'Specific EOI' to slave */
173 cached_irq_mask
|= irqmask
;
177 inb(PIC_SLAVE_IMR
); /* DUMMY - (do we need this?) */
178 outb(cached_slave_mask
, PIC_SLAVE_IMR
);
179 /* 'Specific EOI' to slave */
180 outb(0x60+(irq
&7), PIC_SLAVE_CMD
);
181 /* 'Specific EOI' to master-IRQ2 */
182 outb(0x60+PIC_CASCADE_IR
, PIC_MASTER_CMD
);
184 inb(PIC_MASTER_IMR
); /* DUMMY - (do we need this?) */
185 outb(cached_master_mask
, PIC_MASTER_IMR
);
186 outb(0x60+irq
, PIC_MASTER_CMD
); /* 'Specific EOI to master */
188 spin_unlock_irqrestore(&i8259A_lock
, flags
);
193 * this is the slow path - should happen rarely.
195 if (i8259A_irq_real(irq
))
197 * oops, the IRQ _is_ in service according to the
198 * 8259A - not spurious, go handle it.
200 goto handle_real_irq
;
203 static int spurious_irq_mask
;
205 * At this point we can be sure the IRQ is spurious,
206 * lets ACK and report it. [once per IRQ]
208 if (!(spurious_irq_mask
& irqmask
)) {
210 "spurious 8259A interrupt: IRQ%d.\n", irq
);
211 spurious_irq_mask
|= irqmask
;
213 atomic_inc(&irq_err_count
);
215 * Theoretically we do not have to handle this IRQ,
216 * but in Linux this does not cause problems and is
219 goto handle_real_irq
;
223 static char irq_trigger
[2];
225 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
227 static void restore_ELCR(char *trigger
)
229 outb(trigger
[0], 0x4d0);
230 outb(trigger
[1], 0x4d1);
233 static void save_ELCR(char *trigger
)
235 /* IRQ 0,1,2,8,13 are marked as reserved */
236 trigger
[0] = inb(0x4d0) & 0xF8;
237 trigger
[1] = inb(0x4d1) & 0xDE;
240 static int i8259A_resume(struct sys_device
*dev
)
242 init_8259A(i8259A_auto_eoi
);
243 restore_ELCR(irq_trigger
);
247 static int i8259A_suspend(struct sys_device
*dev
, pm_message_t state
)
249 save_ELCR(irq_trigger
);
253 static int i8259A_shutdown(struct sys_device
*dev
)
255 /* Put the i8259A into a quiescent state that
256 * the kernel initialization code can get it
259 outb(0xff, PIC_MASTER_IMR
); /* mask all of 8259A-1 */
260 outb(0xff, PIC_SLAVE_IMR
); /* mask all of 8259A-1 */
264 static struct sysdev_class i8259_sysdev_class
= {
266 .suspend
= i8259A_suspend
,
267 .resume
= i8259A_resume
,
268 .shutdown
= i8259A_shutdown
,
271 static struct sys_device device_i8259A
= {
273 .cls
= &i8259_sysdev_class
,
276 static int __init
i8259A_init_sysfs(void)
278 int error
= sysdev_class_register(&i8259_sysdev_class
);
280 error
= sysdev_register(&device_i8259A
);
284 device_initcall(i8259A_init_sysfs
);
286 void mask_8259A(void)
290 spin_lock_irqsave(&i8259A_lock
, flags
);
292 outb(0xff, PIC_MASTER_IMR
); /* mask all of 8259A-1 */
293 outb(0xff, PIC_SLAVE_IMR
); /* mask all of 8259A-2 */
295 spin_unlock_irqrestore(&i8259A_lock
, flags
);
298 void unmask_8259A(void)
302 spin_lock_irqsave(&i8259A_lock
, flags
);
304 outb(cached_master_mask
, PIC_MASTER_IMR
); /* restore master IRQ mask */
305 outb(cached_slave_mask
, PIC_SLAVE_IMR
); /* restore slave IRQ mask */
307 spin_unlock_irqrestore(&i8259A_lock
, flags
);
310 void init_8259A(int auto_eoi
)
314 i8259A_auto_eoi
= auto_eoi
;
316 spin_lock_irqsave(&i8259A_lock
, flags
);
318 outb(0xff, PIC_MASTER_IMR
); /* mask all of 8259A-1 */
319 outb(0xff, PIC_SLAVE_IMR
); /* mask all of 8259A-2 */
322 * outb_pic - this has to work on a wide range of PC hardware.
324 outb_pic(0x11, PIC_MASTER_CMD
); /* ICW1: select 8259A-1 init */
326 /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64,
327 to 0x20-0x27 on i386 */
328 outb_pic(IRQ0_VECTOR
, PIC_MASTER_IMR
);
330 /* 8259A-1 (the master) has a slave on IR2 */
331 outb_pic(1U << PIC_CASCADE_IR
, PIC_MASTER_IMR
);
333 if (!auto_eoi
) /* master expects normal EOI */
334 outb_p(MASTER_ICW4_DEFAULT
, PIC_MASTER_IMR
);
335 else /* master does Auto EOI */
336 outb_p(MASTER_ICW4_DEFAULT
| PIC_ICW4_AEOI
, PIC_MASTER_IMR
);
338 outb_pic(0x11, PIC_SLAVE_CMD
); /* ICW1: select 8259A-2 init */
340 /* ICW2: 8259A-2 IR0-7 mapped to IRQ8_VECTOR */
341 outb_pic(IRQ8_VECTOR
, PIC_SLAVE_IMR
);
342 /* 8259A-2 is a slave on master's IR2 */
343 outb_pic(PIC_CASCADE_IR
, PIC_SLAVE_IMR
);
344 /* (slave's support for AEOI in flat mode is to be investigated) */
345 outb_pic(SLAVE_ICW4_DEFAULT
, PIC_SLAVE_IMR
);
349 * In AEOI mode we just have to mask the interrupt
352 i8259A_chip
.mask_ack
= disable_8259A_irq
;
354 i8259A_chip
.mask_ack
= mask_and_ack_8259A
;
356 udelay(100); /* wait for 8259A to initialize */
358 outb(cached_master_mask
, PIC_MASTER_IMR
); /* restore master IRQ mask */
359 outb(cached_slave_mask
, PIC_SLAVE_IMR
); /* restore slave IRQ mask */
361 spin_unlock_irqrestore(&i8259A_lock
, flags
);