kernel/2.6.29.6-aldebaran-rt/arch/x86/kernel/cpu/cpufreq/cpufreq-nforce2.c

   1 /*
   2  * (C) 2004-2006  Sebastian Witt <se.witt@gmx.net>
   3  *
   4  *  Licensed under the terms of the GNU GPL License version 2.
   5  *  Based upon reverse engineered information
   6  *
   7  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/init.h>
  14 #include <linux/cpufreq.h>
  15 #include <linux/pci.h>
  16 #include <linux/delay.h>
  17
  18 #define NFORCE2_XTAL 25
  19 #define NFORCE2_BOOTFSB 0x48
  20 #define NFORCE2_PLLENABLE 0xa8
  21 #define NFORCE2_PLLREG 0xa4
  22 #define NFORCE2_PLLADR 0xa0
  23 #define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div)
  24
  25 #define NFORCE2_MIN_FSB 50
  26 #define NFORCE2_SAFE_DISTANCE 50
  27
  28 /* Delay in ms between FSB changes */
  29 /* #define NFORCE2_DELAY 10 */
  30
  31 /*
  32  * nforce2_chipset:
  33  * FSB is changed using the chipset
  34  */
  35 static struct pci_dev *nforce2_chipset_dev;
  36
  37 /* fid:
  38  * multiplier * 10
  39  */
  40 static int fid;
  41
  42 /* min_fsb, max_fsb:
  43  * minimum and maximum FSB (= FSB at boot time)
  44  */
  45 static int min_fsb;
  46 static int max_fsb;
  47
  48 MODULE_AUTHOR("Sebastian Witt <se.witt@gmx.net>");
  49 MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver");
  50 MODULE_LICENSE("GPL");
  51
  52 module_param(fid, int, 0444);
  53 module_param(min_fsb, int, 0444);
  54
  55 MODULE_PARM_DESC(fid, "CPU multiplier to use (11.5 = 115)");
  56 MODULE_PARM_DESC(min_fsb,
  57                 "Minimum FSB to use, if not defined: current FSB - 50");
  58
  59 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-nforce2", msg)
  60
  61 /**
  62  * nforce2_calc_fsb - calculate FSB
  63  * @pll: PLL value
  64  *
  65  *   Calculates FSB from PLL value
  66  */
  67 static int nforce2_calc_fsb(int pll)
  68 {
  69         unsigned char mul, div;
  70
  71         mul = (pll >> 8) & 0xff;
  72         div = pll & 0xff;
  73
  74         if (div > 0)
  75                 return NFORCE2_XTAL * mul / div;
  76
  77         return 0;
  78 }
  79
  80 /**
  81  * nforce2_calc_pll - calculate PLL value
  82  * @fsb: FSB
  83  *
  84  *   Calculate PLL value for given FSB
  85  */
  86 static int nforce2_calc_pll(unsigned int fsb)
  87 {
  88         unsigned char xmul, xdiv;
  89         unsigned char mul = 0, div = 0;
  90         int tried = 0;
  91
  92         /* Try to calculate multiplier and divider up to 4 times */
  93         while (((mul == 0) || (div == 0)) && (tried <= 3)) {
  94                 for (xdiv = 2; xdiv <= 0x80; xdiv++)
  95                         for (xmul = 1; xmul <= 0xfe; xmul++)
  96                                 if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) ==
  97                                     fsb + tried) {
  98                                         mul = xmul;
  99                                         div = xdiv;
 100                                 }
 101                 tried++;
 102         }
 103
 104         if ((mul == 0) || (div == 0))
 105                 return -1;
 106
 107         return NFORCE2_PLL(mul, div);
 108 }
 109
 110 /**
 111  * nforce2_write_pll - write PLL value to chipset
 112  * @pll: PLL value
 113  *
 114  *   Writes new FSB PLL value to chipset
 115  */
 116 static void nforce2_write_pll(int pll)
 117 {
 118         int temp;
 119
 120         /* Set the pll addr. to 0x00 */
 121         pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, 0);
 122
 123         /* Now write the value in all 64 registers */
 124         for (temp = 0; temp <= 0x3f; temp++)
 125                 pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLREG, pll);
 126
 127         return;
 128 }
 129
 130 /**
 131  * nforce2_fsb_read - Read FSB
 132  *
 133  *   Read FSB from chipset
 134  *   If bootfsb != 0, return FSB at boot-time
 135  */
 136 static unsigned int nforce2_fsb_read(int bootfsb)
 137 {
 138         struct pci_dev *nforce2_sub5;
 139         u32 fsb, temp = 0;
 140
 141         /* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
 142         nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
 143                                                 0x01EF, PCI_ANY_ID, PCI_ANY_ID, NULL);
 144         if (!nforce2_sub5)
 145                 return 0;
 146
 147         pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
 148         fsb /= 1000000;
 149
 150         /* Check if PLL register is already set */
 151         pci_read_config_byte(nforce2_chipset_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
 152
 153         if (bootfsb || !temp)
 154                 return fsb;
 155
 156         /* Use PLL register FSB value */
 157         pci_read_config_dword(nforce2_chipset_dev, NFORCE2_PLLREG, &temp);
 158         fsb = nforce2_calc_fsb(temp);
 159
 160         return fsb;
 161 }
 162
 163 /**
 164  * nforce2_set_fsb - set new FSB
 165  * @fsb: New FSB
 166  *
 167  *   Sets new FSB
 168  */
 169 static int nforce2_set_fsb(unsigned int fsb)
 170 {
 171         u32 temp = 0;
 172         unsigned int tfsb;
 173         int diff;
 174         int pll = 0;
 175
 176         if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) {
 177                 printk(KERN_ERR "cpufreq: FSB %d is out of range!\n", fsb);
 178                 return -EINVAL;
 179         }
 180
 181         tfsb = nforce2_fsb_read(0);
 182         if (!tfsb) {
 183                 printk(KERN_ERR "cpufreq: Error while reading the FSB\n");
 184                 return -EINVAL;
 185         }
 186
 187         /* First write? Then set actual value */
 188         pci_read_config_byte(nforce2_chipset_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
 189         if (!temp) {
 190                 pll = nforce2_calc_pll(tfsb);
 191
 192                 if (pll < 0)
 193                         return -EINVAL;
 194
 195                 nforce2_write_pll(pll);
 196         }
 197
 198         /* Enable write access */
 199         temp = 0x01;
 200         pci_write_config_byte(nforce2_chipset_dev, NFORCE2_PLLENABLE, (u8)temp);
 201
 202         diff = tfsb - fsb;
 203
 204         if (!diff)
 205                 return 0;
 206
 207         while ((tfsb != fsb) && (tfsb <= max_fsb) && (tfsb >= min_fsb)) {
 208                 if (diff < 0)
 209                         tfsb++;
 210                 else
 211                         tfsb--;
 212
 213                 /* Calculate the PLL reg. value */
 214                 pll = nforce2_calc_pll(tfsb);
 215                 if (pll == -1)
 216                         return -EINVAL;
 217
 218                 nforce2_write_pll(pll);
 219 #ifdef NFORCE2_DELAY
 220                 mdelay(NFORCE2_DELAY);
 221 #endif
 222         }
 223
 224         temp = 0x40;
 225         pci_write_config_byte(nforce2_chipset_dev, NFORCE2_PLLADR, (u8)temp);
 226
 227         return 0;
 228 }
 229
 230 /**
 231  * nforce2_get - get the CPU frequency
 232  * @cpu: CPU number
 233  *
 234  * Returns the CPU frequency
 235  */
 236 static unsigned int nforce2_get(unsigned int cpu)
 237 {
 238         if (cpu)
 239                 return 0;
 240         return nforce2_fsb_read(0) * fid * 100;
 241 }
 242
 243 /**
 244  * nforce2_target - set a new CPUFreq policy
 245  * @policy: new policy
 246  * @target_freq: the target frequency
 247  * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
 248  *
 249  * Sets a new CPUFreq policy.
 250  */
 251 static int nforce2_target(struct cpufreq_policy *policy,
 252                           unsigned int target_freq, unsigned int relation)
 253 {
 254 /*        unsigned long         flags; */
 255         struct cpufreq_freqs freqs;
 256         unsigned int target_fsb;
 257
 258         if ((target_freq > policy->max) || (target_freq < policy->min))
 259                 return -EINVAL;
 260
 261         target_fsb = target_freq / (fid * 100);
 262
 263         freqs.old = nforce2_get(policy->cpu);
 264         freqs.new = target_fsb * fid * 100;
 265         freqs.cpu = 0;          /* Only one CPU on nForce2 platforms */
 266
 267         if (freqs.old == freqs.new)
 268                 return 0;
 269
 270         dprintk("Old CPU frequency %d kHz, new %d kHz\n",
 271                freqs.old, freqs.new);
 272
 273         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 274
 275         /* Disable IRQs */
 276         /* local_irq_save(flags); */
 277
 278         if (nforce2_set_fsb(target_fsb) < 0)
 279                 printk(KERN_ERR "cpufreq: Changing FSB to %d failed\n",
 280                         target_fsb);
 281         else
 282                 dprintk("Changed FSB successfully to %d\n",
 283                         target_fsb);
 284
 285         /* Enable IRQs */
 286         /* local_irq_restore(flags); */
 287
 288         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 289
 290         return 0;
 291 }
 292
 293 /**
 294  * nforce2_verify - verifies a new CPUFreq policy
 295  * @policy: new policy
 296  */
 297 static int nforce2_verify(struct cpufreq_policy *policy)
 298 {
 299         unsigned int fsb_pol_max;
 300
 301         fsb_pol_max = policy->max / (fid * 100);
 302
 303         if (policy->min < (fsb_pol_max * fid * 100))
 304                 policy->max = (fsb_pol_max + 1) * fid * 100;
 305
 306         cpufreq_verify_within_limits(policy,
 307                                      policy->cpuinfo.min_freq,
 308                                      policy->cpuinfo.max_freq);
 309         return 0;
 310 }
 311
 312 static int nforce2_cpu_init(struct cpufreq_policy *policy)
 313 {
 314         unsigned int fsb;
 315         unsigned int rfid;
 316
 317         /* capability check */
 318         if (policy->cpu != 0)
 319                 return -ENODEV;
 320
 321         /* Get current FSB */
 322         fsb = nforce2_fsb_read(0);
 323
 324         if (!fsb)
 325                 return -EIO;
 326
 327         /* FIX: Get FID from CPU */
 328         if (!fid) {
 329                 if (!cpu_khz) {
 330                         printk(KERN_WARNING
 331                                "cpufreq: cpu_khz not set, can't calculate multiplier!\n");
 332                         return -ENODEV;
 333                 }
 334
 335                 fid = cpu_khz / (fsb * 100);
 336                 rfid = fid % 5;
 337
 338                 if (rfid) {
 339                         if (rfid > 2)
 340                                 fid += 5 - rfid;
 341                         else
 342                                 fid -= rfid;
 343                 }
 344         }
 345
 346         printk(KERN_INFO "cpufreq: FSB currently at %i MHz, FID %d.%d\n", fsb,
 347                fid / 10, fid % 10);
 348
 349         /* Set maximum FSB to FSB at boot time */
 350         max_fsb = nforce2_fsb_read(1);
 351
 352         if (!max_fsb)
 353                 return -EIO;
 354
 355         if (!min_fsb)
 356                 min_fsb = max_fsb - NFORCE2_SAFE_DISTANCE;
 357
 358         if (min_fsb < NFORCE2_MIN_FSB)
 359                 min_fsb = NFORCE2_MIN_FSB;
 360
 361         /* cpuinfo and default policy values */
 362         policy->cpuinfo.min_freq = min_fsb * fid * 100;
 363         policy->cpuinfo.max_freq = max_fsb * fid * 100;
 364         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
 365         policy->cur = nforce2_get(policy->cpu);
 366         policy->min = policy->cpuinfo.min_freq;
 367         policy->max = policy->cpuinfo.max_freq;
 368
 369         return 0;
 370 }
 371
 372 static int nforce2_cpu_exit(struct cpufreq_policy *policy)
 373 {
 374         return 0;
 375 }
 376
 377 static struct cpufreq_driver nforce2_driver = {
 378         .name = "nforce2",
 379         .verify = nforce2_verify,
 380         .target = nforce2_target,
 381         .get = nforce2_get,
 382         .init = nforce2_cpu_init,
 383         .exit = nforce2_cpu_exit,
 384         .owner = THIS_MODULE,
 385 };
 386
 387 /**
 388  * nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
 389  *
 390  * Detects nForce2 A2 and C1 stepping
 391  *
 392  */
 393 static unsigned int nforce2_detect_chipset(void)
 394 {
 395         nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
 396                                         PCI_DEVICE_ID_NVIDIA_NFORCE2,
 397                                         PCI_ANY_ID, PCI_ANY_ID, NULL);
 398
 399         if (nforce2_chipset_dev == NULL)
 400                 return -ENODEV;
 401
 402         printk(KERN_INFO "cpufreq: Detected nForce2 chipset revision %X\n",
 403                nforce2_chipset_dev->revision);
 404         printk(KERN_INFO
 405                "cpufreq: FSB changing is maybe unstable and can lead to crashes and data loss.\n");
 406
 407         return 0;
 408 }
 409
 410 /**
 411  * nforce2_init - initializes the nForce2 CPUFreq driver
 412  *
 413  * Initializes the nForce2 FSB support. Returns -ENODEV on unsupported
 414  * devices, -EINVAL on problems during initiatization, and zero on
 415  * success.
 416  */
 417 static int __init nforce2_init(void)
 418 {
 419         /* TODO: do we need to detect the processor? */
 420
 421         /* detect chipset */
 422         if (nforce2_detect_chipset()) {
 423                 printk(KERN_ERR "cpufreq: No nForce2 chipset.\n");
 424                 return -ENODEV;
 425         }
 426
 427         return cpufreq_register_driver(&nforce2_driver);
 428 }
 429
 430 /**
 431  * nforce2_exit - unregisters cpufreq module
 432  *
 433  *   Unregisters nForce2 FSB change support.
 434  */
 435 static void __exit nforce2_exit(void)
 436 {
 437         cpufreq_unregister_driver(&nforce2_driver);
 438 }
 439
 440 module_init(nforce2_init);
 441 module_exit(nforce2_exit);
 442