1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/delay.h>
9 #include <linux/sched.h>
10 #include <linux/init.h>
11 #include <linux/kgdb.h>
12 #include <linux/smp.h>
15 #include <asm/stackprotector.h>
16 #include <asm/perf_counter.h>
17 #include <asm/mmu_context.h>
18 #include <asm/hypervisor.h>
19 #include <asm/processor.h>
20 #include <asm/sections.h>
21 #include <asm/topology.h>
22 #include <asm/cpumask.h>
23 #include <asm/pgtable.h>
24 #include <asm/atomic.h>
25 #include <asm/proto.h>
26 #include <asm/setup.h>
39 #ifdef CONFIG_X86_LOCAL_APIC
40 #include <asm/uv/uv.h>
45 /* all of these masks are initialized in setup_cpu_local_masks() */
46 cpumask_var_t cpu_initialized_mask
;
47 cpumask_var_t cpu_callout_mask
;
48 cpumask_var_t cpu_callin_mask
;
50 /* representing cpus for which sibling maps can be computed */
51 cpumask_var_t cpu_sibling_setup_mask
;
53 /* correctly size the local cpu masks */
54 void __init
setup_cpu_local_masks(void)
56 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
57 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
58 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
59 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
62 static const struct cpu_dev
*this_cpu __cpuinitdata
;
64 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
67 * We need valid kernel segments for data and code in long mode too
68 * IRET will check the segment types kkeil 2000/10/28
69 * Also sysret mandates a special GDT layout
71 * TLS descriptors are currently at a different place compared to i386.
72 * Hopefully nobody expects them at a fixed place (Wine?)
74 [GDT_ENTRY_KERNEL32_CS
] = { { { 0x0000ffff, 0x00cf9b00 } } },
75 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00af9b00 } } },
76 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9300 } } },
77 [GDT_ENTRY_DEFAULT_USER32_CS
] = { { { 0x0000ffff, 0x00cffb00 } } },
78 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff300 } } },
79 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00affb00 } } },
81 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00cf9a00 } } },
82 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9200 } } },
83 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00cffa00 } } },
84 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff200 } } },
86 * Segments used for calling PnP BIOS have byte granularity.
87 * They code segments and data segments have fixed 64k limits,
88 * the transfer segment sizes are set at run time.
91 [GDT_ENTRY_PNPBIOS_CS32
] = { { { 0x0000ffff, 0x00409a00 } } },
93 [GDT_ENTRY_PNPBIOS_CS16
] = { { { 0x0000ffff, 0x00009a00 } } },
95 [GDT_ENTRY_PNPBIOS_DS
] = { { { 0x0000ffff, 0x00009200 } } },
97 [GDT_ENTRY_PNPBIOS_TS1
] = { { { 0x00000000, 0x00009200 } } },
99 [GDT_ENTRY_PNPBIOS_TS2
] = { { { 0x00000000, 0x00009200 } } },
101 * The APM segments have byte granularity and their bases
102 * are set at run time. All have 64k limits.
105 [GDT_ENTRY_APMBIOS_BASE
] = { { { 0x0000ffff, 0x00409a00 } } },
107 [GDT_ENTRY_APMBIOS_BASE
+1] = { { { 0x0000ffff, 0x00009a00 } } },
109 [GDT_ENTRY_APMBIOS_BASE
+2] = { { { 0x0000ffff, 0x00409200 } } },
111 [GDT_ENTRY_ESPFIX_SS
] = { { { 0x00000000, 0x00c09200 } } },
112 [GDT_ENTRY_PERCPU
] = { { { 0x0000ffff, 0x00cf9200 } } },
113 GDT_STACK_CANARY_INIT
116 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
119 static int cachesize_override __cpuinitdata
= -1;
120 static int disable_x86_serial_nr __cpuinitdata
= 1;
122 static int __init
cachesize_setup(char *str
)
124 get_option(&str
, &cachesize_override
);
127 __setup("cachesize=", cachesize_setup
);
129 static int __init
x86_fxsr_setup(char *s
)
131 setup_clear_cpu_cap(X86_FEATURE_FXSR
);
132 setup_clear_cpu_cap(X86_FEATURE_XMM
);
135 __setup("nofxsr", x86_fxsr_setup
);
137 static int __init
x86_sep_setup(char *s
)
139 setup_clear_cpu_cap(X86_FEATURE_SEP
);
142 __setup("nosep", x86_sep_setup
);
144 /* Standard macro to see if a specific flag is changeable */
145 static inline int flag_is_changeable_p(u32 flag
)
150 * Cyrix and IDT cpus allow disabling of CPUID
151 * so the code below may return different results
152 * when it is executed before and after enabling
153 * the CPUID. Add "volatile" to not allow gcc to
154 * optimize the subsequent calls to this function.
156 asm volatile ("pushfl \n\t"
167 : "=&r" (f1
), "=&r" (f2
)
170 return ((f1
^f2
) & flag
) != 0;
173 /* Probe for the CPUID instruction */
174 static int __cpuinit
have_cpuid_p(void)
176 return flag_is_changeable_p(X86_EFLAGS_ID
);
179 static void __cpuinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
181 unsigned long lo
, hi
;
183 if (!cpu_has(c
, X86_FEATURE_PN
) || !disable_x86_serial_nr
)
186 /* Disable processor serial number: */
188 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
190 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
192 printk(KERN_NOTICE
"CPU serial number disabled.\n");
193 clear_cpu_cap(c
, X86_FEATURE_PN
);
195 /* Disabling the serial number may affect the cpuid level */
196 c
->cpuid_level
= cpuid_eax(0);
199 static int __init
x86_serial_nr_setup(char *s
)
201 disable_x86_serial_nr
= 0;
204 __setup("serialnumber", x86_serial_nr_setup
);
206 static inline int flag_is_changeable_p(u32 flag
)
210 /* Probe for the CPUID instruction */
211 static inline int have_cpuid_p(void)
215 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
221 * Some CPU features depend on higher CPUID levels, which may not always
222 * be available due to CPUID level capping or broken virtualization
223 * software. Add those features to this table to auto-disable them.
225 struct cpuid_dependent_feature
{
230 static const struct cpuid_dependent_feature __cpuinitconst
231 cpuid_dependent_features
[] = {
232 { X86_FEATURE_MWAIT
, 0x00000005 },
233 { X86_FEATURE_DCA
, 0x00000009 },
234 { X86_FEATURE_XSAVE
, 0x0000000d },
238 static void __cpuinit
filter_cpuid_features(struct cpuinfo_x86
*c
, bool warn
)
240 const struct cpuid_dependent_feature
*df
;
242 for (df
= cpuid_dependent_features
; df
->feature
; df
++) {
244 if (!cpu_has(c
, df
->feature
))
247 * Note: cpuid_level is set to -1 if unavailable, but
248 * extended_extended_level is set to 0 if unavailable
249 * and the legitimate extended levels are all negative
250 * when signed; hence the weird messing around with
253 if (!((s32
)df
->level
< 0 ?
254 (u32
)df
->level
> (u32
)c
->extended_cpuid_level
:
255 (s32
)df
->level
> (s32
)c
->cpuid_level
))
258 clear_cpu_cap(c
, df
->feature
);
263 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
264 x86_cap_flags
[df
->feature
], df
->level
);
269 * Naming convention should be: <Name> [(<Codename>)]
270 * This table only is used unless init_<vendor>() below doesn't set it;
271 * in particular, if CPUID levels 0x80000002..4 are supported, this
275 /* Look up CPU names by table lookup. */
276 static const char *__cpuinit
table_lookup_model(struct cpuinfo_x86
*c
)
278 const struct cpu_model_info
*info
;
280 if (c
->x86_model
>= 16)
281 return NULL
; /* Range check */
286 info
= this_cpu
->c_models
;
288 while (info
&& info
->family
) {
289 if (info
->family
== c
->x86
)
290 return info
->model_names
[c
->x86_model
];
293 return NULL
; /* Not found */
296 __u32 cleared_cpu_caps
[NCAPINTS
] __cpuinitdata
;
298 void load_percpu_segment(int cpu
)
301 loadsegment(fs
, __KERNEL_PERCPU
);
304 wrmsrl(MSR_GS_BASE
, (unsigned long)per_cpu(irq_stack_union
.gs_base
, cpu
));
306 load_stack_canary_segment();
310 * Current gdt points %fs at the "master" per-cpu area: after this,
311 * it's on the real one.
313 void switch_to_new_gdt(int cpu
)
315 struct desc_ptr gdt_descr
;
317 gdt_descr
.address
= (long)get_cpu_gdt_table(cpu
);
318 gdt_descr
.size
= GDT_SIZE
- 1;
319 load_gdt(&gdt_descr
);
320 /* Reload the per-cpu base */
322 load_percpu_segment(cpu
);
325 static const struct cpu_dev
*__cpuinitdata cpu_devs
[X86_VENDOR_NUM
] = {};
327 static void __cpuinit
default_init(struct cpuinfo_x86
*c
)
330 display_cacheinfo(c
);
332 /* Not much we can do here... */
333 /* Check if at least it has cpuid */
334 if (c
->cpuid_level
== -1) {
335 /* No cpuid. It must be an ancient CPU */
337 strcpy(c
->x86_model_id
, "486");
338 else if (c
->x86
== 3)
339 strcpy(c
->x86_model_id
, "386");
344 static const struct cpu_dev __cpuinitconst default_cpu
= {
345 .c_init
= default_init
,
346 .c_vendor
= "Unknown",
347 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
350 static void __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
355 if (c
->extended_cpuid_level
< 0x80000004)
358 v
= (unsigned int *)c
->x86_model_id
;
359 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
360 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
361 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
362 c
->x86_model_id
[48] = 0;
365 * Intel chips right-justify this string for some dumb reason;
366 * undo that brain damage:
368 p
= q
= &c
->x86_model_id
[0];
374 while (q
<= &c
->x86_model_id
[48])
375 *q
++ = '\0'; /* Zero-pad the rest */
379 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
381 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
383 n
= c
->extended_cpuid_level
;
385 if (n
>= 0x80000005) {
386 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
387 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
388 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
389 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
391 /* On K8 L1 TLB is inclusive, so don't count it */
396 if (n
< 0x80000006) /* Some chips just has a large L1. */
399 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
403 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
405 /* do processor-specific cache resizing */
406 if (this_cpu
->c_size_cache
)
407 l2size
= this_cpu
->c_size_cache(c
, l2size
);
409 /* Allow user to override all this if necessary. */
410 if (cachesize_override
!= -1)
411 l2size
= cachesize_override
;
414 return; /* Again, no L2 cache is possible */
417 c
->x86_cache_size
= l2size
;
419 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
423 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
426 u32 eax
, ebx
, ecx
, edx
;
427 int index_msb
, core_bits
;
429 if (!cpu_has(c
, X86_FEATURE_HT
))
432 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
435 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
438 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
440 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
442 if (smp_num_siblings
== 1) {
443 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
447 if (smp_num_siblings
<= 1)
450 if (smp_num_siblings
> nr_cpu_ids
) {
451 pr_warning("CPU: Unsupported number of siblings %d",
453 smp_num_siblings
= 1;
457 index_msb
= get_count_order(smp_num_siblings
);
458 c
->phys_proc_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
);
460 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
462 index_msb
= get_count_order(smp_num_siblings
);
464 core_bits
= get_count_order(c
->x86_max_cores
);
466 c
->cpu_core_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
) &
467 ((1 << core_bits
) - 1);
470 if ((c
->x86_max_cores
* smp_num_siblings
) > 1) {
471 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
473 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
479 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
)
481 char *v
= c
->x86_vendor_id
;
485 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
489 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
490 (cpu_devs
[i
]->c_ident
[1] &&
491 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
493 this_cpu
= cpu_devs
[i
];
494 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
502 "CPU: vendor_id '%s' unknown, using generic init.\n", v
);
504 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
507 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
508 this_cpu
= &default_cpu
;
511 void __cpuinit
cpu_detect(struct cpuinfo_x86
*c
)
513 /* Get vendor name */
514 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
515 (unsigned int *)&c
->x86_vendor_id
[0],
516 (unsigned int *)&c
->x86_vendor_id
[8],
517 (unsigned int *)&c
->x86_vendor_id
[4]);
520 /* Intel-defined flags: level 0x00000001 */
521 if (c
->cpuid_level
>= 0x00000001) {
522 u32 junk
, tfms
, cap0
, misc
;
524 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
525 c
->x86
= (tfms
>> 8) & 0xf;
526 c
->x86_model
= (tfms
>> 4) & 0xf;
527 c
->x86_mask
= tfms
& 0xf;
530 c
->x86
+= (tfms
>> 20) & 0xff;
532 c
->x86_model
+= ((tfms
>> 16) & 0xf) << 4;
534 if (cap0
& (1<<19)) {
535 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
536 c
->x86_cache_alignment
= c
->x86_clflush_size
;
541 static void __cpuinit
get_cpu_cap(struct cpuinfo_x86
*c
)
546 /* Intel-defined flags: level 0x00000001 */
547 if (c
->cpuid_level
>= 0x00000001) {
548 u32 capability
, excap
;
550 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
551 c
->x86_capability
[0] = capability
;
552 c
->x86_capability
[4] = excap
;
555 /* AMD-defined flags: level 0x80000001 */
556 xlvl
= cpuid_eax(0x80000000);
557 c
->extended_cpuid_level
= xlvl
;
559 if ((xlvl
& 0xffff0000) == 0x80000000) {
560 if (xlvl
>= 0x80000001) {
561 c
->x86_capability
[1] = cpuid_edx(0x80000001);
562 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
566 if (c
->extended_cpuid_level
>= 0x80000008) {
567 u32 eax
= cpuid_eax(0x80000008);
569 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
570 c
->x86_phys_bits
= eax
& 0xff;
573 else if (cpu_has(c
, X86_FEATURE_PAE
) || cpu_has(c
, X86_FEATURE_PSE36
))
574 c
->x86_phys_bits
= 36;
577 if (c
->extended_cpuid_level
>= 0x80000007)
578 c
->x86_power
= cpuid_edx(0x80000007);
582 static void __cpuinit
identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
588 * First of all, decide if this is a 486 or higher
589 * It's a 486 if we can modify the AC flag
591 if (flag_is_changeable_p(X86_EFLAGS_AC
))
596 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
597 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
598 c
->x86_vendor_id
[0] = 0;
599 cpu_devs
[i
]->c_identify(c
);
600 if (c
->x86_vendor_id
[0]) {
609 * Do minimum CPU detection early.
610 * Fields really needed: vendor, cpuid_level, family, model, mask,
612 * The others are not touched to avoid unwanted side effects.
614 * WARNING: this function is only called on the BP. Don't add code here
615 * that is supposed to run on all CPUs.
617 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
620 c
->x86_clflush_size
= 64;
621 c
->x86_phys_bits
= 36;
622 c
->x86_virt_bits
= 48;
624 c
->x86_clflush_size
= 32;
625 c
->x86_phys_bits
= 32;
626 c
->x86_virt_bits
= 32;
628 c
->x86_cache_alignment
= c
->x86_clflush_size
;
630 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
631 c
->extended_cpuid_level
= 0;
634 identify_cpu_without_cpuid(c
);
636 /* cyrix could have cpuid enabled via c_identify()*/
646 if (this_cpu
->c_early_init
)
647 this_cpu
->c_early_init(c
);
650 c
->cpu_index
= boot_cpu_id
;
652 filter_cpuid_features(c
, false);
655 void __init
early_cpu_init(void)
657 const struct cpu_dev
*const *cdev
;
660 printk(KERN_INFO
"KERNEL supported cpus:\n");
661 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
662 const struct cpu_dev
*cpudev
= *cdev
;
665 if (count
>= X86_VENDOR_NUM
)
667 cpu_devs
[count
] = cpudev
;
670 for (j
= 0; j
< 2; j
++) {
671 if (!cpudev
->c_ident
[j
])
673 printk(KERN_INFO
" %s %s\n", cpudev
->c_vendor
,
678 early_identify_cpu(&boot_cpu_data
);
682 * The NOPL instruction is supposed to exist on all CPUs with
683 * family >= 6; unfortunately, that's not true in practice because
684 * of early VIA chips and (more importantly) broken virtualizers that
685 * are not easy to detect. In the latter case it doesn't even *fail*
686 * reliably, so probing for it doesn't even work. Disable it completely
687 * unless we can find a reliable way to detect all the broken cases.
689 static void __cpuinit
detect_nopl(struct cpuinfo_x86
*c
)
691 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
694 static void __cpuinit
generic_identify(struct cpuinfo_x86
*c
)
696 c
->extended_cpuid_level
= 0;
699 identify_cpu_without_cpuid(c
);
701 /* cyrix could have cpuid enabled via c_identify()*/
711 if (c
->cpuid_level
>= 0x00000001) {
712 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
714 # ifdef CONFIG_X86_HT
715 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
717 c
->apicid
= c
->initial_apicid
;
722 c
->phys_proc_id
= c
->initial_apicid
;
726 get_model_name(c
); /* Default name */
728 init_scattered_cpuid_features(c
);
733 * This does the hard work of actually picking apart the CPU stuff...
735 static void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
739 c
->loops_per_jiffy
= loops_per_jiffy
;
740 c
->x86_cache_size
= -1;
741 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
742 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
743 c
->x86_vendor_id
[0] = '\0'; /* Unset */
744 c
->x86_model_id
[0] = '\0'; /* Unset */
745 c
->x86_max_cores
= 1;
746 c
->x86_coreid_bits
= 0;
748 c
->x86_clflush_size
= 64;
749 c
->x86_phys_bits
= 36;
750 c
->x86_virt_bits
= 48;
752 c
->cpuid_level
= -1; /* CPUID not detected */
753 c
->x86_clflush_size
= 32;
754 c
->x86_phys_bits
= 32;
755 c
->x86_virt_bits
= 32;
757 c
->x86_cache_alignment
= c
->x86_clflush_size
;
758 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
762 if (this_cpu
->c_identify
)
763 this_cpu
->c_identify(c
);
766 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
770 * Vendor-specific initialization. In this section we
771 * canonicalize the feature flags, meaning if there are
772 * features a certain CPU supports which CPUID doesn't
773 * tell us, CPUID claiming incorrect flags, or other bugs,
774 * we handle them here.
776 * At the end of this section, c->x86_capability better
777 * indicate the features this CPU genuinely supports!
779 if (this_cpu
->c_init
)
782 /* Disable the PN if appropriate */
783 squash_the_stupid_serial_number(c
);
786 * The vendor-specific functions might have changed features.
787 * Now we do "generic changes."
790 /* Filter out anything that depends on CPUID levels we don't have */
791 filter_cpuid_features(c
, true);
793 /* If the model name is still unset, do table lookup. */
794 if (!c
->x86_model_id
[0]) {
796 p
= table_lookup_model(c
);
798 strcpy(c
->x86_model_id
, p
);
801 sprintf(c
->x86_model_id
, "%02x/%02x",
802 c
->x86
, c
->x86_model
);
811 * On SMP, boot_cpu_data holds the common feature set between
812 * all CPUs; so make sure that we indicate which features are
813 * common between the CPUs. The first time this routine gets
814 * executed, c == &boot_cpu_data.
816 if (c
!= &boot_cpu_data
) {
817 /* AND the already accumulated flags with these */
818 for (i
= 0; i
< NCAPINTS
; i
++)
819 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
822 /* Clear all flags overriden by options */
823 for (i
= 0; i
< NCAPINTS
; i
++)
824 c
->x86_capability
[i
] &= ~cleared_cpu_caps
[i
];
826 #ifdef CONFIG_X86_MCE
827 /* Init Machine Check Exception if available. */
831 select_idle_routine(c
);
833 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
834 numa_add_cpu(smp_processor_id());
839 static void vgetcpu_set_mode(void)
841 if (cpu_has(&boot_cpu_data
, X86_FEATURE_RDTSCP
))
842 vgetcpu_mode
= VGETCPU_RDTSCP
;
844 vgetcpu_mode
= VGETCPU_LSL
;
848 void __init
identify_boot_cpu(void)
850 identify_cpu(&boot_cpu_data
);
858 init_hw_perf_counters();
861 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
863 BUG_ON(c
== &boot_cpu_data
);
876 static const struct msr_range msr_range_array
[] __cpuinitconst
= {
877 { 0x00000000, 0x00000418},
878 { 0xc0000000, 0xc000040b},
879 { 0xc0010000, 0xc0010142},
880 { 0xc0011000, 0xc001103b},
883 static void __cpuinit
print_cpu_msr(void)
885 unsigned index_min
, index_max
;
890 for (i
= 0; i
< ARRAY_SIZE(msr_range_array
); i
++) {
891 index_min
= msr_range_array
[i
].min
;
892 index_max
= msr_range_array
[i
].max
;
894 for (index
= index_min
; index
< index_max
; index
++) {
895 if (rdmsrl_amd_safe(index
, &val
))
897 printk(KERN_INFO
" MSR%08x: %016llx\n", index
, val
);
902 static int show_msr __cpuinitdata
;
904 static __init
int setup_show_msr(char *arg
)
908 get_option(&arg
, &num
);
914 __setup("show_msr=", setup_show_msr
);
916 static __init
int setup_noclflush(char *arg
)
918 setup_clear_cpu_cap(X86_FEATURE_CLFLSH
);
921 __setup("noclflush", setup_noclflush
);
923 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
925 const char *vendor
= NULL
;
927 if (c
->x86_vendor
< X86_VENDOR_NUM
) {
928 vendor
= this_cpu
->c_vendor
;
930 if (c
->cpuid_level
>= 0)
931 vendor
= c
->x86_vendor_id
;
934 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
935 printk(KERN_CONT
"%s ", vendor
);
937 if (c
->x86_model_id
[0])
938 printk(KERN_CONT
"%s", c
->x86_model_id
);
940 printk(KERN_CONT
"%d86", c
->x86
);
942 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
943 printk(KERN_CONT
" stepping %02x\n", c
->x86_mask
);
945 printk(KERN_CONT
"\n");
948 if (c
->cpu_index
< show_msr
)
956 static __init
int setup_disablecpuid(char *arg
)
960 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
961 setup_clear_cpu_cap(bit
);
967 __setup("clearcpuid=", setup_disablecpuid
);
970 struct desc_ptr idt_descr
= { 256 * 16 - 1, (unsigned long) idt_table
};
972 DEFINE_PER_CPU_FIRST(union irq_stack_union
,
973 irq_stack_union
) __aligned(PAGE_SIZE
);
975 DEFINE_PER_CPU(char *, irq_stack_ptr
) =
976 init_per_cpu_var(irq_stack_union
.irq_stack
) + IRQ_STACK_SIZE
- 64;
978 DEFINE_PER_CPU(unsigned long, kernel_stack
) =
979 (unsigned long)&init_thread_union
- KERNEL_STACK_OFFSET
+ THREAD_SIZE
;
980 EXPORT_PER_CPU_SYMBOL(kernel_stack
);
982 DEFINE_PER_CPU(unsigned int, irq_count
) = -1;
985 * Special IST stacks which the CPU switches to when it calls
986 * an IST-marked descriptor entry. Up to 7 stacks (hardware
987 * limit), all of them are 4K, except the debug stack which
990 static const unsigned int exception_stack_sizes
[N_EXCEPTION_STACKS
] = {
991 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STKSZ
,
993 [DEBUG_STACK
- 1] = DEBUG_STKSZ
997 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
998 [(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+ DEBUG_STKSZ
])
999 __aligned(PAGE_SIZE
);
1001 /* May not be marked __init: used by software suspend */
1002 void syscall_init(void)
1005 * LSTAR and STAR live in a bit strange symbiosis.
1006 * They both write to the same internal register. STAR allows to
1007 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1009 wrmsrl(MSR_STAR
, ((u64
)__USER32_CS
)<<48 | ((u64
)__KERNEL_CS
)<<32);
1010 wrmsrl(MSR_LSTAR
, system_call
);
1011 wrmsrl(MSR_CSTAR
, ignore_sysret
);
1013 #ifdef CONFIG_IA32_EMULATION
1014 syscall32_cpu_init();
1017 /* Flags to clear on syscall */
1018 wrmsrl(MSR_SYSCALL_MASK
,
1019 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|X86_EFLAGS_IOPL
);
1022 unsigned long kernel_eflags
;
1025 * Copies of the original ist values from the tss are only accessed during
1026 * debugging, no special alignment required.
1028 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
1030 #else /* CONFIG_X86_64 */
1032 #ifdef CONFIG_CC_STACKPROTECTOR
1033 DEFINE_PER_CPU(unsigned long, stack_canary
);
1036 /* Make sure %fs and %gs are initialized properly in idle threads */
1037 struct pt_regs
* __cpuinit
idle_regs(struct pt_regs
*regs
)
1039 memset(regs
, 0, sizeof(struct pt_regs
));
1040 regs
->fs
= __KERNEL_PERCPU
;
1041 regs
->gs
= __KERNEL_STACK_CANARY
;
1045 #endif /* CONFIG_X86_64 */
1048 * Clear all 6 debug registers:
1050 static void clear_all_debug_regs(void)
1054 for (i
= 0; i
< 8; i
++) {
1055 /* Ignore db4, db5 */
1056 if ((i
== 4) || (i
== 5))
1064 * cpu_init() initializes state that is per-CPU. Some data is already
1065 * initialized (naturally) in the bootstrap process, such as the GDT
1066 * and IDT. We reload them nevertheless, this function acts as a
1067 * 'CPU state barrier', nothing should get across.
1068 * A lot of state is already set up in PDA init for 64 bit
1070 #ifdef CONFIG_X86_64
1072 void __cpuinit
cpu_init(void)
1074 struct orig_ist
*orig_ist
;
1075 struct task_struct
*me
;
1076 struct tss_struct
*t
;
1081 cpu
= stack_smp_processor_id();
1082 t
= &per_cpu(init_tss
, cpu
);
1083 orig_ist
= &per_cpu(orig_ist
, cpu
);
1086 if (cpu
!= 0 && percpu_read(node_number
) == 0 &&
1087 cpu_to_node(cpu
) != NUMA_NO_NODE
)
1088 percpu_write(node_number
, cpu_to_node(cpu
));
1093 if (cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
))
1094 panic("CPU#%d already initialized!\n", cpu
);
1096 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
1098 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1101 * Initialize the per-CPU GDT with the boot GDT,
1102 * and set up the GDT descriptor:
1105 switch_to_new_gdt(cpu
);
1108 load_idt((const struct desc_ptr
*)&idt_descr
);
1110 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1113 wrmsrl(MSR_FS_BASE
, 0);
1114 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1122 * set up and load the per-CPU TSS
1124 if (!orig_ist
->ist
[0]) {
1125 char *estacks
= per_cpu(exception_stacks
, cpu
);
1127 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
1128 estacks
+= exception_stack_sizes
[v
];
1129 orig_ist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
1130 (unsigned long)estacks
;
1134 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1137 * <= is required because the CPU will access up to
1138 * 8 bits beyond the end of the IO permission bitmap.
1140 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
1141 t
->io_bitmap
[i
] = ~0UL;
1143 atomic_inc(&init_mm
.mm_count
);
1144 me
->active_mm
= &init_mm
;
1146 enter_lazy_tlb(&init_mm
, me
);
1148 load_sp0(t
, ¤t
->thread
);
1149 set_tss_desc(cpu
, t
);
1151 load_LDT(&init_mm
.context
);
1155 * If the kgdb is connected no debug regs should be altered. This
1156 * is only applicable when KGDB and a KGDB I/O module are built
1157 * into the kernel and you are using early debugging with
1158 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1160 if (kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
)
1161 arch_kgdb_ops
.correct_hw_break();
1164 clear_all_debug_regs();
1168 raw_local_save_flags(kernel_eflags
);
1176 void __cpuinit
cpu_init(void)
1178 int cpu
= smp_processor_id();
1179 struct task_struct
*curr
= current
;
1180 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
1181 struct thread_struct
*thread
= &curr
->thread
;
1183 if (cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
)) {
1184 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
1189 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
1191 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
1192 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1194 load_idt(&idt_descr
);
1195 switch_to_new_gdt(cpu
);
1198 * Set up and load the per-CPU TSS and LDT
1200 atomic_inc(&init_mm
.mm_count
);
1201 curr
->active_mm
= &init_mm
;
1203 enter_lazy_tlb(&init_mm
, curr
);
1205 load_sp0(t
, thread
);
1206 set_tss_desc(cpu
, t
);
1208 load_LDT(&init_mm
.context
);
1210 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1212 #ifdef CONFIG_DOUBLEFAULT
1213 /* Set up doublefault TSS pointer in the GDT */
1214 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1217 clear_all_debug_regs();
1220 * Force FPU initialization:
1223 current_thread_info()->status
= TS_XSAVE
;
1225 current_thread_info()->status
= 0;
1227 mxcsr_feature_mask_init();
1230 * Boot processor to setup the FP and extended state context info.
1232 if (smp_processor_id() == boot_cpu_id
)
1233 init_thread_xstate();