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added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / arch / sh / kernel / traps_32.c
blob60dcf87ed019b76b5be51baf24c2156122b04350
1 /*
2 * 'traps.c' handles hardware traps and faults after we have saved some
3 * state in 'entry.S'.
4 *
5 * SuperH version: Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf
7 * Copyright (C) 2000 David Howells
8 * Copyright (C) 2002 - 2007 Paul Mundt
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/hardirq.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/module.h>
20 #include <linux/kallsyms.h>
21 #include <linux/io.h>
22 #include <linux/bug.h>
23 #include <linux/debug_locks.h>
24 #include <linux/kdebug.h>
25 #include <linux/kexec.h>
26 #include <linux/limits.h>
27 #include <asm/system.h>
28 #include <asm/uaccess.h>
29 #include <asm/fpu.h>
30 #include <asm/kprobes.h>
31
32 #ifdef CONFIG_CPU_SH2
33 # define TRAP_RESERVED_INST 4
34 # define TRAP_ILLEGAL_SLOT_INST 6
35 # define TRAP_ADDRESS_ERROR 9
36 # ifdef CONFIG_CPU_SH2A
37 # define TRAP_FPU_ERROR 13
38 # define TRAP_DIVZERO_ERROR 17
39 # define TRAP_DIVOVF_ERROR 18
40 # endif
41 #else
42 #define TRAP_RESERVED_INST 12
43 #define TRAP_ILLEGAL_SLOT_INST 13
44 #endif
45
46 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
47 {
48 unsigned long p;
49 int i;
50
51 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
52
53 for (p = bottom & ~31; p < top; ) {
54 printk("%04lx: ", p & 0xffff);
55
56 for (i = 0; i < 8; i++, p += 4) {
57 unsigned int val;
58
59 if (p < bottom || p >= top)
60 printk(" ");
61 else {
62 if (__get_user(val, (unsigned int __user *)p)) {
63 printk("\n");
64 return;
65 }
66 printk("%08x ", val);
67 }
68 }
69 printk("\n");
70 }
71 }
72
73 static DEFINE_SPINLOCK(die_lock);
74
75 void die(const char * str, struct pt_regs * regs, long err)
76 {
77 static int die_counter;
78
79 oops_enter();
80
81 console_verbose();
82 spin_lock_irq(&die_lock);
83 bust_spinlocks(1);
84
85 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
86
87 print_modules();
88 show_regs(regs);
89
90 printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
91 task_pid_nr(current), task_stack_page(current) + 1);
92
93 if (!user_mode(regs) || in_interrupt())
94 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
95 (unsigned long)task_stack_page(current));
96
97 notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
98
99 bust_spinlocks(0);
100 add_taint(TAINT_DIE);
101 spin_unlock_irq(&die_lock);
102
103 if (kexec_should_crash(current))
104 crash_kexec(regs);
105
106 if (in_interrupt())
107 panic("Fatal exception in interrupt");
108
109 if (panic_on_oops)
110 panic("Fatal exception");
111
112 oops_exit();
113 do_exit(SIGSEGV);
114 }
115
116 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
117 long err)
118 {
119 if (!user_mode(regs))
120 die(str, regs, err);
121 }
122
123 /*
124 * try and fix up kernelspace address errors
125 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
126 * - kernel/userspace interfaces cause a jump to an appropriate handler
127 * - other kernel errors are bad
128 */
129 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
130 {
131 if (!user_mode(regs)) {
132 const struct exception_table_entry *fixup;
133 fixup = search_exception_tables(regs->pc);
134 if (fixup) {
135 regs->pc = fixup->fixup;
136 return;
137 }
138 die(str, regs, err);
139 }
140 }
141
142 static inline void sign_extend(unsigned int count, unsigned char *dst)
143 {
144 #ifdef __LITTLE_ENDIAN__
145 if ((count == 1) && dst[0] & 0x80) {
146 dst[1] = 0xff;
147 dst[2] = 0xff;
148 dst[3] = 0xff;
149 }
150 if ((count == 2) && dst[1] & 0x80) {
151 dst[2] = 0xff;
152 dst[3] = 0xff;
153 }
154 #else
155 if ((count == 1) && dst[3] & 0x80) {
156 dst[2] = 0xff;
157 dst[1] = 0xff;
158 dst[0] = 0xff;
159 }
160 if ((count == 2) && dst[2] & 0x80) {
161 dst[1] = 0xff;
162 dst[0] = 0xff;
163 }
164 #endif
165 }
166
167 static struct mem_access user_mem_access = {
168 copy_from_user,
169 copy_to_user,
170 };
171
172 /*
173 * handle an instruction that does an unaligned memory access by emulating the
174 * desired behaviour
175 * - note that PC _may not_ point to the faulting instruction
176 * (if that instruction is in a branch delay slot)
177 * - return 0 if emulation okay, -EFAULT on existential error
178 */
179 static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
180 struct mem_access *ma)
181 {
182 int ret, index, count;
183 unsigned long *rm, *rn;
184 unsigned char *src, *dst;
185 unsigned char __user *srcu, *dstu;
186
187 index = (instruction>>8)&15; /* 0x0F00 */
188 rn = &regs->regs[index];
189
190 index = (instruction>>4)&15; /* 0x00F0 */
191 rm = &regs->regs[index];
192
193 count = 1<<(instruction&3);
194
195 ret = -EFAULT;
196 switch (instruction>>12) {
197 case 0: /* mov.[bwl] to/from memory via r0+rn */
198 if (instruction & 8) {
199 /* from memory */
200 srcu = (unsigned char __user *)*rm;
201 srcu += regs->regs[0];
202 dst = (unsigned char *)rn;
203 *(unsigned long *)dst = 0;
204
205 #if !defined(__LITTLE_ENDIAN__)
206 dst += 4-count;
207 #endif
208 if (ma->from(dst, srcu, count))
209 goto fetch_fault;
210
211 sign_extend(count, dst);
212 } else {
213 /* to memory */
214 src = (unsigned char *)rm;
215 #if !defined(__LITTLE_ENDIAN__)
216 src += 4-count;
217 #endif
218 dstu = (unsigned char __user *)*rn;
219 dstu += regs->regs[0];
220
221 if (ma->to(dstu, src, count))
222 goto fetch_fault;
223 }
224 ret = 0;
225 break;
226
227 case 1: /* mov.l Rm,@(disp,Rn) */
228 src = (unsigned char*) rm;
229 dstu = (unsigned char __user *)*rn;
230 dstu += (instruction&0x000F)<<2;
231
232 if (ma->to(dstu, src, 4))
233 goto fetch_fault;
234 ret = 0;
235 break;
236
237 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
238 if (instruction & 4)
239 *rn -= count;
240 src = (unsigned char*) rm;
241 dstu = (unsigned char __user *)*rn;
242 #if !defined(__LITTLE_ENDIAN__)
243 src += 4-count;
244 #endif
245 if (ma->to(dstu, src, count))
246 goto fetch_fault;
247 ret = 0;
248 break;
249
250 case 5: /* mov.l @(disp,Rm),Rn */
251 srcu = (unsigned char __user *)*rm;
252 srcu += (instruction & 0x000F) << 2;
253 dst = (unsigned char *)rn;
254 *(unsigned long *)dst = 0;
255
256 if (ma->from(dst, srcu, 4))
257 goto fetch_fault;
258 ret = 0;
259 break;
260
261 case 6: /* mov.[bwl] from memory, possibly with post-increment */
262 srcu = (unsigned char __user *)*rm;
263 if (instruction & 4)
264 *rm += count;
265 dst = (unsigned char*) rn;
266 *(unsigned long*)dst = 0;
267
268 #if !defined(__LITTLE_ENDIAN__)
269 dst += 4-count;
270 #endif
271 if (ma->from(dst, srcu, count))
272 goto fetch_fault;
273 sign_extend(count, dst);
274 ret = 0;
275 break;
276
277 case 8:
278 switch ((instruction&0xFF00)>>8) {
279 case 0x81: /* mov.w R0,@(disp,Rn) */
280 src = (unsigned char *) &regs->regs[0];
281 #if !defined(__LITTLE_ENDIAN__)
282 src += 2;
283 #endif
284 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
285 dstu += (instruction & 0x000F) << 1;
286
287 if (ma->to(dstu, src, 2))
288 goto fetch_fault;
289 ret = 0;
290 break;
291
292 case 0x85: /* mov.w @(disp,Rm),R0 */
293 srcu = (unsigned char __user *)*rm;
294 srcu += (instruction & 0x000F) << 1;
295 dst = (unsigned char *) &regs->regs[0];
296 *(unsigned long *)dst = 0;
297
298 #if !defined(__LITTLE_ENDIAN__)
299 dst += 2;
300 #endif
301 if (ma->from(dst, srcu, 2))
302 goto fetch_fault;
303 sign_extend(2, dst);
304 ret = 0;
305 break;
306 }
307 break;
308 }
309 return ret;
310
311 fetch_fault:
312 /* Argh. Address not only misaligned but also non-existent.
313 * Raise an EFAULT and see if it's trapped
314 */
315 die_if_no_fixup("Fault in unaligned fixup", regs, 0);
316 return -EFAULT;
317 }
318
319 /*
320 * emulate the instruction in the delay slot
321 * - fetches the instruction from PC+2
322 */
323 static inline int handle_delayslot(struct pt_regs *regs,
324 opcode_t old_instruction,
325 struct mem_access *ma)
326 {
327 opcode_t instruction;
328 void __user *addr = (void __user *)(regs->pc +
329 instruction_size(old_instruction));
330
331 if (copy_from_user(&instruction, addr, sizeof(instruction))) {
332 /* the instruction-fetch faulted */
333 if (user_mode(regs))
334 return -EFAULT;
335
336 /* kernel */
337 die("delay-slot-insn faulting in handle_unaligned_delayslot",
338 regs, 0);
339 }
340
341 return handle_unaligned_ins(instruction, regs, ma);
342 }
343
344 /*
345 * handle an instruction that does an unaligned memory access
346 * - have to be careful of branch delay-slot instructions that fault
347 * SH3:
348 * - if the branch would be taken PC points to the branch
349 * - if the branch would not be taken, PC points to delay-slot
350 * SH4:
351 * - PC always points to delayed branch
352 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
353 */
354
355 /* Macros to determine offset from current PC for branch instructions */
356 /* Explicit type coercion is used to force sign extension where needed */
357 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
358 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
359
360 /*
361 * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
362 * opcodes..
363 */
364
365 static int handle_unaligned_notify_count = 10;
366
367 int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs,
368 struct mem_access *ma)
369 {
370 u_int rm;
371 int ret, index;
372
373 index = (instruction>>8)&15; /* 0x0F00 */
374 rm = regs->regs[index];
375
376 /* shout about the first ten userspace fixups */
377 if (user_mode(regs) && handle_unaligned_notify_count>0) {
378 handle_unaligned_notify_count--;
379
380 printk(KERN_NOTICE "Fixing up unaligned userspace access "
381 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
382 current->comm, task_pid_nr(current),
383 (void *)regs->pc, instruction);
384 }
385
386 ret = -EFAULT;
387 switch (instruction&0xF000) {
388 case 0x0000:
389 if (instruction==0x000B) {
390 /* rts */
391 ret = handle_delayslot(regs, instruction, ma);
392 if (ret==0)
393 regs->pc = regs->pr;
394 }
395 else if ((instruction&0x00FF)==0x0023) {
396 /* braf @Rm */
397 ret = handle_delayslot(regs, instruction, ma);
398 if (ret==0)
399 regs->pc += rm + 4;
400 }
401 else if ((instruction&0x00FF)==0x0003) {
402 /* bsrf @Rm */
403 ret = handle_delayslot(regs, instruction, ma);
404 if (ret==0) {
405 regs->pr = regs->pc + 4;
406 regs->pc += rm + 4;
407 }
408 }
409 else {
410 /* mov.[bwl] to/from memory via r0+rn */
411 goto simple;
412 }
413 break;
414
415 case 0x1000: /* mov.l Rm,@(disp,Rn) */
416 goto simple;
417
418 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
419 goto simple;
420
421 case 0x4000:
422 if ((instruction&0x00FF)==0x002B) {
423 /* jmp @Rm */
424 ret = handle_delayslot(regs, instruction, ma);
425 if (ret==0)
426 regs->pc = rm;
427 }
428 else if ((instruction&0x00FF)==0x000B) {
429 /* jsr @Rm */
430 ret = handle_delayslot(regs, instruction, ma);
431 if (ret==0) {
432 regs->pr = regs->pc + 4;
433 regs->pc = rm;
434 }
435 }
436 else {
437 /* mov.[bwl] to/from memory via r0+rn */
438 goto simple;
439 }
440 break;
441
442 case 0x5000: /* mov.l @(disp,Rm),Rn */
443 goto simple;
444
445 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
446 goto simple;
447
448 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
449 switch (instruction&0x0F00) {
450 case 0x0100: /* mov.w R0,@(disp,Rm) */
451 goto simple;
452 case 0x0500: /* mov.w @(disp,Rm),R0 */
453 goto simple;
454 case 0x0B00: /* bf lab - no delayslot*/
455 break;
456 case 0x0F00: /* bf/s lab */
457 ret = handle_delayslot(regs, instruction, ma);
458 if (ret==0) {
459 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
460 if ((regs->sr & 0x00000001) != 0)
461 regs->pc += 4; /* next after slot */
462 else
463 #endif
464 regs->pc += SH_PC_8BIT_OFFSET(instruction);
465 }
466 break;
467 case 0x0900: /* bt lab - no delayslot */
468 break;
469 case 0x0D00: /* bt/s lab */
470 ret = handle_delayslot(regs, instruction, ma);
471 if (ret==0) {
472 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
473 if ((regs->sr & 0x00000001) == 0)
474 regs->pc += 4; /* next after slot */
475 else
476 #endif
477 regs->pc += SH_PC_8BIT_OFFSET(instruction);
478 }
479 break;
480 }
481 break;
482
483 case 0xA000: /* bra label */
484 ret = handle_delayslot(regs, instruction, ma);
485 if (ret==0)
486 regs->pc += SH_PC_12BIT_OFFSET(instruction);
487 break;
488
489 case 0xB000: /* bsr label */
490 ret = handle_delayslot(regs, instruction, ma);
491 if (ret==0) {
492 regs->pr = regs->pc + 4;
493 regs->pc += SH_PC_12BIT_OFFSET(instruction);
494 }
495 break;
496 }
497 return ret;
498
499 /* handle non-delay-slot instruction */
500 simple:
501 ret = handle_unaligned_ins(instruction, regs, ma);
502 if (ret==0)
503 regs->pc += instruction_size(instruction);
504 return ret;
505 }
506
507 /*
508 * Handle various address error exceptions:
509 * - instruction address error:
510 * misaligned PC
511 * PC >= 0x80000000 in user mode
512 * - data address error (read and write)
513 * misaligned data access
514 * access to >= 0x80000000 is user mode
515 * Unfortuntaly we can't distinguish between instruction address error
516 * and data address errors caused by read accesses.
517 */
518 asmlinkage void do_address_error(struct pt_regs *regs,
519 unsigned long writeaccess,
520 unsigned long address)
521 {
522 unsigned long error_code = 0;
523 mm_segment_t oldfs;
524 siginfo_t info;
525 opcode_t instruction;
526 int tmp;
527
528 /* Intentional ifdef */
529 #ifdef CONFIG_CPU_HAS_SR_RB
530 error_code = lookup_exception_vector();
531 #endif
532
533 oldfs = get_fs();
534
535 if (user_mode(regs)) {
536 int si_code = BUS_ADRERR;
537
538 local_irq_enable();
539
540 /* bad PC is not something we can fix */
541 if (regs->pc & 1) {
542 si_code = BUS_ADRALN;
543 goto uspace_segv;
544 }
545
546 set_fs(USER_DS);
547 if (copy_from_user(&instruction, (void __user *)(regs->pc),
548 sizeof(instruction))) {
549 /* Argh. Fault on the instruction itself.
550 This should never happen non-SMP
551 */
552 set_fs(oldfs);
553 goto uspace_segv;
554 }
555
556 tmp = handle_unaligned_access(instruction, regs,
557 &user_mem_access);
558 set_fs(oldfs);
559
560 if (tmp==0)
561 return; /* sorted */
562 uspace_segv:
563 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
564 "access (PC %lx PR %lx)\n", current->comm, regs->pc,
565 regs->pr);
566
567 info.si_signo = SIGBUS;
568 info.si_errno = 0;
569 info.si_code = si_code;
570 info.si_addr = (void __user *)address;
571 force_sig_info(SIGBUS, &info, current);
572 } else {
573 if (regs->pc & 1)
574 die("unaligned program counter", regs, error_code);
575
576 set_fs(KERNEL_DS);
577 if (copy_from_user(&instruction, (void __user *)(regs->pc),
578 sizeof(instruction))) {
579 /* Argh. Fault on the instruction itself.
580 This should never happen non-SMP
581 */
582 set_fs(oldfs);
583 die("insn faulting in do_address_error", regs, 0);
584 }
585
586 handle_unaligned_access(instruction, regs, &user_mem_access);
587 set_fs(oldfs);
588 }
589 }
590
591 #ifdef CONFIG_SH_DSP
592 /*
593 * SH-DSP support gerg@snapgear.com.
594 */
595 int is_dsp_inst(struct pt_regs *regs)
596 {
597 unsigned short inst = 0;
598
599 /*
600 * Safe guard if DSP mode is already enabled or we're lacking
601 * the DSP altogether.
602 */
603 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
604 return 0;
605
606 get_user(inst, ((unsigned short *) regs->pc));
607
608 inst &= 0xf000;
609
610 /* Check for any type of DSP or support instruction */
611 if ((inst == 0xf000) || (inst == 0x4000))
612 return 1;
613
614 return 0;
615 }
616 #else
617 #define is_dsp_inst(regs) (0)
618 #endif /* CONFIG_SH_DSP */
619
620 #ifdef CONFIG_CPU_SH2A
621 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
622 unsigned long r6, unsigned long r7,
623 struct pt_regs __regs)
624 {
625 siginfo_t info;
626
627 switch (r4) {
628 case TRAP_DIVZERO_ERROR:
629 info.si_code = FPE_INTDIV;
630 break;
631 case TRAP_DIVOVF_ERROR:
632 info.si_code = FPE_INTOVF;
633 break;
634 }
635
636 force_sig_info(SIGFPE, &info, current);
637 }
638 #endif
639
640 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
641 unsigned long r6, unsigned long r7,
642 struct pt_regs __regs)
643 {
644 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
645 unsigned long error_code;
646 struct task_struct *tsk = current;
647
648 #ifdef CONFIG_SH_FPU_EMU
649 unsigned short inst = 0;
650 int err;
651
652 get_user(inst, (unsigned short*)regs->pc);
653
654 err = do_fpu_inst(inst, regs);
655 if (!err) {
656 regs->pc += instruction_size(inst);
657 return;
658 }
659 /* not a FPU inst. */
660 #endif
661
662 #ifdef CONFIG_SH_DSP
663 /* Check if it's a DSP instruction */
664 if (is_dsp_inst(regs)) {
665 /* Enable DSP mode, and restart instruction. */
666 regs->sr |= SR_DSP;
667 return;
668 }
669 #endif
670
671 error_code = lookup_exception_vector();
672
673 local_irq_enable();
674 force_sig(SIGILL, tsk);
675 die_if_no_fixup("reserved instruction", regs, error_code);
676 }
677
678 #ifdef CONFIG_SH_FPU_EMU
679 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
680 {
681 /*
682 * bfs: 8fxx: PC+=d*2+4;
683 * bts: 8dxx: PC+=d*2+4;
684 * bra: axxx: PC+=D*2+4;
685 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
686 * braf:0x23: PC+=Rn*2+4;
687 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
688 * jmp: 4x2b: PC=Rn;
689 * jsr: 4x0b: PC=Rn after PR=PC+4;
690 * rts: 000b: PC=PR;
691 */
692 if (((inst & 0xf000) == 0xb000) || /* bsr */
693 ((inst & 0xf0ff) == 0x0003) || /* bsrf */
694 ((inst & 0xf0ff) == 0x400b)) /* jsr */
695 regs->pr = regs->pc + 4;
696
697 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
698 regs->pc += SH_PC_8BIT_OFFSET(inst);
699 return 0;
700 }
701
702 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
703 regs->pc += SH_PC_12BIT_OFFSET(inst);
704 return 0;
705 }
706
707 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
708 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
709 return 0;
710 }
711
712 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
713 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
714 return 0;
715 }
716
717 if ((inst & 0xffff) == 0x000b) { /* rts */
718 regs->pc = regs->pr;
719 return 0;
720 }
721
722 return 1;
723 }
724 #endif
725
726 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
727 unsigned long r6, unsigned long r7,
728 struct pt_regs __regs)
729 {
730 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
731 unsigned long inst;
732 struct task_struct *tsk = current;
733
734 if (kprobe_handle_illslot(regs->pc) == 0)
735 return;
736
737 #ifdef CONFIG_SH_FPU_EMU
738 get_user(inst, (unsigned short *)regs->pc + 1);
739 if (!do_fpu_inst(inst, regs)) {
740 get_user(inst, (unsigned short *)regs->pc);
741 if (!emulate_branch(inst, regs))
742 return;
743 /* fault in branch.*/
744 }
745 /* not a FPU inst. */
746 #endif
747
748 inst = lookup_exception_vector();
749
750 local_irq_enable();
751 force_sig(SIGILL, tsk);
752 die_if_no_fixup("illegal slot instruction", regs, inst);
753 }
754
755 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
756 unsigned long r6, unsigned long r7,
757 struct pt_regs __regs)
758 {
759 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
760 long ex;
761
762 ex = lookup_exception_vector();
763 die_if_kernel("exception", regs, ex);
764 }
765
766 #if defined(CONFIG_SH_STANDARD_BIOS)
767 void *gdb_vbr_vector;
768
769 static inline void __init gdb_vbr_init(void)
770 {
771 register unsigned long vbr;
772
773 /*
774 * Read the old value of the VBR register to initialise
775 * the vector through which debug and BIOS traps are
776 * delegated by the Linux trap handler.
777 */
778 asm volatile("stc vbr, %0" : "=r" (vbr));
779
780 gdb_vbr_vector = (void *)(vbr + 0x100);
781 printk("Setting GDB trap vector to 0x%08lx\n",
782 (unsigned long)gdb_vbr_vector);
783 }
784 #endif
785
786 void __cpuinit per_cpu_trap_init(void)
787 {
788 extern void *vbr_base;
789
790 #ifdef CONFIG_SH_STANDARD_BIOS
791 if (raw_smp_processor_id() == 0)
792 gdb_vbr_init();
793 #endif
794
795 /* NOTE: The VBR value should be at P1
796 (or P2, virtural "fixed" address space).
797 It's definitely should not in physical address. */
798
799 asm volatile("ldc %0, vbr"
800 : /* no output */
801 : "r" (&vbr_base)
802 : "memory");
803 }
804
805 void *set_exception_table_vec(unsigned int vec, void *handler)
806 {
807 extern void *exception_handling_table[];
808 void *old_handler;
809
810 old_handler = exception_handling_table[vec];
811 exception_handling_table[vec] = handler;
812 return old_handler;
813 }
814
815 void __init trap_init(void)
816 {
817 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
818 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
819
820 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
821 defined(CONFIG_SH_FPU_EMU)
822 /*
823 * For SH-4 lacking an FPU, treat floating point instructions as
824 * reserved. They'll be handled in the math-emu case, or faulted on
825 * otherwise.
826 */
827 set_exception_table_evt(0x800, do_reserved_inst);
828 set_exception_table_evt(0x820, do_illegal_slot_inst);
829 #elif defined(CONFIG_SH_FPU)
830 #ifdef CONFIG_CPU_SUBTYPE_SHX3
831 set_exception_table_evt(0xd80, fpu_state_restore_trap_handler);
832 set_exception_table_evt(0xda0, fpu_state_restore_trap_handler);
833 #else
834 set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
835 set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
836 #endif
837 #endif
838
839 #ifdef CONFIG_CPU_SH2
840 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
841 #endif
842 #ifdef CONFIG_CPU_SH2A
843 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
844 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
845 #ifdef CONFIG_SH_FPU
846 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
847 #endif
848 #endif
849
850 /* Setup VBR for boot cpu */
851 per_cpu_trap_init();
852 }
853
854 void show_trace(struct task_struct *tsk, unsigned long *sp,
855 struct pt_regs *regs)
856 {
857 unsigned long addr;
858
859 if (regs && user_mode(regs))
860 return;
861
862 printk("\nCall trace:\n");
863
864 while (!kstack_end(sp)) {
865 addr = *sp++;
866 if (kernel_text_address(addr))
867 print_ip_sym(addr);
868 }
869
870 printk("\n");
871
872 if (!tsk)
873 tsk = current;
874
875 debug_show_held_locks(tsk);
876 }
877
878 void show_stack(struct task_struct *tsk, unsigned long *sp)
879 {
880 unsigned long stack;
881
882 if (!tsk)
883 tsk = current;
884 if (tsk == current)
885 sp = (unsigned long *)current_stack_pointer;
886 else
887 sp = (unsigned long *)tsk->thread.sp;
888
889 stack = (unsigned long)sp;
890 dump_mem("Stack: ", stack, THREAD_SIZE +
891 (unsigned long)task_stack_page(tsk));
892 show_trace(tsk, sp, NULL);
893 }
894
895 void dump_stack(void)
896 {
897 show_stack(NULL, NULL);
898 }
899 EXPORT_SYMBOL(dump_stack);
Nao low-level kernelspace/userspace library that runs on our robots, Nao-Team HTWK