4 * Copyright (C) 2006 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
14 #include <linux/uio_driver.h>
15 #include <asm/clock.h>
17 static struct resource iic0_resources
[] = {
22 .flags
= IORESOURCE_MEM
,
27 .flags
= IORESOURCE_IRQ
,
31 static struct platform_device iic0_device
= {
32 .name
= "i2c-sh_mobile",
33 .id
= 0, /* "i2c0" clock */
34 .num_resources
= ARRAY_SIZE(iic0_resources
),
35 .resource
= iic0_resources
,
38 static struct resource iic1_resources
[] = {
43 .flags
= IORESOURCE_MEM
,
48 .flags
= IORESOURCE_IRQ
,
52 static struct platform_device iic1_device
= {
53 .name
= "i2c-sh_mobile",
54 .id
= 1, /* "i2c1" clock */
55 .num_resources
= ARRAY_SIZE(iic1_resources
),
56 .resource
= iic1_resources
,
59 static struct uio_info vpu_platform_data
= {
65 static struct resource vpu_resources
[] = {
70 .flags
= IORESOURCE_MEM
,
73 /* place holder for contiguous memory */
77 static struct platform_device vpu_device
= {
78 .name
= "uio_pdrv_genirq",
81 .platform_data
= &vpu_platform_data
,
83 .resource
= vpu_resources
,
84 .num_resources
= ARRAY_SIZE(vpu_resources
),
87 static struct uio_info veu_platform_data
= {
93 static struct resource veu_resources
[] = {
98 .flags
= IORESOURCE_MEM
,
101 /* place holder for contiguous memory */
105 static struct platform_device veu_device
= {
106 .name
= "uio_pdrv_genirq",
109 .platform_data
= &veu_platform_data
,
111 .resource
= veu_resources
,
112 .num_resources
= ARRAY_SIZE(veu_resources
),
115 static struct uio_info jpu_platform_data
= {
121 static struct resource jpu_resources
[] = {
126 .flags
= IORESOURCE_MEM
,
129 /* place holder for contiguous memory */
133 static struct platform_device jpu_device
= {
134 .name
= "uio_pdrv_genirq",
137 .platform_data
= &jpu_platform_data
,
139 .resource
= jpu_resources
,
140 .num_resources
= ARRAY_SIZE(jpu_resources
),
143 static struct plat_sci_port sci_platform_data
[] = {
145 .mapbase
= 0xffe00000,
146 .flags
= UPF_BOOT_AUTOCONF
,
148 .irqs
= { 80, 80, 80, 80 },
150 .mapbase
= 0xffe10000,
151 .flags
= UPF_BOOT_AUTOCONF
,
153 .irqs
= { 81, 81, 81, 81 },
155 .mapbase
= 0xffe20000,
156 .flags
= UPF_BOOT_AUTOCONF
,
158 .irqs
= { 82, 82, 82, 82 },
160 .mapbase
= 0xffe30000,
161 .flags
= UPF_BOOT_AUTOCONF
,
163 .irqs
= { 83, 83, 83, 83 },
169 static struct platform_device sci_device
= {
173 .platform_data
= sci_platform_data
,
177 static struct platform_device
*sh7343_devices
[] __initdata
= {
186 static int __init
sh7343_devices_setup(void)
188 clk_always_enable("uram0"); /* URAM */
189 clk_always_enable("xymem0"); /* XYMEM */
190 clk_always_enable("veu0"); /* VEU */
191 clk_always_enable("vpu0"); /* VPU */
192 clk_always_enable("jpu0"); /* JPU */
194 platform_resource_setup_memory(&vpu_device
, "vpu", 1 << 20);
195 platform_resource_setup_memory(&veu_device
, "veu", 2 << 20);
196 platform_resource_setup_memory(&jpu_device
, "jpu", 2 << 20);
198 return platform_add_devices(sh7343_devices
,
199 ARRAY_SIZE(sh7343_devices
));
201 __initcall(sh7343_devices_setup
);
206 /* interrupt sources */
207 IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
,
208 DMAC0
, DMAC1
, DMAC2
, DMAC3
,
209 VIO_CEUI
, VIO_BEUI
, VIO_VEUI
, VOU
,
210 MFI
, VPU
, TPU
, Z3D4
, USBI0
, USBI1
,
211 MMC_ERR
, MMC_TRAN
, MMC_FSTAT
, MMC_FRDY
,
212 DMAC4
, DMAC5
, DMAC_DADERR
,
214 SCIF
, SCIF1
, SCIF2
, SCIF3
,
216 FLCTL_FLSTEI
, FLCTL_FLENDI
, FLCTL_FLTREQ0I
, FLCTL_FLTREQ1I
,
217 I2C0_ALI
, I2C0_TACKI
, I2C0_WAITI
, I2C0_DTEI
,
218 I2C1_ALI
, I2C1_TACKI
, I2C1_WAITI
, I2C1_DTEI
,
219 SIM_TEI
, SIM_TXI
, SIM_RXI
, SIM_ERI
,
221 SDHI0
, SDHI1
, SDHI2
, SDHI3
,
226 /* interrupt groups */
228 DMAC0123
, VIOVOU
, MMC
, DMAC45
, FLCTL
, I2C0
, I2C1
, SIM
, SDHI
, USB
,
231 static struct intc_vect vectors
[] __initdata
= {
232 INTC_VECT(IRQ0
, 0x600), INTC_VECT(IRQ1
, 0x620),
233 INTC_VECT(IRQ2
, 0x640), INTC_VECT(IRQ3
, 0x660),
234 INTC_VECT(IRQ4
, 0x680), INTC_VECT(IRQ5
, 0x6a0),
235 INTC_VECT(IRQ6
, 0x6c0), INTC_VECT(IRQ7
, 0x6e0),
236 INTC_VECT(I2C1_ALI
, 0x780), INTC_VECT(I2C1_TACKI
, 0x7a0),
237 INTC_VECT(I2C1_WAITI
, 0x7c0), INTC_VECT(I2C1_DTEI
, 0x7e0),
238 INTC_VECT(DMAC0
, 0x800), INTC_VECT(DMAC1
, 0x820),
239 INTC_VECT(DMAC2
, 0x840), INTC_VECT(DMAC3
, 0x860),
240 INTC_VECT(VIO_CEUI
, 0x880), INTC_VECT(VIO_BEUI
, 0x8a0),
241 INTC_VECT(VIO_VEUI
, 0x8c0), INTC_VECT(VOU
, 0x8e0),
242 INTC_VECT(MFI
, 0x900), INTC_VECT(VPU
, 0x980),
243 INTC_VECT(TPU
, 0x9a0), INTC_VECT(Z3D4
, 0x9e0),
244 INTC_VECT(USBI0
, 0xa20), INTC_VECT(USBI1
, 0xa40),
245 INTC_VECT(MMC_ERR
, 0xb00), INTC_VECT(MMC_TRAN
, 0xb20),
246 INTC_VECT(MMC_FSTAT
, 0xb40), INTC_VECT(MMC_FRDY
, 0xb60),
247 INTC_VECT(DMAC4
, 0xb80), INTC_VECT(DMAC5
, 0xba0),
248 INTC_VECT(DMAC_DADERR
, 0xbc0), INTC_VECT(KEYSC
, 0xbe0),
249 INTC_VECT(SCIF
, 0xc00), INTC_VECT(SCIF1
, 0xc20),
250 INTC_VECT(SCIF2
, 0xc40), INTC_VECT(SCIF3
, 0xc60),
251 INTC_VECT(SIOF0
, 0xc80), INTC_VECT(SIOF1
, 0xca0),
252 INTC_VECT(SIO
, 0xd00),
253 INTC_VECT(FLCTL_FLSTEI
, 0xd80), INTC_VECT(FLCTL_FLENDI
, 0xda0),
254 INTC_VECT(FLCTL_FLTREQ0I
, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I
, 0xde0),
255 INTC_VECT(I2C0_ALI
, 0xe00), INTC_VECT(I2C0_TACKI
, 0xe20),
256 INTC_VECT(I2C0_WAITI
, 0xe40), INTC_VECT(I2C0_DTEI
, 0xe60),
257 INTC_VECT(SDHI0
, 0xe80), INTC_VECT(SDHI1
, 0xea0),
258 INTC_VECT(SDHI2
, 0xec0), INTC_VECT(SDHI3
, 0xee0),
259 INTC_VECT(CMT
, 0xf00), INTC_VECT(TSIF
, 0xf20),
260 INTC_VECT(SIU
, 0xf80),
261 INTC_VECT(TMU0
, 0x400), INTC_VECT(TMU1
, 0x420),
262 INTC_VECT(TMU2
, 0x440),
263 INTC_VECT(JPU
, 0x560), INTC_VECT(LCDC
, 0x580),
266 static struct intc_group groups
[] __initdata
= {
267 INTC_GROUP(DMAC0123
, DMAC0
, DMAC1
, DMAC2
, DMAC3
),
268 INTC_GROUP(VIOVOU
, VIO_CEUI
, VIO_BEUI
, VIO_VEUI
, VOU
),
269 INTC_GROUP(MMC
, MMC_FRDY
, MMC_FSTAT
, MMC_TRAN
, MMC_ERR
),
270 INTC_GROUP(DMAC45
, DMAC4
, DMAC5
, DMAC_DADERR
),
271 INTC_GROUP(FLCTL
, FLCTL_FLSTEI
, FLCTL_FLENDI
,
272 FLCTL_FLTREQ0I
, FLCTL_FLTREQ1I
),
273 INTC_GROUP(I2C0
, I2C0_ALI
, I2C0_TACKI
, I2C0_WAITI
, I2C0_DTEI
),
274 INTC_GROUP(I2C1
, I2C1_ALI
, I2C1_TACKI
, I2C1_WAITI
, I2C1_DTEI
),
275 INTC_GROUP(SIM
, SIM_TEI
, SIM_TXI
, SIM_RXI
, SIM_ERI
),
276 INTC_GROUP(SDHI
, SDHI0
, SDHI1
, SDHI2
, SDHI3
),
277 INTC_GROUP(USB
, USBI0
, USBI1
),
280 static struct intc_mask_reg mask_registers
[] __initdata
= {
281 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
282 { VOU
, VIO_VEUI
, VIO_BEUI
, VIO_CEUI
, DMAC3
, DMAC2
, DMAC1
, DMAC0
} },
283 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
284 { 0, 0, 0, VPU
, 0, 0, 0, MFI
} },
285 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
286 { SIM_TEI
, SIM_TXI
, SIM_RXI
, SIM_ERI
, 0, 0, 0, IRDA
} },
287 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
288 { 0, TMU2
, TMU1
, TMU0
, JPU
, 0, 0, LCDC
} },
289 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
290 { KEYSC
, DMAC_DADERR
, DMAC5
, DMAC4
, SCIF3
, SCIF2
, SCIF1
, SCIF
} },
291 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
292 { 0, 0, 0, SIO
, Z3D4
, 0, SIOF1
, SIOF0
} },
293 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
294 { I2C0_DTEI
, I2C0_WAITI
, I2C0_TACKI
, I2C0_ALI
,
295 FLCTL_FLTREQ1I
, FLCTL_FLTREQ0I
, FLCTL_FLENDI
, FLCTL_FLSTEI
} },
296 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
297 { SDHI3
, SDHI2
, SDHI1
, SDHI0
, 0, 0, 0, SIU
} },
298 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
299 { 0, 0, 0, CMT
, 0, USBI1
, USBI0
} },
300 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
301 { MMC_FRDY
, MMC_FSTAT
, MMC_TRAN
, MMC_ERR
} },
302 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
303 { I2C1_DTEI
, I2C1_WAITI
, I2C1_TACKI
, I2C1_ALI
, TPU
, 0, 0, TSIF
} },
304 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
305 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
308 static struct intc_prio_reg prio_registers
[] __initdata
= {
309 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0
, TMU1
, TMU2
} },
310 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU
, LCDC
, SIM
} },
311 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123
, VIOVOU
, MFI
, VPU
} },
312 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC
, DMAC45
, USB
, CMT
} },
313 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF
, SCIF1
, SCIF2
, SCIF3
} },
314 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0
, SIOF1
, FLCTL
, I2C0
} },
315 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO
, 0, TSIF
, I2C1
} },
316 { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4
, 0, SIU
} },
317 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC
, 0, SDHI
} },
318 { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU
} },
319 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
320 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
323 static struct intc_sense_reg sense_registers
[] __initdata
= {
324 { 0xa414001c, 16, 2, /* ICR1 */
325 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
328 static struct intc_mask_reg ack_registers
[] __initdata
= {
329 { 0xa4140024, 0, 8, /* INTREQ00 */
330 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
333 static DECLARE_INTC_DESC_ACK(intc_desc
, "sh7343", vectors
, groups
,
334 mask_registers
, prio_registers
, sense_registers
,
337 void __init
plat_irq_setup(void)
339 register_intc_controller(&intc_desc
);