kernel/2.6.29.6-aldebaran-rt/arch/powerpc/sysdev/bestcomm/bcom_fec_rx_task.c

   1 /*
   2  * Bestcomm FEC RX task microcode
   3  *
   4  * Copyright (c) 2004 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation.
   9  *
  10  * Automatically created based on BestCommAPI-2.2/code_dma/image_rtos1/dma_image.hex
  11  * on Tue Mar 22 11:19:38 2005 GMT
  12  */
  13
  14 #include <asm/types.h>
  15
  16 /*
  17  * The header consists of the following fields:
  18  *      u32     magic;
  19  *      u8      desc_size;
  20  *      u8      var_size;
  21  *      u8      inc_size;
  22  *      u8      first_var;
  23  *      u8      reserved[8];
  24  *
  25  * The size fields contain the number of 32-bit words.
  26  */
  27
  28 u32 bcom_fec_rx_task[] = {
  29         /* header */
  30         0x4243544b,
  31         0x18060709,
  32         0x00000000,
  33         0x00000000,
  34
  35         /* Task descriptors */
  36         0x808220e3, /* LCD: idx0 = var1, idx1 = var4; idx1 <= var3; idx0 += inc4, idx1 += inc3 */
  37         0x10601010, /*   DRD1A: var4 = var2; FN=0 MORE init=3 WS=0 RS=0 */
  38         0xb8800264, /*   LCD: idx2 = *idx1, idx3 = var0; idx2 < var9; idx2 += inc4, idx3 += inc4 */
  39         0x10001308, /*     DRD1A: var4 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
  40         0x60140002, /*     DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=2 RS=2 */
  41         0x0cccfcca, /*     DRD2B1: *idx3 = EU3(); EU3(*idx3,var10)  */
  42         0x80004000, /*   LCDEXT: idx2 = 0x00000000; ; */
  43         0xb8c58029, /*   LCD: idx3 = *(idx1 + var00000015); idx3 once var0; idx3 += inc5 */
  44         0x60000002, /*     DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=0 RS=0 */
  45         0x088cf8cc, /*     DRD2B1: idx2 = EU3(); EU3(idx3,var12)  */
  46         0x991982f2, /*   LCD: idx2 = idx2, idx3 = idx3; idx2 > var11; idx2 += inc6, idx3 += inc2 */
  47         0x006acf80, /*     DRD1A: *idx3 = *idx0; FN=0 init=3 WS=1 RS=1 */
  48         0x80004000, /*   LCDEXT: idx2 = 0x00000000; ; */
  49         0x9999802d, /*   LCD: idx3 = idx3; idx3 once var0; idx3 += inc5 */
  50         0x70000002, /*     DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
  51         0x034cfc4e, /*     DRD2B1: var13 = EU3(); EU3(*idx1,var14)  */
  52         0x00008868, /*     DRD1A: idx2 = var13; FN=0 init=0 WS=0 RS=0 */
  53         0x99198341, /*   LCD: idx2 = idx2, idx3 = idx3; idx2 > var13; idx2 += inc0, idx3 += inc1 */
  54         0x007ecf80, /*     DRD1A: *idx3 = *idx0; FN=0 init=3 WS=3 RS=3 */
  55         0x99198272, /*   LCD: idx2 = idx2, idx3 = idx3; idx2 > var9; idx2 += inc6, idx3 += inc2 */
  56         0x046acf80, /*     DRD1A: *idx3 = *idx0; FN=0 INT init=3 WS=1 RS=1 */
  57         0x9819002d, /*   LCD: idx2 = idx0; idx2 once var0; idx2 += inc5 */
  58         0x0060c790, /*     DRD1A: *idx1 = *idx2; FN=0 init=3 WS=0 RS=0 */
  59         0x000001f8, /*   NOP */
  60
  61         /* VAR[9]-VAR[14] */
  62         0x40000000,
  63         0x7fff7fff,
  64         0x00000000,
  65         0x00000003,
  66         0x40000008,
  67         0x43ffffff,
  68
  69         /* INC[0]-INC[6] */
  70         0x40000000,
  71         0xe0000000,
  72         0xe0000000,
  73         0xa0000008,
  74         0x20000000,
  75         0x00000000,
  76         0x4000ffff,
  77 };
  78