kernel/2.6.29.6-aldebaran-rt/arch/powerpc/platforms/8xx/m8xx_setup.c

   1 /*
   2  *  Copyright (C) 1995  Linus Torvalds
   3  *  Adapted from 'alpha' version by Gary Thomas
   4  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   5  *  Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
   6  *  Further modified for generic 8xx by Dan.
   7  */
   8
   9 /*
  10  * bootup setup stuff..
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/slab.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/init.h>
  17 #include <linux/time.h>
  18 #include <linux/rtc.h>
  19 #include <linux/fsl_devices.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/mpc8xx.h>
  23 #include <asm/8xx_immap.h>
  24 #include <asm/prom.h>
  25 #include <asm/fs_pd.h>
  26 #include <mm/mmu_decl.h>
  27
  28 #include <sysdev/mpc8xx_pic.h>
  29
  30 #include "mpc8xx.h"
  31
  32 struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
  33
  34 extern int cpm_pic_init(void);
  35 extern int cpm_get_irq(void);
  36
  37 /* A place holder for time base interrupts, if they are ever enabled. */
  38 static irqreturn_t timebase_interrupt(int irq, void *dev)
  39 {
  40         printk ("timebase_interrupt()\n");
  41
  42         return IRQ_HANDLED;
  43 }
  44
  45 static struct irqaction tbint_irqaction = {
  46         .handler = timebase_interrupt,
  47         .mask = CPU_MASK_NONE,
  48         .name = "tbint",
  49 };
  50
  51 /* per-board overridable init_internal_rtc() function. */
  52 void __init __attribute__ ((weak))
  53 init_internal_rtc(void)
  54 {
  55         sit8xx_t __iomem *sys_tmr = immr_map(im_sit);
  56
  57         /* Disable the RTC one second and alarm interrupts. */
  58         clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
  59
  60         /* Enable the RTC */
  61         setbits16(&sys_tmr->sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
  62         immr_unmap(sys_tmr);
  63 }
  64
  65 static int __init get_freq(char *name, unsigned long *val)
  66 {
  67         struct device_node *cpu;
  68         const unsigned int *fp;
  69         int found = 0;
  70
  71         /* The cpu node should have timebase and clock frequency properties */
  72         cpu = of_find_node_by_type(NULL, "cpu");
  73
  74         if (cpu) {
  75                 fp = of_get_property(cpu, name, NULL);
  76                 if (fp) {
  77                         found = 1;
  78                         *val = *fp;
  79                 }
  80
  81                 of_node_put(cpu);
  82         }
  83
  84         return found;
  85 }
  86
  87 /* The decrementer counts at the system (internal) clock frequency divided by
  88  * sixteen, or external oscillator divided by four.  We force the processor
  89  * to use system clock divided by sixteen.
  90  */
  91 void __init mpc8xx_calibrate_decr(void)
  92 {
  93         struct device_node *cpu;
  94         cark8xx_t __iomem *clk_r1;
  95         car8xx_t __iomem *clk_r2;
  96         sitk8xx_t __iomem *sys_tmr1;
  97         sit8xx_t __iomem *sys_tmr2;
  98         int irq, virq;
  99
 100         clk_r1 = immr_map(im_clkrstk);
 101
 102         /* Unlock the SCCR. */
 103         out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
 104         out_be32(&clk_r1->cark_sccrk, KAPWR_KEY);
 105         immr_unmap(clk_r1);
 106
 107         /* Force all 8xx processors to use divide by 16 processor clock. */
 108         clk_r2 = immr_map(im_clkrst);
 109         setbits32(&clk_r2->car_sccr, 0x02000000);
 110         immr_unmap(clk_r2);
 111
 112         /* Processor frequency is MHz.
 113          */
 114         ppc_proc_freq = 50000000;
 115         if (!get_freq("clock-frequency", &ppc_proc_freq))
 116                 printk(KERN_ERR "WARNING: Estimating processor frequency "
 117                                 "(not found)\n");
 118
 119         ppc_tb_freq = ppc_proc_freq / 16;
 120         printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);
 121
 122         /* Perform some more timer/timebase initialization.  This used
 123          * to be done elsewhere, but other changes caused it to get
 124          * called more than once....that is a bad thing.
 125          *
 126          * First, unlock all of the registers we are going to modify.
 127          * To protect them from corruption during power down, registers
 128          * that are maintained by keep alive power are "locked".  To
 129          * modify these registers we have to write the key value to
 130          * the key location associated with the register.
 131          * Some boards power up with these unlocked, while others
 132          * are locked.  Writing anything (including the unlock code?)
 133          * to the unlocked registers will lock them again.  So, here
 134          * we guarantee the registers are locked, then we unlock them
 135          * for our use.
 136          */
 137         sys_tmr1 = immr_map(im_sitk);
 138         out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);
 139         out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);
 140         out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
 141         out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY);
 142         out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY);
 143         out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY);
 144         immr_unmap(sys_tmr1);
 145
 146         init_internal_rtc();
 147
 148         /* Enabling the decrementer also enables the timebase interrupts
 149          * (or from the other point of view, to get decrementer interrupts
 150          * we have to enable the timebase).  The decrementer interrupt
 151          * is wired into the vector table, nothing to do here for that.
 152          */
 153         cpu = of_find_node_by_type(NULL, "cpu");
 154         virq= irq_of_parse_and_map(cpu, 0);
 155         irq = irq_map[virq].hwirq;
 156
 157         sys_tmr2 = immr_map(im_sit);
 158         out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
 159                                         (TBSCR_TBF | TBSCR_TBE));
 160         immr_unmap(sys_tmr2);
 161
 162         if (setup_irq(virq, &tbint_irqaction))
 163                 panic("Could not allocate timer IRQ!");
 164 }
 165
 166 /* The RTC on the MPC8xx is an internal register.
 167  * We want to protect this during power down, so we need to unlock,
 168  * modify, and re-lock.
 169  */
 170
 171 int mpc8xx_set_rtc_time(struct rtc_time *tm)
 172 {
 173         sitk8xx_t __iomem *sys_tmr1;
 174         sit8xx_t __iomem *sys_tmr2;
 175         int time;
 176
 177         sys_tmr1 = immr_map(im_sitk);
 178         sys_tmr2 = immr_map(im_sit);
 179         time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday,
 180                       tm->tm_hour, tm->tm_min, tm->tm_sec);
 181
 182         out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY);
 183         out_be32(&sys_tmr2->sit_rtc, time);
 184         out_be32(&sys_tmr1->sitk_rtck, ~KAPWR_KEY);
 185
 186         immr_unmap(sys_tmr2);
 187         immr_unmap(sys_tmr1);
 188         return 0;
 189 }
 190
 191 void mpc8xx_get_rtc_time(struct rtc_time *tm)
 192 {
 193         unsigned long data;
 194         sit8xx_t __iomem *sys_tmr = immr_map(im_sit);
 195
 196         /* Get time from the RTC. */
 197         data = in_be32(&sys_tmr->sit_rtc);
 198         to_tm(data, tm);
 199         tm->tm_year -= 1900;
 200         tm->tm_mon -= 1;
 201         immr_unmap(sys_tmr);
 202         return;
 203 }
 204
 205 void mpc8xx_restart(char *cmd)
 206 {
 207         car8xx_t __iomem *clk_r = immr_map(im_clkrst);
 208
 209
 210         local_irq_disable();
 211
 212         setbits32(&clk_r->car_plprcr, 0x00000080);
 213         /* Clear the ME bit in MSR to cause checkstop on machine check
 214         */
 215         mtmsr(mfmsr() & ~0x1000);
 216
 217         in_8(&clk_r->res[0]);
 218         panic("Restart failed\n");
 219 }
 220
 221 static void cpm_cascade(unsigned int irq, struct irq_desc *desc)
 222 {
 223         int cascade_irq;
 224
 225         if ((cascade_irq = cpm_get_irq()) >= 0) {
 226                 struct irq_desc *cdesc = irq_desc + cascade_irq;
 227
 228                 generic_handle_irq(cascade_irq);
 229                 cdesc->chip->eoi(cascade_irq);
 230         }
 231         desc->chip->eoi(irq);
 232 }
 233
 234 /* Initialize the internal interrupt controllers.  The number of
 235  * interrupts supported can vary with the processor type, and the
 236  * 82xx family can have up to 64.
 237  * External interrupts can be either edge or level triggered, and
 238  * need to be initialized by the appropriate driver.
 239  */
 240 void __init mpc8xx_pics_init(void)
 241 {
 242         int irq;
 243
 244         if (mpc8xx_pic_init()) {
 245                 printk(KERN_ERR "Failed interrupt 8xx controller  initialization\n");
 246                 return;
 247         }
 248
 249         irq = cpm_pic_init();
 250         if (irq != NO_IRQ)
 251                 set_irq_chained_handler(irq, cpm_cascade);
 252 }