kernel/2.6.29.6-aldebaran-rt/arch/powerpc/oprofile/op_model_power4.c

   1 /*
   2  * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
   3  * Added mmcra[slot] support:
   4  * Copyright (C) 2006-2007 Will Schmidt <willschm@us.ibm.com>, IBM
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/oprofile.h>
  13 #include <linux/init.h>
  14 #include <linux/smp.h>
  15 #include <asm/firmware.h>
  16 #include <asm/ptrace.h>
  17 #include <asm/system.h>
  18 #include <asm/processor.h>
  19 #include <asm/cputable.h>
  20 #include <asm/rtas.h>
  21 #include <asm/oprofile_impl.h>
  22 #include <asm/reg.h>
  23
  24 #define dbg(args...)
  25
  26 static unsigned long reset_value[OP_MAX_COUNTER];
  27
  28 static int oprofile_running;
  29
  30 /* mmcr values are set in power4_reg_setup, used in power4_cpu_setup */
  31 static u32 mmcr0_val;
  32 static u64 mmcr1_val;
  33 static u64 mmcra_val;
  34
  35 static int power4_reg_setup(struct op_counter_config *ctr,
  36                              struct op_system_config *sys,
  37                              int num_ctrs)
  38 {
  39         int i;
  40
  41         /*
  42          * The performance counter event settings are given in the mmcr0,
  43          * mmcr1 and mmcra values passed from the user in the
  44          * op_system_config structure (sys variable).
  45          */
  46         mmcr0_val = sys->mmcr0;
  47         mmcr1_val = sys->mmcr1;
  48         mmcra_val = sys->mmcra;
  49
  50         for (i = 0; i < cur_cpu_spec->num_pmcs; ++i)
  51                 reset_value[i] = 0x80000000UL - ctr[i].count;
  52
  53         /* setup user and kernel profiling */
  54         if (sys->enable_kernel)
  55                 mmcr0_val &= ~MMCR0_KERNEL_DISABLE;
  56         else
  57                 mmcr0_val |= MMCR0_KERNEL_DISABLE;
  58
  59         if (sys->enable_user)
  60                 mmcr0_val &= ~MMCR0_PROBLEM_DISABLE;
  61         else
  62                 mmcr0_val |= MMCR0_PROBLEM_DISABLE;
  63
  64         return 0;
  65 }
  66
  67 extern void ppc_enable_pmcs(void);
  68
  69 /*
  70  * Older CPUs require the MMCRA sample bit to be always set, but newer
  71  * CPUs only want it set for some groups. Eventually we will remove all
  72  * knowledge of this bit in the kernel, oprofile userspace should be
  73  * setting it when required.
  74  *
  75  * In order to keep current installations working we force the bit for
  76  * those older CPUs. Once everyone has updated their oprofile userspace we
  77  * can remove this hack.
  78  */
  79 static inline int mmcra_must_set_sample(void)
  80 {
  81         if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p) ||
  82             __is_processor(PV_970) || __is_processor(PV_970FX) ||
  83             __is_processor(PV_970MP) || __is_processor(PV_970GX))
  84                 return 1;
  85
  86         return 0;
  87 }
  88
  89 static int power4_cpu_setup(struct op_counter_config *ctr)
  90 {
  91         unsigned int mmcr0 = mmcr0_val;
  92         unsigned long mmcra = mmcra_val;
  93
  94         ppc_enable_pmcs();
  95
  96         /* set the freeze bit */
  97         mmcr0 |= MMCR0_FC;
  98         mtspr(SPRN_MMCR0, mmcr0);
  99
 100         mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
 101         mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE;
 102         mtspr(SPRN_MMCR0, mmcr0);
 103
 104         mtspr(SPRN_MMCR1, mmcr1_val);
 105
 106         if (mmcra_must_set_sample())
 107                 mmcra |= MMCRA_SAMPLE_ENABLE;
 108         mtspr(SPRN_MMCRA, mmcra);
 109
 110         dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
 111             mfspr(SPRN_MMCR0));
 112         dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
 113             mfspr(SPRN_MMCR1));
 114         dbg("setup on cpu %d, mmcra %lx\n", smp_processor_id(),
 115             mfspr(SPRN_MMCRA));
 116
 117         return 0;
 118 }
 119
 120 static int power4_start(struct op_counter_config *ctr)
 121 {
 122         int i;
 123         unsigned int mmcr0;
 124
 125         /* set the PMM bit (see comment below) */
 126         mtmsrd(mfmsr() | MSR_PMM);
 127
 128         for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
 129                 if (ctr[i].enabled) {
 130                         classic_ctr_write(i, reset_value[i]);
 131                 } else {
 132                         classic_ctr_write(i, 0);
 133                 }
 134         }
 135
 136         mmcr0 = mfspr(SPRN_MMCR0);
 137
 138         /*
 139          * We must clear the PMAO bit on some (GQ) chips. Just do it
 140          * all the time
 141          */
 142         mmcr0 &= ~MMCR0_PMAO;
 143
 144         /*
 145          * now clear the freeze bit, counting will not start until we
 146          * rfid from this excetion, because only at that point will
 147          * the PMM bit be cleared
 148          */
 149         mmcr0 &= ~MMCR0_FC;
 150         mtspr(SPRN_MMCR0, mmcr0);
 151
 152         oprofile_running = 1;
 153
 154         dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
 155         return 0;
 156 }
 157
 158 static void power4_stop(void)
 159 {
 160         unsigned int mmcr0;
 161
 162         /* freeze counters */
 163         mmcr0 = mfspr(SPRN_MMCR0);
 164         mmcr0 |= MMCR0_FC;
 165         mtspr(SPRN_MMCR0, mmcr0);
 166
 167         oprofile_running = 0;
 168
 169         dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
 170
 171         mb();
 172 }
 173
 174 /* Fake functions used by canonicalize_pc */
 175 static void __used hypervisor_bucket(void)
 176 {
 177 }
 178
 179 static void __used rtas_bucket(void)
 180 {
 181 }
 182
 183 static void __used kernel_unknown_bucket(void)
 184 {
 185 }
 186
 187 /*
 188  * On GQ and newer the MMCRA stores the HV and PR bits at the time
 189  * the SIAR was sampled. We use that to work out if the SIAR was sampled in
 190  * the hypervisor, our exception vectors or RTAS.
 191  * If the MMCRA_SAMPLE_ENABLE bit is set, we can use the MMCRA[slot] bits
 192  * to more accurately identify the address of the sampled instruction. The
 193  * mmcra[slot] bits represent the slot number of a sampled instruction
 194  * within an instruction group.  The slot will contain a value between 1
 195  * and 5 if MMCRA_SAMPLE_ENABLE is set, otherwise 0.
 196  */
 197 static unsigned long get_pc(struct pt_regs *regs)
 198 {
 199         unsigned long pc = mfspr(SPRN_SIAR);
 200         unsigned long mmcra;
 201         unsigned long slot;
 202
 203         /* Cant do much about it */
 204         if (!cur_cpu_spec->oprofile_mmcra_sihv)
 205                 return pc;
 206
 207         mmcra = mfspr(SPRN_MMCRA);
 208
 209         if (mmcra & MMCRA_SAMPLE_ENABLE) {
 210                 slot = ((mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT);
 211                 if (slot > 1)
 212                         pc += 4 * (slot - 1);
 213         }
 214
 215         /* Were we in the hypervisor? */
 216         if (firmware_has_feature(FW_FEATURE_LPAR) &&
 217             (mmcra & cur_cpu_spec->oprofile_mmcra_sihv))
 218                 /* function descriptor madness */
 219                 return *((unsigned long *)hypervisor_bucket);
 220
 221         /* We were in userspace, nothing to do */
 222         if (mmcra & cur_cpu_spec->oprofile_mmcra_sipr)
 223                 return pc;
 224
 225 #ifdef CONFIG_PPC_RTAS
 226         /* Were we in RTAS? */
 227         if (pc >= rtas.base && pc < (rtas.base + rtas.size))
 228                 /* function descriptor madness */
 229                 return *((unsigned long *)rtas_bucket);
 230 #endif
 231
 232         /* Were we in our exception vectors or SLB real mode miss handler? */
 233         if (pc < 0x1000000UL)
 234                 return (unsigned long)__va(pc);
 235
 236         /* Not sure where we were */
 237         if (!is_kernel_addr(pc))
 238                 /* function descriptor madness */
 239                 return *((unsigned long *)kernel_unknown_bucket);
 240
 241         return pc;
 242 }
 243
 244 static int get_kernel(unsigned long pc, unsigned long mmcra)
 245 {
 246         int is_kernel;
 247
 248         if (!cur_cpu_spec->oprofile_mmcra_sihv) {
 249                 is_kernel = is_kernel_addr(pc);
 250         } else {
 251                 is_kernel = ((mmcra & cur_cpu_spec->oprofile_mmcra_sipr) == 0);
 252         }
 253
 254         return is_kernel;
 255 }
 256
 257 static void power4_handle_interrupt(struct pt_regs *regs,
 258                                     struct op_counter_config *ctr)
 259 {
 260         unsigned long pc;
 261         int is_kernel;
 262         int val;
 263         int i;
 264         unsigned int mmcr0;
 265         unsigned long mmcra;
 266
 267         mmcra = mfspr(SPRN_MMCRA);
 268
 269         pc = get_pc(regs);
 270         is_kernel = get_kernel(pc, mmcra);
 271
 272         /* set the PMM bit (see comment below) */
 273         mtmsrd(mfmsr() | MSR_PMM);
 274
 275         for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
 276                 val = classic_ctr_read(i);
 277                 if (val < 0) {
 278                         if (oprofile_running && ctr[i].enabled) {
 279                                 oprofile_add_ext_sample(pc, regs, i, is_kernel);
 280                                 classic_ctr_write(i, reset_value[i]);
 281                         } else {
 282                                 classic_ctr_write(i, 0);
 283                         }
 284                 }
 285         }
 286
 287         mmcr0 = mfspr(SPRN_MMCR0);
 288
 289         /* reset the perfmon trigger */
 290         mmcr0 |= MMCR0_PMXE;
 291
 292         /*
 293          * We must clear the PMAO bit on some (GQ) chips. Just do it
 294          * all the time
 295          */
 296         mmcr0 &= ~MMCR0_PMAO;
 297
 298         /* Clear the appropriate bits in the MMCRA */
 299         mmcra &= ~cur_cpu_spec->oprofile_mmcra_clear;
 300         mtspr(SPRN_MMCRA, mmcra);
 301
 302         /*
 303          * now clear the freeze bit, counting will not start until we
 304          * rfid from this exception, because only at that point will
 305          * the PMM bit be cleared
 306          */
 307         mmcr0 &= ~MMCR0_FC;
 308         mtspr(SPRN_MMCR0, mmcr0);
 309 }
 310
 311 struct op_powerpc_model op_model_power4 = {
 312         .reg_setup              = power4_reg_setup,
 313         .cpu_setup              = power4_cpu_setup,
 314         .start                  = power4_start,
 315         .stop                   = power4_stop,
 316         .handle_interrupt       = power4_handle_interrupt,
 317 };