kernel/2.6.29.6-aldebaran-rt/arch/mips/include/asm/octeon/cvmx-l2c.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2008 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 /*
  29  *
  30  * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
  31  * facilities.
  32  */
  33
  34 #ifndef __CVMX_L2C_H__
  35 #define __CVMX_L2C_H__
  36
  37 /* Deprecated macro, use function */
  38 #define CVMX_L2_ASSOC     cvmx_l2c_get_num_assoc()
  39
  40 /* Deprecated macro, use function */
  41 #define CVMX_L2_SET_BITS  cvmx_l2c_get_set_bits()
  42
  43 /* Deprecated macro, use function */
  44 #define CVMX_L2_SETS      cvmx_l2c_get_num_sets()
  45
  46 #define CVMX_L2C_IDX_ADDR_SHIFT 7  /* based on 128 byte cache line size */
  47 #define CVMX_L2C_IDX_MASK       (cvmx_l2c_get_num_sets() - 1)
  48
  49 /* Defines for index aliasing computations */
  50 #define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT \
  51         (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
  52
  53 #define CVMX_L2C_ALIAS_MASK \
  54         (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
  55
  56 union cvmx_l2c_tag {
  57         uint64_t u64;
  58         struct {
  59                 uint64_t reserved:28;
  60                 uint64_t V:1;   /* Line valid */
  61                 uint64_t D:1;   /* Line dirty */
  62                 uint64_t L:1;   /* Line locked */
  63                 uint64_t U:1;   /* Use, LRU eviction */
  64                 uint64_t addr:32;       /* Phys mem (not all bits valid) */
  65         } s;
  66 };
  67
  68   /* L2C Performance Counter events. */
  69 enum cvmx_l2c_event {
  70         CVMX_L2C_EVENT_CYCLES = 0,
  71         CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
  72         CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
  73         CVMX_L2C_EVENT_DATA_MISS = 3,
  74         CVMX_L2C_EVENT_DATA_HIT = 4,
  75         CVMX_L2C_EVENT_MISS = 5,
  76         CVMX_L2C_EVENT_HIT = 6,
  77         CVMX_L2C_EVENT_VICTIM_HIT = 7,
  78         CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
  79         CVMX_L2C_EVENT_TAG_PROBE = 9,
  80         CVMX_L2C_EVENT_TAG_UPDATE = 10,
  81         CVMX_L2C_EVENT_TAG_COMPLETE = 11,
  82         CVMX_L2C_EVENT_TAG_DIRTY = 12,
  83         CVMX_L2C_EVENT_DATA_STORE_NOP = 13,
  84         CVMX_L2C_EVENT_DATA_STORE_READ = 14,
  85         CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
  86         CVMX_L2C_EVENT_FILL_DATA_VALID = 16,
  87         CVMX_L2C_EVENT_WRITE_REQUEST = 17,
  88         CVMX_L2C_EVENT_READ_REQUEST = 18,
  89         CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
  90         CVMX_L2C_EVENT_XMC_NOP = 20,
  91         CVMX_L2C_EVENT_XMC_LDT = 21,
  92         CVMX_L2C_EVENT_XMC_LDI = 22,
  93         CVMX_L2C_EVENT_XMC_LDD = 23,
  94         CVMX_L2C_EVENT_XMC_STF = 24,
  95         CVMX_L2C_EVENT_XMC_STT = 25,
  96         CVMX_L2C_EVENT_XMC_STP = 26,
  97         CVMX_L2C_EVENT_XMC_STC = 27,
  98         CVMX_L2C_EVENT_XMC_DWB = 28,
  99         CVMX_L2C_EVENT_XMC_PL2 = 29,
 100         CVMX_L2C_EVENT_XMC_PSL1 = 30,
 101         CVMX_L2C_EVENT_XMC_IOBLD = 31,
 102         CVMX_L2C_EVENT_XMC_IOBST = 32,
 103         CVMX_L2C_EVENT_XMC_IOBDMA = 33,
 104         CVMX_L2C_EVENT_XMC_IOBRSP = 34,
 105         CVMX_L2C_EVENT_XMC_BUS_VALID = 35,
 106         CVMX_L2C_EVENT_XMC_MEM_DATA = 36,
 107         CVMX_L2C_EVENT_XMC_REFL_DATA = 37,
 108         CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38,
 109         CVMX_L2C_EVENT_RSC_NOP = 39,
 110         CVMX_L2C_EVENT_RSC_STDN = 40,
 111         CVMX_L2C_EVENT_RSC_FILL = 41,
 112         CVMX_L2C_EVENT_RSC_REFL = 42,
 113         CVMX_L2C_EVENT_RSC_STIN = 43,
 114         CVMX_L2C_EVENT_RSC_SCIN = 44,
 115         CVMX_L2C_EVENT_RSC_SCFL = 45,
 116         CVMX_L2C_EVENT_RSC_SCDN = 46,
 117         CVMX_L2C_EVENT_RSC_DATA_VALID = 47,
 118         CVMX_L2C_EVENT_RSC_VALID_FILL = 48,
 119         CVMX_L2C_EVENT_RSC_VALID_STRSP = 49,
 120         CVMX_L2C_EVENT_RSC_VALID_REFL = 50,
 121         CVMX_L2C_EVENT_LRF_REQ = 51,
 122         CVMX_L2C_EVENT_DT_RD_ALLOC = 52,
 123         CVMX_L2C_EVENT_DT_WR_INVAL = 53
 124 };
 125
 126 /**
 127  * Configure one of the four L2 Cache performance counters to capture event
 128  * occurences.
 129  *
 130  * @counter:        The counter to configure. Range 0..3.
 131  * @event:          The type of L2 Cache event occurrence to count.
 132  * @clear_on_read:  When asserted, any read of the performance counter
 133  *                       clears the counter.
 134  *
 135  * The routine does not clear the counter.
 136  */
 137 void cvmx_l2c_config_perf(uint32_t counter,
 138                           enum cvmx_l2c_event event, uint32_t clear_on_read);
 139 /**
 140  * Read the given L2 Cache performance counter. The counter must be configured
 141  * before reading, but this routine does not enforce this requirement.
 142  *
 143  * @counter:  The counter to configure. Range 0..3.
 144  *
 145  * Returns The current counter value.
 146  */
 147 uint64_t cvmx_l2c_read_perf(uint32_t counter);
 148
 149 /**
 150  * Return the L2 Cache way partitioning for a given core.
 151  *
 152  * @core:  The core processor of interest.
 153  *
 154  * Returns    The mask specifying the partitioning. 0 bits in mask indicates
 155  *              the cache 'ways' that a core can evict from.
 156  *            -1 on error
 157  */
 158 int cvmx_l2c_get_core_way_partition(uint32_t core);
 159
 160 /**
 161  * Partitions the L2 cache for a core
 162  *
 163  * @core:  The core that the partitioning applies to.
 164  *
 165  * @mask: The partitioning of the ways expressed as a binary mask. A 0
 166  *        bit allows the core to evict cache lines from a way, while a
 167  *        1 bit blocks the core from evicting any lines from that
 168  *        way. There must be at least one allowed way (0 bit) in the
 169  *        mask.
 170  *
 171  * If any ways are blocked for all cores and the HW blocks, then those
 172  * ways will never have any cache lines evicted from them.  All cores
 173  * and the hardware blocks are free to read from all ways regardless
 174  * of the partitioning.
 175  */
 176 int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
 177
 178 /**
 179  * Return the L2 Cache way partitioning for the hw blocks.
 180  *
 181  * Returns    The mask specifying the reserved way. 0 bits in mask indicates
 182  *              the cache 'ways' that a core can evict from.
 183  *            -1 on error
 184  */
 185 int cvmx_l2c_get_hw_way_partition(void);
 186
 187 /**
 188  * Partitions the L2 cache for the hardware blocks.
 189  *
 190  * @mask: The partitioning of the ways expressed as a binary mask. A 0
 191  *        bit allows the core to evict cache lines from a way, while a
 192  *        1 bit blocks the core from evicting any lines from that
 193  *        way. There must be at least one allowed way (0 bit) in the
 194  *        mask.
 195  *
 196  * If any ways are blocked for all cores and the HW blocks, then those
 197  * ways will never have any cache lines evicted from them.  All cores
 198  * and the hardware blocks are free to read from all ways regardless
 199  * of the partitioning.
 200  */
 201 int cvmx_l2c_set_hw_way_partition(uint32_t mask);
 202
 203 /**
 204  * Locks a line in the L2 cache at the specified physical address
 205  *
 206  * @addr:   physical address of line to lock
 207  *
 208  * Returns 0 on success,
 209  *         1 if line not locked.
 210  */
 211 int cvmx_l2c_lock_line(uint64_t addr);
 212
 213 /**
 214  * Locks a specified memory region in the L2 cache.
 215  *
 216  * Note that if not all lines can be locked, that means that all
 217  * but one of the ways (associations) available to the locking
 218  * core are locked.  Having only 1 association available for
 219  * normal caching may have a significant adverse affect on performance.
 220  * Care should be taken to ensure that enough of the L2 cache is left
 221  * unlocked to allow for normal caching of DRAM.
 222  *
 223  * @start:  Physical address of the start of the region to lock
 224  * @len:    Length (in bytes) of region to lock
 225  *
 226  * Returns Number of requested lines that where not locked.
 227  *         0 on success (all locked)
 228  */
 229 int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len);
 230
 231 /**
 232  * Unlock and flush a cache line from the L2 cache.
 233  * IMPORTANT: Must only be run by one core at a time due to use
 234  * of L2C debug features.
 235  * Note that this function will flush a matching but unlocked cache line.
 236  * (If address is not in L2, no lines are flushed.)
 237  *
 238  * @address: Physical address to unlock
 239  *
 240  * Returns 0: line not unlocked
 241  *         1: line unlocked
 242  */
 243 int cvmx_l2c_unlock_line(uint64_t address);
 244
 245 /**
 246  * Unlocks a region of memory that is locked in the L2 cache
 247  *
 248  * @start:  start physical address
 249  * @len:    length (in bytes) to unlock
 250  *
 251  * Returns Number of locked lines that the call unlocked
 252  */
 253 int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
 254
 255 /**
 256  * Read the L2 controller tag for a given location in L2
 257  *
 258  * @association:
 259  *               Which association to read line from
 260  * @index:  Which way to read from.
 261  *
 262  * Returns l2c tag structure for line requested.
 263  */
 264 union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index);
 265
 266 /* Wrapper around deprecated old function name */
 267 static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
 268                                               uint32_t index)
 269 {
 270         return cvmx_l2c_get_tag(association, index);
 271 }
 272
 273 /**
 274  * Returns the cache index for a given physical address
 275  *
 276  * @addr:   physical address
 277  *
 278  * Returns L2 cache index
 279  */
 280 uint32_t cvmx_l2c_address_to_index(uint64_t addr);
 281
 282 /**
 283  * Flushes (and unlocks) the entire L2 cache.
 284  * IMPORTANT: Must only be run by one core at a time due to use
 285  * of L2C debug features.
 286  */
 287 void cvmx_l2c_flush(void);
 288
 289 /**
 290  *
 291  * Returns Returns the size of the L2 cache in bytes,
 292  * -1 on error (unrecognized model)
 293  */
 294 int cvmx_l2c_get_cache_size_bytes(void);
 295
 296 /**
 297  * Return the number of sets in the L2 Cache
 298  *
 299  * Returns
 300  */
 301 int cvmx_l2c_get_num_sets(void);
 302
 303 /**
 304  * Return log base 2 of the number of sets in the L2 cache
 305  * Returns
 306  */
 307 int cvmx_l2c_get_set_bits(void);
 308 /**
 309  * Return the number of associations in the L2 Cache
 310  *
 311  * Returns
 312  */
 313 int cvmx_l2c_get_num_assoc(void);
 314
 315 /**
 316  * Flush a line from the L2 cache
 317  * This should only be called from one core at a time, as this routine
 318  * sets the core to the 'debug' core in order to flush the line.
 319  *
 320  * @assoc:  Association (or way) to flush
 321  * @index:  Index to flush
 322  */
 323 void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index);
 324
 325 #endif /* __CVMX_L2C_H__ */