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added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / arch / mips / emma / markeins / irq.c
blobc2583ecc93cf876a530d9daeef066a1dadd35c53
1 /*
2 * arch/mips/emma2rh/markeins/irq.c
3 * This file defines the irq handler for EMMA2RH.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/types.h>
29 #include <linux/ptrace.h>
30 #include <linux/delay.h>
31
32 #include <asm/irq_cpu.h>
33 #include <asm/system.h>
34 #include <asm/mipsregs.h>
35 #include <asm/addrspace.h>
36 #include <asm/bootinfo.h>
37
38 #include <asm/emma/emma2rh.h>
39
40 static void emma2rh_irq_enable(unsigned int irq)
41 {
42 u32 reg_value;
43 u32 reg_bitmask;
44 u32 reg_index;
45
46 irq -= EMMA2RH_IRQ_BASE;
47
48 reg_index = EMMA2RH_BHIF_INT_EN_0 +
49 (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
50 reg_value = emma2rh_in32(reg_index);
51 reg_bitmask = 0x1 << (irq % 32);
52 emma2rh_out32(reg_index, reg_value | reg_bitmask);
53 }
54
55 static void emma2rh_irq_disable(unsigned int irq)
56 {
57 u32 reg_value;
58 u32 reg_bitmask;
59 u32 reg_index;
60
61 irq -= EMMA2RH_IRQ_BASE;
62
63 reg_index = EMMA2RH_BHIF_INT_EN_0 +
64 (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
65 reg_value = emma2rh_in32(reg_index);
66 reg_bitmask = 0x1 << (irq % 32);
67 emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
68 }
69
70 struct irq_chip emma2rh_irq_controller = {
71 .name = "emma2rh_irq",
72 .ack = emma2rh_irq_disable,
73 .mask = emma2rh_irq_disable,
74 .mask_ack = emma2rh_irq_disable,
75 .unmask = emma2rh_irq_enable,
76 };
77
78 void emma2rh_irq_init(void)
79 {
80 u32 i;
81
82 for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
83 set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i,
84 &emma2rh_irq_controller,
85 handle_level_irq);
86 }
87
88 static void emma2rh_sw_irq_enable(unsigned int irq)
89 {
90 u32 reg;
91
92 irq -= EMMA2RH_SW_IRQ_BASE;
93
94 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
95 reg |= 1 << irq;
96 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
97 }
98
99 static void emma2rh_sw_irq_disable(unsigned int irq)
100 {
101 u32 reg;
102
103 irq -= EMMA2RH_SW_IRQ_BASE;
104
105 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
106 reg &= ~(1 << irq);
107 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
108 }
109
110 struct irq_chip emma2rh_sw_irq_controller = {
111 .name = "emma2rh_sw_irq",
112 .ack = emma2rh_sw_irq_disable,
113 .mask = emma2rh_sw_irq_disable,
114 .mask_ack = emma2rh_sw_irq_disable,
115 .unmask = emma2rh_sw_irq_enable,
116 };
117
118 void emma2rh_sw_irq_init(void)
119 {
120 u32 i;
121
122 for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
123 set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE + i,
124 &emma2rh_sw_irq_controller,
125 handle_level_irq);
126 }
127
128 static void emma2rh_gpio_irq_enable(unsigned int irq)
129 {
130 u32 reg;
131
132 irq -= EMMA2RH_GPIO_IRQ_BASE;
133
134 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
135 reg |= 1 << irq;
136 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
137 }
138
139 static void emma2rh_gpio_irq_disable(unsigned int irq)
140 {
141 u32 reg;
142
143 irq -= EMMA2RH_GPIO_IRQ_BASE;
144
145 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
146 reg &= ~(1 << irq);
147 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
148 }
149
150 static void emma2rh_gpio_irq_ack(unsigned int irq)
151 {
152 u32 reg;
153
154 irq -= EMMA2RH_GPIO_IRQ_BASE;
155 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
156
157 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
158 reg &= ~(1 << irq);
159 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
160 }
161
162 static void emma2rh_gpio_irq_end(unsigned int irq)
163 {
164 u32 reg;
165
166 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
167
168 irq -= EMMA2RH_GPIO_IRQ_BASE;
169
170 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
171 reg |= 1 << irq;
172 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
173 }
174 }
175
176 struct irq_chip emma2rh_gpio_irq_controller = {
177 .name = "emma2rh_gpio_irq",
178 .ack = emma2rh_gpio_irq_ack,
179 .mask = emma2rh_gpio_irq_disable,
180 .mask_ack = emma2rh_gpio_irq_ack,
181 .unmask = emma2rh_gpio_irq_enable,
182 .end = emma2rh_gpio_irq_end,
183 };
184
185 void emma2rh_gpio_irq_init(void)
186 {
187 u32 i;
188
189 for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
190 set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i,
191 &emma2rh_gpio_irq_controller);
192 }
193
194 static struct irqaction irq_cascade = {
195 .handler = no_action,
196 .flags = 0,
197 .mask = CPU_MASK_NONE,
198 .name = "cascade",
199 .dev_id = NULL,
200 .next = NULL,
201 };
202
203 /*
204 * the first level int-handler will jump here if it is a emma2rh irq
205 */
206 void emma2rh_irq_dispatch(void)
207 {
208 u32 intStatus;
209 u32 bitmask;
210 u32 i;
211
212 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0) &
213 emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
214
215 #ifdef EMMA2RH_SW_CASCADE
216 if (intStatus &
217 (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
218 u32 swIntStatus;
219 swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
220 & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
221 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
222 if (swIntStatus & bitmask) {
223 do_IRQ(EMMA2RH_SW_IRQ_BASE + i);
224 return;
225 }
226 }
227 }
228 #endif
229
230 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
231 if (intStatus & bitmask) {
232 do_IRQ(EMMA2RH_IRQ_BASE + i);
233 return;
234 }
235 }
236
237 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1) &
238 emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
239
240 #ifdef EMMA2RH_GPIO_CASCADE
241 if (intStatus &
242 (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
243 u32 gpioIntStatus;
244 gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
245 & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
246 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
247 if (gpioIntStatus & bitmask) {
248 do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i);
249 return;
250 }
251 }
252 }
253 #endif
254
255 for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
256 if (intStatus & bitmask) {
257 do_IRQ(EMMA2RH_IRQ_BASE + i);
258 return;
259 }
260 }
261
262 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2) &
263 emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
264
265 for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
266 if (intStatus & bitmask) {
267 do_IRQ(EMMA2RH_IRQ_BASE + i);
268 return;
269 }
270 }
271 }
272
273 void __init arch_init_irq(void)
274 {
275 u32 reg;
276
277 /* by default, interrupts are disabled. */
278 emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0);
279 emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0);
280 emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0);
281 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0);
282 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0);
283 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0);
284 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0);
285
286 clear_c0_status(0xff00);
287 set_c0_status(0x0400);
288
289 #define GPIO_PCI (0xf<<15)
290 /* setup GPIO interrupt for PCI interface */
291 /* direction input */
292 reg = emma2rh_in32(EMMA2RH_GPIO_DIR);
293 emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);
294 /* disable interrupt */
295 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
296 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);
297 /* level triggerd */
298 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);
299 emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);
300 reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);
301 emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));
302 /* interrupt clear */
303 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
304
305 /* init all controllers */
306 emma2rh_irq_init();
307 emma2rh_sw_irq_init();
308 emma2rh_gpio_irq_init();
309 mips_cpu_irq_init();
310
311 /* setup cascade interrupts */
312 setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
313 setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
314 setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
315 }
316
317 asmlinkage void plat_irq_dispatch(void)
318 {
319 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
320
321 if (pending & STATUSF_IP7)
322 do_IRQ(CPU_IRQ_BASE + 7);
323 else if (pending & STATUSF_IP2)
324 emma2rh_irq_dispatch();
325 else if (pending & STATUSF_IP1)
326 do_IRQ(CPU_IRQ_BASE + 1);
327 else if (pending & STATUSF_IP0)
328 do_IRQ(CPU_IRQ_BASE + 0);
329 else
330 spurious_interrupt();
331 }
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