kernel/2.6.29.6-aldebaran-rt/arch/mips/alchemy/devboards/pb1000/board_setup.c

   1 /*
   2  * Copyright 2000, 2008 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc. <source@mvista.com>
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  *
  10  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  11  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  13  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  14  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  15  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  16  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  17  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  18  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  19  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  20  *
  21  *  You should have received a copy of the  GNU General Public License along
  22  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  23  *  675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/delay.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <asm/mach-au1x00/au1000.h>
  30 #include <asm/mach-pb1x00/pb1000.h>
  31 #include <prom.h>
  32
  33
  34 struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
  35         { AU1000_GPIO_15, IRQF_TRIGGER_LOW, 0 },
  36 };
  37
  38
  39 const char *get_system_type(void)
  40 {
  41         return "Alchemy Pb1000";
  42 }
  43
  44 void board_reset(void)
  45 {
  46 }
  47
  48 void __init board_init_irq(void)
  49 {
  50         au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
  51 }
  52
  53 void __init board_setup(void)
  54 {
  55         u32 pin_func, static_cfg0;
  56         u32 sys_freqctrl, sys_clksrc;
  57         u32 prid = read_c0_prid();
  58
  59 #ifdef CONFIG_SERIAL_8250_CONSOLE
  60         char *argptr = prom_getcmdline();
  61         argptr = strstr(argptr, "console=");
  62         if (argptr == NULL) {
  63                 argptr = prom_getcmdline();
  64                 strcat(argptr, " console=ttyS0,115200");
  65         }
  66 #endif
  67
  68         /* Set AUX clock to 12 MHz * 8 = 96 MHz */
  69         au_writel(8, SYS_AUXPLL);
  70         au_writel(0, SYS_PINSTATERD);
  71         udelay(100);
  72
  73 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  74         /* Zero and disable FREQ2 */
  75         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  76         sys_freqctrl &= ~0xFFF00000;
  77         au_writel(sys_freqctrl, SYS_FREQCTRL0);
  78
  79         /* Zero and disable USBH/USBD clocks */
  80         sys_clksrc = au_readl(SYS_CLKSRC);
  81         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  82                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  83         au_writel(sys_clksrc, SYS_CLKSRC);
  84
  85         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  86         sys_freqctrl &= ~0xFFF00000;
  87
  88         sys_clksrc = au_readl(SYS_CLKSRC);
  89         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  90                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  91
  92         switch (prid & 0x000000FF) {
  93         case 0x00: /* DA */
  94         case 0x01: /* HA */
  95         case 0x02: /* HB */
  96                 /* CPU core freq to 48 MHz to slow it way down... */
  97                 au_writel(4, SYS_CPUPLL);
  98
  99                 /*
 100                  * Setup 48 MHz FREQ2 from CPUPLL for USB Host
 101                  * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
 102                  */
 103                 sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
 104                 au_writel(sys_freqctrl, SYS_FREQCTRL0);
 105
 106                 /* CPU core freq to 384 MHz */
 107                 au_writel(0x20, SYS_CPUPLL);
 108
 109                 printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
 110                 break;
 111
 112         default: /* HC and newer */
 113                 /* FREQ2 = aux / 2 = 48 MHz */
 114                 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
 115                                  SYS_FC_FE2 | SYS_FC_FS2;
 116                 au_writel(sys_freqctrl, SYS_FREQCTRL0);
 117                 break;
 118         }
 119
 120         /*
 121          * Route 48 MHz FREQ2 into USB Host and/or Device
 122          */
 123         sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
 124         au_writel(sys_clksrc, SYS_CLKSRC);
 125
 126         /* Configure pins GPIO[14:9] as GPIO */
 127         pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
 128
 129         /* 2nd USB port is USB host */
 130         pin_func |= SYS_PF_USB;
 131
 132         au_writel(pin_func, SYS_PINFUNC);
 133         au_writel(0x2800, SYS_TRIOUTCLR);
 134         au_writel(0x0030, SYS_OUTPUTCLR);
 135 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
 136
 137         /* Make GPIO 15 an input (for interrupt line) */
 138         pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
 139         /* We don't need I2S, so make it available for GPIO[31:29] */
 140         pin_func |= SYS_PF_I2S;
 141         au_writel(pin_func, SYS_PINFUNC);
 142
 143         au_writel(0x8000, SYS_TRIOUTCLR);
 144
 145         static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
 146         au_writel(static_cfg0, MEM_STCFG0);
 147
 148         /* configure RCE2* for LCD */
 149         au_writel(0x00000004, MEM_STCFG2);
 150
 151         /* MEM_STTIME2 */
 152         au_writel(0x09000000, MEM_STTIME2);
 153
 154         /* Set 32-bit base address decoding for RCE2* */
 155         au_writel(0x10003ff0, MEM_STADDR2);
 156
 157         /*
 158          * PCI CPLD setup
 159          * Expand CE0 to cover PCI
 160          */
 161         au_writel(0x11803e40, MEM_STADDR1);
 162
 163         /* Burst visibility on */
 164         au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
 165
 166         au_writel(0x83, MEM_STCFG1);         /* ewait enabled, flash timing */
 167         au_writel(0x33030a10, MEM_STTIME1);  /* slower timing for FPGA */
 168
 169         /* Setup the static bus controller */
 170         au_writel(0x00000002, MEM_STCFG3);  /* type = PCMCIA */
 171         au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
 172         au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
 173
 174         /*
 175          * Enable Au1000 BCLK switching - note: sed1356 must not use
 176          * its BCLK (Au1000 LCLK) for any timings
 177          */
 178         switch (prid & 0x000000FF) {
 179         case 0x00: /* DA */
 180         case 0x01: /* HA */
 181         case 0x02: /* HB */
 182                 break;
 183         default:  /* HC and newer */
 184                 /*
 185                  * Enable sys bus clock divider when IDLE state or no bus
 186                  * activity.
 187                  */
 188                 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
 189                 break;
 190         }
 191 }