kernel/2.6.29.6-aldebaran-rt/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h

   1 /*
   2  * file:         include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
   3  * based on:
   4  * author:
   5  *
   6  * created:
   7  * description:
   8  *      blackfin serial driver header files
   9  * rev:
  10  *
  11  * modified:
  12  *
  13  *
  14  * bugs:         enter bugs at http://blackfin.uclinux.org/
  15  *
  16  * this program is free software; you can redistribute it and/or modify
  17  * it under the terms of the gnu general public license as published by
  18  * the free software foundation; either version 2, or (at your option)
  19  * any later version.
  20  *
  21  * this program is distributed in the hope that it will be useful,
  22  * but without any warranty; without even the implied warranty of
  23  * merchantability or fitness for a particular purpose.  see the
  24  * gnu general public license for more details.
  25  *
  26  * you should have received a copy of the gnu general public license
  27  * along with this program; see the file copying.
  28  * if not, write to the free software foundation,
  29  * 59 temple place - suite 330, boston, ma 02111-1307, usa.
  30  */
  31
  32 #include <linux/serial.h>
  33 #include <asm/dma.h>
  34 #include <asm/portmux.h>
  35
  36 #define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
  37 #define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
  38 #define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
  39 #define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
  40 #define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
  41 #define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
  42 #define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  43
  44 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
  45 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
  46 #define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
  47 #define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
  48 #define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
  49 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
  50 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
  51 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
  52
  53 #define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
  54 #define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
  55
  56 #define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
  57 #define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
  58 #define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
  59 #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
  60 #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
  61
  62 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
  63 # define CONFIG_SERIAL_BFIN_CTSRTS
  64
  65 # ifndef CONFIG_UART0_CTS_PIN
  66 #  define CONFIG_UART0_CTS_PIN -1
  67 # endif
  68
  69 # ifndef CONFIG_UART0_RTS_PIN
  70 #  define CONFIG_UART0_RTS_PIN -1
  71 # endif
  72
  73 # ifndef CONFIG_UART1_CTS_PIN
  74 #  define CONFIG_UART1_CTS_PIN -1
  75 # endif
  76
  77 # ifndef CONFIG_UART1_RTS_PIN
  78 #  define CONFIG_UART1_RTS_PIN -1
  79 # endif
  80 #endif
  81
  82 #define BFIN_UART_TX_FIFO_SIZE  2
  83
  84 /*
  85  * The pin configuration is different from schematic
  86  */
  87 struct bfin_serial_port {
  88         struct uart_port        port;
  89         unsigned int            old_status;
  90         unsigned int lsr;
  91 #ifdef CONFIG_SERIAL_BFIN_DMA
  92         int                     tx_done;
  93         int                     tx_count;
  94         struct circ_buf         rx_dma_buf;
  95         struct timer_list       rx_dma_timer;
  96         int                     rx_dma_nrows;
  97         unsigned int            tx_dma_channel;
  98         unsigned int            rx_dma_channel;
  99         struct work_struct      tx_dma_workqueue;
 100 #endif
 101 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 102         struct timer_list       cts_timer;
 103         int             cts_pin;
 104         int             rts_pin;
 105 #endif
 106 };
 107
 108 /* The hardware clears the LSR bits upon read, so we need to cache
 109  * some of the more fun bits in software so they don't get lost
 110  * when checking the LSR in other code paths (TX).
 111  */
 112 static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
 113 {
 114         unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
 115         uart->lsr |= (lsr & (BI|FE|PE|OE));
 116         return lsr | uart->lsr;
 117 }
 118
 119 static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
 120 {
 121         uart->lsr = 0;
 122         bfin_write16(uart->port.membase + OFFSET_LSR, -1);
 123 }
 124
 125 struct bfin_serial_res {
 126         unsigned long   uart_base_addr;
 127         int             uart_irq;
 128 #ifdef CONFIG_SERIAL_BFIN_DMA
 129         unsigned int    uart_tx_dma_channel;
 130         unsigned int    uart_rx_dma_channel;
 131 #endif
 132 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 133         int     uart_cts_pin;
 134         int     uart_rts_pin;
 135 #endif
 136 };
 137
 138 struct bfin_serial_res bfin_serial_resource[] = {
 139 #ifdef CONFIG_SERIAL_BFIN_UART0
 140         {
 141         0xFFC00400,
 142         IRQ_UART0_RX,
 143 #ifdef CONFIG_SERIAL_BFIN_DMA
 144         CH_UART0_TX,
 145         CH_UART0_RX,
 146 #endif
 147 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 148         CONFIG_UART0_CTS_PIN,
 149         CONFIG_UART0_RTS_PIN,
 150 #endif
 151         },
 152 #endif
 153 #ifdef CONFIG_SERIAL_BFIN_UART1
 154         {
 155         0xFFC02000,
 156         IRQ_UART1_RX,
 157 #ifdef CONFIG_SERIAL_BFIN_DMA
 158         CH_UART1_TX,
 159         CH_UART1_RX,
 160 #endif
 161 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 162         CONFIG_UART1_CTS_PIN,
 163         CONFIG_UART1_RTS_PIN,
 164 #endif
 165         },
 166 #endif
 167 };
 168
 169 #define DRIVER_NAME "bfin-uart"
 170
 171 static void bfin_serial_hw_init(struct bfin_serial_port *uart)
 172 {
 173
 174 #ifdef CONFIG_SERIAL_BFIN_UART0
 175         peripheral_request(P_UART0_TX, DRIVER_NAME);
 176         peripheral_request(P_UART0_RX, DRIVER_NAME);
 177 #endif
 178
 179 #ifdef CONFIG_SERIAL_BFIN_UART1
 180         peripheral_request(P_UART1_TX, DRIVER_NAME);
 181         peripheral_request(P_UART1_RX, DRIVER_NAME);
 182 #endif
 183
 184 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 185         if (uart->cts_pin >= 0) {
 186                 gpio_request(uart->cts_pin, DRIVER_NAME);
 187                 gpio_direction_input(uart->cts_pin);
 188         }
 189
 190         if (uart->rts_pin >= 0) {
 191                 gpio_request(uart->rts_pin, DRIVER_NAME);
 192                 gpio_direction_output(uart->rts_pin, 0);
 193         }
 194 #endif
 195 }