2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
15 #include <linux/mman.h>
16 #include <linux/nodemask.h>
18 #include <asm/cputype.h>
19 #include <asm/mach-types.h>
20 #include <asm/sections.h>
21 #include <asm/setup.h>
22 #include <asm/sizes.h>
25 #include <asm/mach/arch.h>
26 #include <asm/mach/map.h>
31 * empty_zero_page is a special page that is used for
32 * zero-initialized data and COW.
34 struct page
*empty_zero_page
;
35 EXPORT_SYMBOL(empty_zero_page
);
38 * The pmd table for the upper-most set of pages.
42 #define CPOLICY_UNCACHED 0
43 #define CPOLICY_BUFFERED 1
44 #define CPOLICY_WRITETHROUGH 2
45 #define CPOLICY_WRITEBACK 3
46 #define CPOLICY_WRITEALLOC 4
48 static unsigned int cachepolicy __initdata
= CPOLICY_WRITEBACK
;
49 static unsigned int ecc_mask __initdata
= 0;
51 pgprot_t pgprot_kernel
;
53 EXPORT_SYMBOL(pgprot_user
);
54 EXPORT_SYMBOL(pgprot_kernel
);
57 const char policy
[16];
63 static struct cachepolicy cache_policies
[] __initdata
= {
67 .pmd
= PMD_SECT_UNCACHED
,
68 .pte
= L_PTE_MT_UNCACHED
,
72 .pmd
= PMD_SECT_BUFFERED
,
73 .pte
= L_PTE_MT_BUFFERABLE
,
75 .policy
= "writethrough",
78 .pte
= L_PTE_MT_WRITETHROUGH
,
80 .policy
= "writeback",
83 .pte
= L_PTE_MT_WRITEBACK
,
85 .policy
= "writealloc",
88 .pte
= L_PTE_MT_WRITEALLOC
,
93 * These are useful for identifying cache coherency
94 * problems by allowing the cache or the cache and
95 * writebuffer to be turned off. (Note: the write
96 * buffer should not be on and the cache off).
98 static void __init
early_cachepolicy(char **p
)
102 for (i
= 0; i
< ARRAY_SIZE(cache_policies
); i
++) {
103 int len
= strlen(cache_policies
[i
].policy
);
105 if (memcmp(*p
, cache_policies
[i
].policy
, len
) == 0) {
107 cr_alignment
&= ~cache_policies
[i
].cr_mask
;
108 cr_no_alignment
&= ~cache_policies
[i
].cr_mask
;
113 if (i
== ARRAY_SIZE(cache_policies
))
114 printk(KERN_ERR
"ERROR: unknown or unsupported cache policy\n");
115 if (cpu_architecture() >= CPU_ARCH_ARMv6
) {
116 printk(KERN_WARNING
"Only cachepolicy=writeback supported on ARMv6 and later\n");
117 cachepolicy
= CPOLICY_WRITEBACK
;
120 set_cr(cr_alignment
);
122 __early_param("cachepolicy=", early_cachepolicy
);
124 static void __init
early_nocache(char **__unused
)
126 char *p
= "buffered";
127 printk(KERN_WARNING
"nocache is deprecated; use cachepolicy=%s\n", p
);
128 early_cachepolicy(&p
);
130 __early_param("nocache", early_nocache
);
132 static void __init
early_nowrite(char **__unused
)
134 char *p
= "uncached";
135 printk(KERN_WARNING
"nowb is deprecated; use cachepolicy=%s\n", p
);
136 early_cachepolicy(&p
);
138 __early_param("nowb", early_nowrite
);
140 static void __init
early_ecc(char **p
)
142 if (memcmp(*p
, "on", 2) == 0) {
143 ecc_mask
= PMD_PROTECTION
;
145 } else if (memcmp(*p
, "off", 3) == 0) {
150 __early_param("ecc=", early_ecc
);
152 static int __init
noalign_setup(char *__unused
)
154 cr_alignment
&= ~CR_A
;
155 cr_no_alignment
&= ~CR_A
;
156 set_cr(cr_alignment
);
159 __setup("noalign", noalign_setup
);
162 void adjust_cr(unsigned long mask
, unsigned long set
)
170 local_irq_save(flags
);
172 cr_no_alignment
= (cr_no_alignment
& ~mask
) | set
;
173 cr_alignment
= (cr_alignment
& ~mask
) | set
;
175 set_cr((get_cr() & ~mask
) | set
);
177 local_irq_restore(flags
);
181 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
182 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
184 static struct mem_type mem_types
[] = {
185 [MT_DEVICE
] = { /* Strongly ordered / ARMv6 shared device */
186 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_SHARED
|
188 .prot_l1
= PMD_TYPE_TABLE
,
189 .prot_sect
= PROT_SECT_DEVICE
| PMD_SECT_S
,
192 [MT_DEVICE_NONSHARED
] = { /* ARMv6 non-shared device */
193 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_NONSHARED
,
194 .prot_l1
= PMD_TYPE_TABLE
,
195 .prot_sect
= PROT_SECT_DEVICE
,
198 [MT_DEVICE_CACHED
] = { /* ioremap_cached */
199 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_CACHED
,
200 .prot_l1
= PMD_TYPE_TABLE
,
201 .prot_sect
= PROT_SECT_DEVICE
| PMD_SECT_WB
,
204 [MT_DEVICE_WC
] = { /* ioremap_wc */
205 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_WC
,
206 .prot_l1
= PMD_TYPE_TABLE
,
207 .prot_sect
= PROT_SECT_DEVICE
,
211 .prot_pte
= PROT_PTE_DEVICE
,
212 .prot_l1
= PMD_TYPE_TABLE
,
213 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
,
217 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
,
218 .domain
= DOMAIN_KERNEL
,
221 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
| PMD_SECT_MINICACHE
,
222 .domain
= DOMAIN_KERNEL
,
225 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
227 .prot_l1
= PMD_TYPE_TABLE
,
228 .domain
= DOMAIN_USER
,
230 [MT_HIGH_VECTORS
] = {
231 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
232 L_PTE_USER
| L_PTE_EXEC
,
233 .prot_l1
= PMD_TYPE_TABLE
,
234 .domain
= DOMAIN_USER
,
237 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_AP_WRITE
,
238 .domain
= DOMAIN_KERNEL
,
241 .prot_sect
= PMD_TYPE_SECT
,
242 .domain
= DOMAIN_KERNEL
,
246 const struct mem_type
*get_mem_type(unsigned int type
)
248 return type
< ARRAY_SIZE(mem_types
) ? &mem_types
[type
] : NULL
;
252 * Adjust the PMD section entries according to the CPU in use.
254 static void __init
build_mem_type_table(void)
256 struct cachepolicy
*cp
;
257 unsigned int cr
= get_cr();
258 unsigned int user_pgprot
, kern_pgprot
, vecs_pgprot
;
259 int cpu_arch
= cpu_architecture();
262 if (cpu_arch
< CPU_ARCH_ARMv6
) {
263 #if defined(CONFIG_CPU_DCACHE_DISABLE)
264 if (cachepolicy
> CPOLICY_BUFFERED
)
265 cachepolicy
= CPOLICY_BUFFERED
;
266 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
267 if (cachepolicy
> CPOLICY_WRITETHROUGH
)
268 cachepolicy
= CPOLICY_WRITETHROUGH
;
271 if (cpu_arch
< CPU_ARCH_ARMv5
) {
272 if (cachepolicy
>= CPOLICY_WRITEALLOC
)
273 cachepolicy
= CPOLICY_WRITEBACK
;
277 cachepolicy
= CPOLICY_WRITEALLOC
;
281 * Strip out features not present on earlier architectures.
282 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
283 * without extended page tables don't have the 'Shared' bit.
285 if (cpu_arch
< CPU_ARCH_ARMv5
)
286 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++)
287 mem_types
[i
].prot_sect
&= ~PMD_SECT_TEX(7);
288 if ((cpu_arch
< CPU_ARCH_ARMv6
|| !(cr
& CR_XP
)) && !cpu_is_xsc3())
289 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++)
290 mem_types
[i
].prot_sect
&= ~PMD_SECT_S
;
293 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
294 * "update-able on write" bit on ARM610). However, Xscale and
295 * Xscale3 require this bit to be cleared.
297 if (cpu_is_xscale() || cpu_is_xsc3()) {
298 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
299 mem_types
[i
].prot_sect
&= ~PMD_BIT4
;
300 mem_types
[i
].prot_l1
&= ~PMD_BIT4
;
302 } else if (cpu_arch
< CPU_ARCH_ARMv6
) {
303 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
304 if (mem_types
[i
].prot_l1
)
305 mem_types
[i
].prot_l1
|= PMD_BIT4
;
306 if (mem_types
[i
].prot_sect
)
307 mem_types
[i
].prot_sect
|= PMD_BIT4
;
312 * Mark the device areas according to the CPU/architecture.
314 if (cpu_is_xsc3() || (cpu_arch
>= CPU_ARCH_ARMv6
&& (cr
& CR_XP
))) {
315 if (!cpu_is_xsc3()) {
317 * Mark device regions on ARMv6+ as execute-never
318 * to prevent speculative instruction fetches.
320 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_XN
;
321 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_XN
;
322 mem_types
[MT_DEVICE_CACHED
].prot_sect
|= PMD_SECT_XN
;
323 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_XN
;
325 if (cpu_arch
>= CPU_ARCH_ARMv7
&& (cr
& CR_TRE
)) {
327 * For ARMv7 with TEX remapping,
328 * - shared device is SXCB=1100
329 * - nonshared device is SXCB=0100
330 * - write combine device mem is SXCB=0001
331 * (Uncached Normal memory)
333 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_TEX(1);
334 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_TEX(1);
335 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_BUFFERABLE
;
336 } else if (cpu_is_xsc3()) {
339 * - shared device is TEXCB=00101
340 * - nonshared device is TEXCB=01000
341 * - write combine device mem is TEXCB=00100
342 * (Inner/Outer Uncacheable in xsc3 parlance)
344 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED
;
345 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_TEX(2);
346 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_TEX(1);
349 * For ARMv6 and ARMv7 without TEX remapping,
350 * - shared device is TEXCB=00001
351 * - nonshared device is TEXCB=01000
352 * - write combine device mem is TEXCB=00100
353 * (Uncached Normal in ARMv6 parlance).
355 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_BUFFERED
;
356 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_TEX(2);
357 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_TEX(1);
361 * On others, write combining is "Uncached/Buffered"
363 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_BUFFERABLE
;
367 * Now deal with the memory-type mappings
369 cp
= &cache_policies
[cachepolicy
];
370 vecs_pgprot
= kern_pgprot
= user_pgprot
= cp
->pte
;
374 * Only use write-through for non-SMP systems
376 if (cpu_arch
>= CPU_ARCH_ARMv5
&& cachepolicy
> CPOLICY_WRITETHROUGH
)
377 vecs_pgprot
= cache_policies
[CPOLICY_WRITETHROUGH
].pte
;
381 * Enable CPU-specific coherency if supported.
382 * (Only available on XSC3 at the moment.)
384 if (arch_is_coherent() && cpu_is_xsc3())
385 mem_types
[MT_MEMORY
].prot_sect
|= PMD_SECT_S
;
388 * ARMv6 and above have extended page tables.
390 if (cpu_arch
>= CPU_ARCH_ARMv6
&& (cr
& CR_XP
)) {
392 * Mark cache clean areas and XIP ROM read only
393 * from SVC mode and no access from userspace.
395 mem_types
[MT_ROM
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
396 mem_types
[MT_MINICLEAN
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
397 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
401 * Mark memory with the "shared" attribute for SMP systems
403 user_pgprot
|= L_PTE_SHARED
;
404 kern_pgprot
|= L_PTE_SHARED
;
405 vecs_pgprot
|= L_PTE_SHARED
;
406 mem_types
[MT_MEMORY
].prot_sect
|= PMD_SECT_S
;
410 for (i
= 0; i
< 16; i
++) {
411 unsigned long v
= pgprot_val(protection_map
[i
]);
412 protection_map
[i
] = __pgprot(v
| user_pgprot
);
415 mem_types
[MT_LOW_VECTORS
].prot_pte
|= vecs_pgprot
;
416 mem_types
[MT_HIGH_VECTORS
].prot_pte
|= vecs_pgprot
;
418 pgprot_user
= __pgprot(L_PTE_PRESENT
| L_PTE_YOUNG
| user_pgprot
);
419 pgprot_kernel
= __pgprot(L_PTE_PRESENT
| L_PTE_YOUNG
|
420 L_PTE_DIRTY
| L_PTE_WRITE
|
421 L_PTE_EXEC
| kern_pgprot
);
423 mem_types
[MT_LOW_VECTORS
].prot_l1
|= ecc_mask
;
424 mem_types
[MT_HIGH_VECTORS
].prot_l1
|= ecc_mask
;
425 mem_types
[MT_MEMORY
].prot_sect
|= ecc_mask
| cp
->pmd
;
426 mem_types
[MT_ROM
].prot_sect
|= cp
->pmd
;
430 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_WT
;
434 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_WB
;
437 printk("Memory policy: ECC %sabled, Data cache %s\n",
438 ecc_mask
? "en" : "dis", cp
->policy
);
440 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
441 struct mem_type
*t
= &mem_types
[i
];
443 t
->prot_l1
|= PMD_DOMAIN(t
->domain
);
445 t
->prot_sect
|= PMD_DOMAIN(t
->domain
);
449 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
451 static void __init
alloc_init_pte(pmd_t
*pmd
, unsigned long addr
,
452 unsigned long end
, unsigned long pfn
,
453 const struct mem_type
*type
)
457 if (pmd_none(*pmd
)) {
458 pte
= alloc_bootmem_low_pages(2 * PTRS_PER_PTE
* sizeof(pte_t
));
459 __pmd_populate(pmd
, __pa(pte
) | type
->prot_l1
);
462 pte
= pte_offset_kernel(pmd
, addr
);
464 set_pte_ext(pte
, pfn_pte(pfn
, __pgprot(type
->prot_pte
)), 0);
466 } while (pte
++, addr
+= PAGE_SIZE
, addr
!= end
);
469 static void __init
alloc_init_section(pgd_t
*pgd
, unsigned long addr
,
470 unsigned long end
, unsigned long phys
,
471 const struct mem_type
*type
)
473 pmd_t
*pmd
= pmd_offset(pgd
, addr
);
476 * Try a section mapping - end, addr and phys must all be aligned
477 * to a section boundary. Note that PMDs refer to the individual
478 * L1 entries, whereas PGDs refer to a group of L1 entries making
479 * up one logical pointer to an L2 table.
481 if (((addr
| end
| phys
) & ~SECTION_MASK
) == 0) {
484 if (addr
& SECTION_SIZE
)
488 *pmd
= __pmd(phys
| type
->prot_sect
);
489 phys
+= SECTION_SIZE
;
490 } while (pmd
++, addr
+= SECTION_SIZE
, addr
!= end
);
495 * No need to loop; pte's aren't interested in the
496 * individual L1 entries.
498 alloc_init_pte(pmd
, addr
, end
, __phys_to_pfn(phys
), type
);
502 static void __init
create_36bit_mapping(struct map_desc
*md
,
503 const struct mem_type
*type
)
505 unsigned long phys
, addr
, length
, end
;
509 phys
= (unsigned long)__pfn_to_phys(md
->pfn
);
510 length
= PAGE_ALIGN(md
->length
);
512 if (!(cpu_architecture() >= CPU_ARCH_ARMv6
|| cpu_is_xsc3())) {
513 printk(KERN_ERR
"MM: CPU does not support supersection "
514 "mapping for 0x%08llx at 0x%08lx\n",
515 __pfn_to_phys((u64
)md
->pfn
), addr
);
519 /* N.B. ARMv6 supersections are only defined to work with domain 0.
520 * Since domain assignments can in fact be arbitrary, the
521 * 'domain == 0' check below is required to insure that ARMv6
522 * supersections are only allocated for domain 0 regardless
523 * of the actual domain assignments in use.
526 printk(KERN_ERR
"MM: invalid domain in supersection "
527 "mapping for 0x%08llx at 0x%08lx\n",
528 __pfn_to_phys((u64
)md
->pfn
), addr
);
532 if ((addr
| length
| __pfn_to_phys(md
->pfn
)) & ~SUPERSECTION_MASK
) {
533 printk(KERN_ERR
"MM: cannot create mapping for "
534 "0x%08llx at 0x%08lx invalid alignment\n",
535 __pfn_to_phys((u64
)md
->pfn
), addr
);
540 * Shift bits [35:32] of address into bits [23:20] of PMD
543 phys
|= (((md
->pfn
>> (32 - PAGE_SHIFT
)) & 0xF) << 20);
545 pgd
= pgd_offset_k(addr
);
548 pmd_t
*pmd
= pmd_offset(pgd
, addr
);
551 for (i
= 0; i
< 16; i
++)
552 *pmd
++ = __pmd(phys
| type
->prot_sect
| PMD_SECT_SUPER
);
554 addr
+= SUPERSECTION_SIZE
;
555 phys
+= SUPERSECTION_SIZE
;
556 pgd
+= SUPERSECTION_SIZE
>> PGDIR_SHIFT
;
557 } while (addr
!= end
);
561 * Create the page directory entries and any necessary
562 * page tables for the mapping specified by `md'. We
563 * are able to cope here with varying sizes and address
564 * offsets, and we take full advantage of sections and
567 void __init
create_mapping(struct map_desc
*md
)
569 unsigned long phys
, addr
, length
, end
;
570 const struct mem_type
*type
;
573 if (md
->virtual != vectors_base() && md
->virtual < TASK_SIZE
) {
574 printk(KERN_WARNING
"BUG: not creating mapping for "
575 "0x%08llx at 0x%08lx in user region\n",
576 __pfn_to_phys((u64
)md
->pfn
), md
->virtual);
580 if ((md
->type
== MT_DEVICE
|| md
->type
== MT_ROM
) &&
581 md
->virtual >= PAGE_OFFSET
&& md
->virtual < VMALLOC_END
) {
582 printk(KERN_WARNING
"BUG: mapping for 0x%08llx at 0x%08lx "
583 "overlaps vmalloc space\n",
584 __pfn_to_phys((u64
)md
->pfn
), md
->virtual);
587 type
= &mem_types
[md
->type
];
590 * Catch 36-bit addresses
592 if (md
->pfn
>= 0x100000) {
593 create_36bit_mapping(md
, type
);
597 addr
= md
->virtual & PAGE_MASK
;
598 phys
= (unsigned long)__pfn_to_phys(md
->pfn
);
599 length
= PAGE_ALIGN(md
->length
+ (md
->virtual & ~PAGE_MASK
));
601 if (type
->prot_l1
== 0 && ((addr
| phys
| length
) & ~SECTION_MASK
)) {
602 printk(KERN_WARNING
"BUG: map for 0x%08lx at 0x%08lx can not "
603 "be mapped using pages, ignoring.\n",
604 __pfn_to_phys(md
->pfn
), addr
);
608 pgd
= pgd_offset_k(addr
);
611 unsigned long next
= pgd_addr_end(addr
, end
);
613 alloc_init_section(pgd
, addr
, next
, phys
, type
);
617 } while (pgd
++, addr
!= end
);
621 * Create the architecture specific mappings
623 void __init
iotable_init(struct map_desc
*io_desc
, int nr
)
627 for (i
= 0; i
< nr
; i
++)
628 create_mapping(io_desc
+ i
);
631 static unsigned long __initdata vmalloc_reserve
= SZ_128M
;
634 * vmalloc=size forces the vmalloc area to be exactly 'size'
635 * bytes. This can be used to increase (or decrease) the vmalloc
636 * area - the default is 128m.
638 static void __init
early_vmalloc(char **arg
)
640 vmalloc_reserve
= memparse(*arg
, arg
);
642 if (vmalloc_reserve
< SZ_16M
) {
643 vmalloc_reserve
= SZ_16M
;
645 "vmalloc area too small, limiting to %luMB\n",
646 vmalloc_reserve
>> 20);
649 if (vmalloc_reserve
> VMALLOC_END
- (PAGE_OFFSET
+ SZ_32M
)) {
650 vmalloc_reserve
= VMALLOC_END
- (PAGE_OFFSET
+ SZ_32M
);
652 "vmalloc area is too big, limiting to %luMB\n",
653 vmalloc_reserve
>> 20);
656 __early_param("vmalloc=", early_vmalloc
);
658 #define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve)
660 static void __init
sanity_check_meminfo(void)
664 for (i
= 0, j
= 0; i
< meminfo
.nr_banks
; i
++) {
665 struct membank
*bank
= &meminfo
.bank
[j
];
666 *bank
= meminfo
.bank
[i
];
668 #ifdef CONFIG_HIGHMEM
670 * Split those memory banks which are partially overlapping
671 * the vmalloc area greatly simplifying things later.
673 if (__va(bank
->start
) < VMALLOC_MIN
&&
674 bank
->size
> VMALLOC_MIN
- __va(bank
->start
)) {
675 if (meminfo
.nr_banks
>= NR_BANKS
) {
676 printk(KERN_CRIT
"NR_BANKS too low, "
677 "ignoring high memory\n");
679 memmove(bank
+ 1, bank
,
680 (meminfo
.nr_banks
- i
) * sizeof(*bank
));
683 bank
[1].size
-= VMALLOC_MIN
- __va(bank
->start
);
684 bank
[1].start
= __pa(VMALLOC_MIN
- 1) + 1;
687 bank
->size
= VMALLOC_MIN
- __va(bank
->start
);
691 * Check whether this memory bank would entirely overlap
694 if (__va(bank
->start
) >= VMALLOC_MIN
||
695 __va(bank
->start
) < (void *)PAGE_OFFSET
) {
696 printk(KERN_NOTICE
"Ignoring RAM at %.8lx-%.8lx "
697 "(vmalloc region overlap).\n",
698 bank
->start
, bank
->start
+ bank
->size
- 1);
703 * Check whether this memory bank would partially overlap
706 if (__va(bank
->start
+ bank
->size
) > VMALLOC_MIN
||
707 __va(bank
->start
+ bank
->size
) < __va(bank
->start
)) {
708 unsigned long newsize
= VMALLOC_MIN
- __va(bank
->start
);
709 printk(KERN_NOTICE
"Truncating RAM at %.8lx-%.8lx "
710 "to -%.8lx (vmalloc region overlap).\n",
711 bank
->start
, bank
->start
+ bank
->size
- 1,
712 bank
->start
+ newsize
- 1);
713 bank
->size
= newsize
;
718 meminfo
.nr_banks
= j
;
721 static inline void prepare_page_table(void)
726 * Clear out all the mappings below the kernel image.
728 for (addr
= 0; addr
< MODULES_VADDR
; addr
+= PGDIR_SIZE
)
729 pmd_clear(pmd_off_k(addr
));
731 #ifdef CONFIG_XIP_KERNEL
732 /* The XIP kernel is mapped in the module area -- skip over it */
733 addr
= ((unsigned long)_etext
+ PGDIR_SIZE
- 1) & PGDIR_MASK
;
735 for ( ; addr
< PAGE_OFFSET
; addr
+= PGDIR_SIZE
)
736 pmd_clear(pmd_off_k(addr
));
739 * Clear out all the kernel space mappings, except for the first
740 * memory bank, up to the end of the vmalloc region.
742 for (addr
= __phys_to_virt(bank_phys_end(&meminfo
.bank
[0]));
743 addr
< VMALLOC_END
; addr
+= PGDIR_SIZE
)
744 pmd_clear(pmd_off_k(addr
));
748 * Reserve the various regions of node 0
750 void __init
reserve_node_zero(pg_data_t
*pgdat
)
752 unsigned long res_size
= 0;
755 * Register the kernel text and data with bootmem.
756 * Note that this can only be in node 0.
758 #ifdef CONFIG_XIP_KERNEL
759 reserve_bootmem_node(pgdat
, __pa(_data
), _end
- _data
,
762 reserve_bootmem_node(pgdat
, __pa(_stext
), _end
- _stext
,
767 * Reserve the page tables. These are already in use,
768 * and can only be in node 0.
770 reserve_bootmem_node(pgdat
, __pa(swapper_pg_dir
),
771 PTRS_PER_PGD
* sizeof(pgd_t
), BOOTMEM_DEFAULT
);
774 * Hmm... This should go elsewhere, but we really really need to
775 * stop things allocating the low memory; ideally we need a better
776 * implementation of GFP_DMA which does not assume that DMA-able
777 * memory starts at zero.
779 if (machine_is_integrator() || machine_is_cintegrator())
780 res_size
= __pa(swapper_pg_dir
) - PHYS_OFFSET
;
783 * These should likewise go elsewhere. They pre-reserve the
784 * screen memory region at the start of main system memory.
786 if (machine_is_edb7211())
787 res_size
= 0x00020000;
788 if (machine_is_p720t())
789 res_size
= 0x00014000;
791 /* H1940 and RX3715 need to reserve this for suspend */
793 if (machine_is_h1940() || machine_is_rx3715()) {
794 reserve_bootmem_node(pgdat
, 0x30003000, 0x1000,
796 reserve_bootmem_node(pgdat
, 0x30081000, 0x1000,
802 * Because of the SA1111 DMA bug, we want to preserve our
803 * precious DMA-able memory...
805 res_size
= __pa(swapper_pg_dir
) - PHYS_OFFSET
;
808 reserve_bootmem_node(pgdat
, PHYS_OFFSET
, res_size
,
813 * Set up device the mappings. Since we clear out the page tables for all
814 * mappings above VMALLOC_END, we will remove any debug device mappings.
815 * This means you have to be careful how you debug this function, or any
816 * called function. This means you can't use any function or debugging
817 * method which may touch any device, otherwise the kernel _will_ crash.
819 static void __init
devicemaps_init(struct machine_desc
*mdesc
)
826 * Allocate the vector page early.
828 vectors
= alloc_bootmem_low_pages(PAGE_SIZE
);
830 for (addr
= VMALLOC_END
; addr
; addr
+= PGDIR_SIZE
)
831 pmd_clear(pmd_off_k(addr
));
834 * Map the kernel if it is XIP.
835 * It is always first in the modulearea.
837 #ifdef CONFIG_XIP_KERNEL
838 map
.pfn
= __phys_to_pfn(CONFIG_XIP_PHYS_ADDR
& SECTION_MASK
);
839 map
.virtual = MODULES_VADDR
;
840 map
.length
= ((unsigned long)_etext
- map
.virtual + ~SECTION_MASK
) & SECTION_MASK
;
842 create_mapping(&map
);
846 * Map the cache flushing regions.
849 map
.pfn
= __phys_to_pfn(FLUSH_BASE_PHYS
);
850 map
.virtual = FLUSH_BASE
;
852 map
.type
= MT_CACHECLEAN
;
853 create_mapping(&map
);
855 #ifdef FLUSH_BASE_MINICACHE
856 map
.pfn
= __phys_to_pfn(FLUSH_BASE_PHYS
+ SZ_1M
);
857 map
.virtual = FLUSH_BASE_MINICACHE
;
859 map
.type
= MT_MINICLEAN
;
860 create_mapping(&map
);
864 * Create a mapping for the machine vectors at the high-vectors
865 * location (0xffff0000). If we aren't using high-vectors, also
866 * create a mapping at the low-vectors virtual address.
868 map
.pfn
= __phys_to_pfn(virt_to_phys(vectors
));
869 map
.virtual = 0xffff0000;
870 map
.length
= PAGE_SIZE
;
871 map
.type
= MT_HIGH_VECTORS
;
872 create_mapping(&map
);
874 if (!vectors_high()) {
876 map
.type
= MT_LOW_VECTORS
;
877 create_mapping(&map
);
881 * Ask the machine support to map in the statically mapped devices.
887 * Finally flush the caches and tlb to ensure that we're in a
888 * consistent state wrt the writebuffer. This also ensures that
889 * any write-allocated cache lines in the vector page are written
890 * back. After this point, we can start to touch devices again.
892 local_flush_tlb_all();
897 * paging_init() sets up the page tables, initialises the zone memory
898 * maps, and sets up the zero page, bad page and bad page tables.
900 void __init
paging_init(struct machine_desc
*mdesc
)
904 build_mem_type_table();
905 sanity_check_meminfo();
906 prepare_page_table();
908 devicemaps_init(mdesc
);
910 top_pmd
= pmd_off_k(0xffff0000);
913 * allocate the zero page. Note that this always succeeds and
914 * returns a zeroed result.
916 zero_page
= alloc_bootmem_low_pages(PAGE_SIZE
);
917 empty_zero_page
= virt_to_page(zero_page
);
918 flush_dcache_page(empty_zero_page
);
922 * In order to soft-boot, we need to insert a 1:1 mapping in place of
923 * the user-mode pages. This will then ensure that we have predictable
924 * results when turning the mmu off
926 void setup_mm_for_reboot(char mode
)
928 unsigned long base_pmdval
;
932 if (current
->mm
&& current
->mm
->pgd
)
933 pgd
= current
->mm
->pgd
;
937 base_pmdval
= PMD_SECT_AP_WRITE
| PMD_SECT_AP_READ
| PMD_TYPE_SECT
;
938 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ
&& !cpu_is_xscale())
939 base_pmdval
|= PMD_BIT4
;
941 for (i
= 0; i
< FIRST_USER_PGD_NR
+ USER_PTRS_PER_PGD
; i
++, pgd
++) {
942 unsigned long pmdval
= (i
<< PGDIR_SHIFT
) | base_pmdval
;
945 pmd
= pmd_off(pgd
, i
<< PGDIR_SHIFT
);
946 pmd
[0] = __pmd(pmdval
);
947 pmd
[1] = __pmd(pmdval
+ (1 << (PGDIR_SHIFT
- 1)));
948 flush_pmd_entry(pmd
);