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added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / arch / arm / mach-versatile / core.c
blob1c43494f5c422092d713a860e1623e83078b9d05
1 /*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29 #include <linux/clocksource.h>
30 #include <linux/clockchips.h>
31 #include <linux/cnt32_to_63.h>
32 #include <linux/io.h>
33
34 #include <asm/clkdev.h>
35 #include <asm/system.h>
36 #include <mach/hardware.h>
37 #include <asm/irq.h>
38 #include <asm/leds.h>
39 #include <asm/hardware/arm_timer.h>
40 #include <asm/hardware/icst307.h>
41 #include <asm/hardware/vic.h>
42 #include <asm/mach-types.h>
43
44 #include <asm/mach/arch.h>
45 #include <asm/mach/flash.h>
46 #include <asm/mach/irq.h>
47 #include <asm/mach/time.h>
48 #include <asm/mach/map.h>
49 #include <asm/mach/mmc.h>
50
51 #include "core.h"
52 #include "clock.h"
53
54 /*
55 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
56 * is the (PA >> 12).
57 *
58 * Setup a VA for the Versatile Vectored Interrupt Controller.
59 */
60 #define __io_address(n) __io(IO_ADDRESS(n))
61 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
62 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
63
64 static void sic_mask_irq(unsigned int irq)
65 {
66 irq -= IRQ_SIC_START;
67 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
68 }
69
70 static void sic_unmask_irq(unsigned int irq)
71 {
72 irq -= IRQ_SIC_START;
73 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
74 }
75
76 static struct irq_chip sic_chip = {
77 .name = "SIC",
78 .ack = sic_mask_irq,
79 .mask = sic_mask_irq,
80 .unmask = sic_unmask_irq,
81 };
82
83 static void
84 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
85 {
86 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
87
88 if (status == 0) {
89 do_bad_IRQ(irq, desc);
90 return;
91 }
92
93 do {
94 irq = ffs(status) - 1;
95 status &= ~(1 << irq);
96
97 irq += IRQ_SIC_START;
98
99 generic_handle_irq(irq);
100 } while (status);
101 }
102
103 #if 1
104 #define IRQ_MMCI0A IRQ_VICSOURCE22
105 #define IRQ_AACI IRQ_VICSOURCE24
106 #define IRQ_ETH IRQ_VICSOURCE25
107 #define PIC_MASK 0xFFD00000
108 #else
109 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
110 #define IRQ_AACI IRQ_SIC_AACI
111 #define IRQ_ETH IRQ_SIC_ETH
112 #define PIC_MASK 0
113 #endif
114
115 void __init versatile_init_irq(void)
116 {
117 unsigned int i;
118
119 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
120
121 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
122
123 /* Do second interrupt controller */
124 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
125
126 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
127 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
128 set_irq_chip(i, &sic_chip);
129 set_irq_handler(i, handle_level_irq);
130 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
131 }
132 }
133
134 /*
135 * Interrupts on secondary controller from 0 to 8 are routed to
136 * source 31 on PIC.
137 * Interrupts from 21 to 31 are routed directly to the VIC on
138 * the corresponding number on primary controller. This is controlled
139 * by setting PIC_ENABLEx.
140 */
141 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
142 }
143
144 static struct map_desc versatile_io_desc[] __initdata = {
145 {
146 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
147 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
148 .length = SZ_4K,
149 .type = MT_DEVICE
150 }, {
151 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
152 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
153 .length = SZ_4K,
154 .type = MT_DEVICE
155 }, {
156 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
157 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
158 .length = SZ_4K,
159 .type = MT_DEVICE
160 }, {
161 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
162 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
163 .length = SZ_4K * 9,
164 .type = MT_DEVICE
165 },
166 #ifdef CONFIG_MACH_VERSATILE_AB
167 {
168 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
169 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
170 .length = SZ_4K,
171 .type = MT_DEVICE
172 }, {
173 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
174 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
175 .length = SZ_64M,
176 .type = MT_DEVICE
177 },
178 #endif
179 #ifdef CONFIG_DEBUG_LL
180 {
181 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
182 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
183 .length = SZ_4K,
184 .type = MT_DEVICE
185 },
186 #endif
187 #ifdef CONFIG_PCI
188 {
189 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
190 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
191 .length = SZ_4K,
192 .type = MT_DEVICE
193 }, {
194 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
195 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
196 .length = VERSATILE_PCI_BASE_SIZE,
197 .type = MT_DEVICE
198 }, {
199 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
200 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
201 .length = VERSATILE_PCI_CFG_BASE_SIZE,
202 .type = MT_DEVICE
203 },
204 #if 0
205 {
206 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
207 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
208 .length = SZ_16M,
209 .type = MT_DEVICE
210 }, {
211 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
212 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
213 .length = SZ_16M,
214 .type = MT_DEVICE
215 }, {
216 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
217 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
218 .length = SZ_16M,
219 .type = MT_DEVICE
220 },
221 #endif
222 #endif
223 };
224
225 void __init versatile_map_io(void)
226 {
227 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
228 }
229
230 #define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
231
232 /*
233 * This is the Versatile sched_clock implementation. This has
234 * a resolution of 41.7ns, and a maximum value of about 35583 days.
235 *
236 * The return value is guaranteed to be monotonic in that range as
237 * long as there is always less than 89 seconds between successive
238 * calls to this function.
239 */
240 unsigned long long sched_clock(void)
241 {
242 unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER));
243
244 /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
245 v *= 125<<1;
246 do_div(v, 3<<1);
247
248 return v;
249 }
250
251
252 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
253
254 static int versatile_flash_init(void)
255 {
256 u32 val;
257
258 val = __raw_readl(VERSATILE_FLASHCTRL);
259 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
260 __raw_writel(val, VERSATILE_FLASHCTRL);
261
262 return 0;
263 }
264
265 static void versatile_flash_exit(void)
266 {
267 u32 val;
268
269 val = __raw_readl(VERSATILE_FLASHCTRL);
270 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
271 __raw_writel(val, VERSATILE_FLASHCTRL);
272 }
273
274 static void versatile_flash_set_vpp(int on)
275 {
276 u32 val;
277
278 val = __raw_readl(VERSATILE_FLASHCTRL);
279 if (on)
280 val |= VERSATILE_FLASHPROG_FLVPPEN;
281 else
282 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
283 __raw_writel(val, VERSATILE_FLASHCTRL);
284 }
285
286 static struct flash_platform_data versatile_flash_data = {
287 .map_name = "cfi_probe",
288 .width = 4,
289 .init = versatile_flash_init,
290 .exit = versatile_flash_exit,
291 .set_vpp = versatile_flash_set_vpp,
292 };
293
294 static struct resource versatile_flash_resource = {
295 .start = VERSATILE_FLASH_BASE,
296 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
297 .flags = IORESOURCE_MEM,
298 };
299
300 static struct platform_device versatile_flash_device = {
301 .name = "armflash",
302 .id = 0,
303 .dev = {
304 .platform_data = &versatile_flash_data,
305 },
306 .num_resources = 1,
307 .resource = &versatile_flash_resource,
308 };
309
310 static struct resource smc91x_resources[] = {
311 [0] = {
312 .start = VERSATILE_ETH_BASE,
313 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
314 .flags = IORESOURCE_MEM,
315 },
316 [1] = {
317 .start = IRQ_ETH,
318 .end = IRQ_ETH,
319 .flags = IORESOURCE_IRQ,
320 },
321 };
322
323 static struct platform_device smc91x_device = {
324 .name = "smc91x",
325 .id = 0,
326 .num_resources = ARRAY_SIZE(smc91x_resources),
327 .resource = smc91x_resources,
328 };
329
330 static struct resource versatile_i2c_resource = {
331 .start = VERSATILE_I2C_BASE,
332 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
333 .flags = IORESOURCE_MEM,
334 };
335
336 static struct platform_device versatile_i2c_device = {
337 .name = "versatile-i2c",
338 .id = -1,
339 .num_resources = 1,
340 .resource = &versatile_i2c_resource,
341 };
342
343 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
344
345 unsigned int mmc_status(struct device *dev)
346 {
347 struct amba_device *adev = container_of(dev, struct amba_device, dev);
348 u32 mask;
349
350 if (adev->res.start == VERSATILE_MMCI0_BASE)
351 mask = 1;
352 else
353 mask = 2;
354
355 return readl(VERSATILE_SYSMCI) & mask;
356 }
357
358 static struct mmc_platform_data mmc0_plat_data = {
359 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
360 .status = mmc_status,
361 };
362
363 /*
364 * Clock handling
365 */
366 static const struct icst307_params versatile_oscvco_params = {
367 .ref = 24000,
368 .vco_max = 200000,
369 .vd_min = 4 + 8,
370 .vd_max = 511 + 8,
371 .rd_min = 1 + 2,
372 .rd_max = 127 + 2,
373 };
374
375 static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
376 {
377 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
378 void __iomem *sys_lock = sys + VERSATILE_SYS_LOCK_OFFSET;
379 u32 val;
380
381 val = readl(sys + clk->oscoff) & ~0x7ffff;
382 val |= vco.v | (vco.r << 9) | (vco.s << 16);
383
384 writel(0xa05f, sys_lock);
385 writel(val, sys + clk->oscoff);
386 writel(0, sys_lock);
387 }
388
389 static struct clk osc4_clk = {
390 .params = &versatile_oscvco_params,
391 .oscoff = VERSATILE_SYS_OSCCLCD_OFFSET,
392 .setvco = versatile_oscvco_set,
393 };
394
395 /*
396 * These are fixed clocks.
397 */
398 static struct clk ref24_clk = {
399 .rate = 24000000,
400 };
401
402 static struct clk_lookup lookups[] __initdata = {
403 { /* UART0 */
404 .dev_id = "dev:f1",
405 .clk = &ref24_clk,
406 }, { /* UART1 */
407 .dev_id = "dev:f2",
408 .clk = &ref24_clk,
409 }, { /* UART2 */
410 .dev_id = "dev:f3",
411 .clk = &ref24_clk,
412 }, { /* UART3 */
413 .dev_id = "fpga:09",
414 .clk = &ref24_clk,
415 }, { /* KMI0 */
416 .dev_id = "fpga:06",
417 .clk = &ref24_clk,
418 }, { /* KMI1 */
419 .dev_id = "fpga:07",
420 .clk = &ref24_clk,
421 }, { /* MMC0 */
422 .dev_id = "fpga:05",
423 .clk = &ref24_clk,
424 }, { /* MMC1 */
425 .dev_id = "fpga:0b",
426 .clk = &ref24_clk,
427 }, { /* CLCD */
428 .dev_id = "dev:20",
429 .clk = &osc4_clk,
430 }
431 };
432
433 /*
434 * CLCD support.
435 */
436 #define SYS_CLCD_MODE_MASK (3 << 0)
437 #define SYS_CLCD_MODE_888 (0 << 0)
438 #define SYS_CLCD_MODE_5551 (1 << 0)
439 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
440 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
441 #define SYS_CLCD_NLCDIOON (1 << 2)
442 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
443 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
444 #define SYS_CLCD_ID_MASK (0x1f << 8)
445 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
446 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
447 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
448 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
449 #define SYS_CLCD_ID_VGA (0x1f << 8)
450
451 static struct clcd_panel vga = {
452 .mode = {
453 .name = "VGA",
454 .refresh = 60,
455 .xres = 640,
456 .yres = 480,
457 .pixclock = 39721,
458 .left_margin = 40,
459 .right_margin = 24,
460 .upper_margin = 32,
461 .lower_margin = 11,
462 .hsync_len = 96,
463 .vsync_len = 2,
464 .sync = 0,
465 .vmode = FB_VMODE_NONINTERLACED,
466 },
467 .width = -1,
468 .height = -1,
469 .tim2 = TIM2_BCD | TIM2_IPC,
470 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
471 .bpp = 16,
472 };
473
474 static struct clcd_panel sanyo_3_8_in = {
475 .mode = {
476 .name = "Sanyo QVGA",
477 .refresh = 116,
478 .xres = 320,
479 .yres = 240,
480 .pixclock = 100000,
481 .left_margin = 6,
482 .right_margin = 6,
483 .upper_margin = 5,
484 .lower_margin = 5,
485 .hsync_len = 6,
486 .vsync_len = 6,
487 .sync = 0,
488 .vmode = FB_VMODE_NONINTERLACED,
489 },
490 .width = -1,
491 .height = -1,
492 .tim2 = TIM2_BCD,
493 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
494 .bpp = 16,
495 };
496
497 static struct clcd_panel sanyo_2_5_in = {
498 .mode = {
499 .name = "Sanyo QVGA Portrait",
500 .refresh = 116,
501 .xres = 240,
502 .yres = 320,
503 .pixclock = 100000,
504 .left_margin = 20,
505 .right_margin = 10,
506 .upper_margin = 2,
507 .lower_margin = 2,
508 .hsync_len = 10,
509 .vsync_len = 2,
510 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
511 .vmode = FB_VMODE_NONINTERLACED,
512 },
513 .width = -1,
514 .height = -1,
515 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
516 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
517 .bpp = 16,
518 };
519
520 static struct clcd_panel epson_2_2_in = {
521 .mode = {
522 .name = "Epson QCIF",
523 .refresh = 390,
524 .xres = 176,
525 .yres = 220,
526 .pixclock = 62500,
527 .left_margin = 3,
528 .right_margin = 2,
529 .upper_margin = 1,
530 .lower_margin = 0,
531 .hsync_len = 3,
532 .vsync_len = 2,
533 .sync = 0,
534 .vmode = FB_VMODE_NONINTERLACED,
535 },
536 .width = -1,
537 .height = -1,
538 .tim2 = TIM2_BCD | TIM2_IPC,
539 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
540 .bpp = 16,
541 };
542
543 /*
544 * Detect which LCD panel is connected, and return the appropriate
545 * clcd_panel structure. Note: we do not have any information on
546 * the required timings for the 8.4in panel, so we presently assume
547 * VGA timings.
548 */
549 static struct clcd_panel *versatile_clcd_panel(void)
550 {
551 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
552 struct clcd_panel *panel = &vga;
553 u32 val;
554
555 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
556 if (val == SYS_CLCD_ID_SANYO_3_8)
557 panel = &sanyo_3_8_in;
558 else if (val == SYS_CLCD_ID_SANYO_2_5)
559 panel = &sanyo_2_5_in;
560 else if (val == SYS_CLCD_ID_EPSON_2_2)
561 panel = &epson_2_2_in;
562 else if (val == SYS_CLCD_ID_VGA)
563 panel = &vga;
564 else {
565 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
566 val);
567 panel = &vga;
568 }
569
570 return panel;
571 }
572
573 /*
574 * Disable all display connectors on the interface module.
575 */
576 static void versatile_clcd_disable(struct clcd_fb *fb)
577 {
578 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
579 u32 val;
580
581 val = readl(sys_clcd);
582 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
583 writel(val, sys_clcd);
584
585 #ifdef CONFIG_MACH_VERSATILE_AB
586 /*
587 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
588 */
589 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
590 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
591 unsigned long ctrl;
592
593 ctrl = readl(versatile_ib2_ctrl);
594 ctrl &= ~0x01;
595 writel(ctrl, versatile_ib2_ctrl);
596 }
597 #endif
598 }
599
600 /*
601 * Enable the relevant connector on the interface module.
602 */
603 static void versatile_clcd_enable(struct clcd_fb *fb)
604 {
605 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
606 u32 val;
607
608 val = readl(sys_clcd);
609 val &= ~SYS_CLCD_MODE_MASK;
610
611 switch (fb->fb.var.green.length) {
612 case 5:
613 val |= SYS_CLCD_MODE_5551;
614 break;
615 case 6:
616 val |= SYS_CLCD_MODE_565_RLSB;
617 break;
618 case 8:
619 val |= SYS_CLCD_MODE_888;
620 break;
621 }
622
623 /*
624 * Set the MUX
625 */
626 writel(val, sys_clcd);
627
628 /*
629 * And now enable the PSUs
630 */
631 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
632 writel(val, sys_clcd);
633
634 #ifdef CONFIG_MACH_VERSATILE_AB
635 /*
636 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
637 */
638 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
639 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
640 unsigned long ctrl;
641
642 ctrl = readl(versatile_ib2_ctrl);
643 ctrl |= 0x01;
644 writel(ctrl, versatile_ib2_ctrl);
645 }
646 #endif
647 }
648
649 static unsigned long framesize = SZ_1M;
650
651 static int versatile_clcd_setup(struct clcd_fb *fb)
652 {
653 dma_addr_t dma;
654
655 fb->panel = versatile_clcd_panel();
656
657 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
658 &dma, GFP_KERNEL);
659 if (!fb->fb.screen_base) {
660 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
661 return -ENOMEM;
662 }
663
664 fb->fb.fix.smem_start = dma;
665 fb->fb.fix.smem_len = framesize;
666
667 return 0;
668 }
669
670 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
671 {
672 return dma_mmap_writecombine(&fb->dev->dev, vma,
673 fb->fb.screen_base,
674 fb->fb.fix.smem_start,
675 fb->fb.fix.smem_len);
676 }
677
678 static void versatile_clcd_remove(struct clcd_fb *fb)
679 {
680 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
681 fb->fb.screen_base, fb->fb.fix.smem_start);
682 }
683
684 static struct clcd_board clcd_plat_data = {
685 .name = "Versatile",
686 .check = clcdfb_check,
687 .decode = clcdfb_decode,
688 .disable = versatile_clcd_disable,
689 .enable = versatile_clcd_enable,
690 .setup = versatile_clcd_setup,
691 .mmap = versatile_clcd_mmap,
692 .remove = versatile_clcd_remove,
693 };
694
695 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
696 #define AACI_DMA { 0x80, 0x81 }
697 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
698 #define MMCI0_DMA { 0x84, 0 }
699 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
700 #define KMI0_DMA { 0, 0 }
701 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
702 #define KMI1_DMA { 0, 0 }
703
704 /*
705 * These devices are connected directly to the multi-layer AHB switch
706 */
707 #define SMC_IRQ { NO_IRQ, NO_IRQ }
708 #define SMC_DMA { 0, 0 }
709 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
710 #define MPMC_DMA { 0, 0 }
711 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
712 #define CLCD_DMA { 0, 0 }
713 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
714 #define DMAC_DMA { 0, 0 }
715
716 /*
717 * These devices are connected via the core APB bridge
718 */
719 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
720 #define SCTL_DMA { 0, 0 }
721 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
722 #define WATCHDOG_DMA { 0, 0 }
723 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
724 #define GPIO0_DMA { 0, 0 }
725 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
726 #define GPIO1_DMA { 0, 0 }
727 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
728 #define RTC_DMA { 0, 0 }
729
730 /*
731 * These devices are connected via the DMA APB bridge
732 */
733 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
734 #define SCI_DMA { 7, 6 }
735 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
736 #define UART0_DMA { 15, 14 }
737 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
738 #define UART1_DMA { 13, 12 }
739 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
740 #define UART2_DMA { 11, 10 }
741 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
742 #define SSP_DMA { 9, 8 }
743
744 /* FPGA Primecells */
745 AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
746 AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
747 AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
748 AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
749
750 /* DevChip Primecells */
751 AMBA_DEVICE(smc, "dev:00", SMC, NULL);
752 AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
753 AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
754 AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
755 AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
756 AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
757 AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL);
758 AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
759 AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
760 AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
761 AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
762 AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
763 AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
764 AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
765
766 static struct amba_device *amba_devs[] __initdata = {
767 &dmac_device,
768 &uart0_device,
769 &uart1_device,
770 &uart2_device,
771 &smc_device,
772 &mpmc_device,
773 &clcd_device,
774 &sctl_device,
775 &wdog_device,
776 &gpio0_device,
777 &gpio1_device,
778 &rtc_device,
779 &sci0_device,
780 &ssp0_device,
781 &aaci_device,
782 &mmc0_device,
783 &kmi0_device,
784 &kmi1_device,
785 };
786
787 #ifdef CONFIG_LEDS
788 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
789
790 static void versatile_leds_event(led_event_t ledevt)
791 {
792 unsigned long flags;
793 u32 val;
794
795 local_irq_save(flags);
796 val = readl(VA_LEDS_BASE);
797
798 switch (ledevt) {
799 case led_idle_start:
800 val = val & ~VERSATILE_SYS_LED0;
801 break;
802
803 case led_idle_end:
804 val = val | VERSATILE_SYS_LED0;
805 break;
806
807 case led_timer:
808 val = val ^ VERSATILE_SYS_LED1;
809 break;
810
811 case led_halted:
812 val = 0;
813 break;
814
815 default:
816 break;
817 }
818
819 writel(val, VA_LEDS_BASE);
820 local_irq_restore(flags);
821 }
822 #endif /* CONFIG_LEDS */
823
824 void __init versatile_init(void)
825 {
826 int i;
827
828 for (i = 0; i < ARRAY_SIZE(lookups); i++)
829 clkdev_add(&lookups[i]);
830
831 platform_device_register(&versatile_flash_device);
832 platform_device_register(&versatile_i2c_device);
833 platform_device_register(&smc91x_device);
834
835 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
836 struct amba_device *d = amba_devs[i];
837 amba_device_register(d, &iomem_resource);
838 }
839
840 #ifdef CONFIG_LEDS
841 leds_event = versatile_leds_event;
842 #endif
843 }
844
845 /*
846 * Where is the timer (VA)?
847 */
848 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
849 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
850 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
851 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
852 #define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
853
854 /*
855 * How long is the timer interval?
856 */
857 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
858 #if TIMER_INTERVAL >= 0x100000
859 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
860 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
861 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
862 #elif TIMER_INTERVAL >= 0x10000
863 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
864 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
865 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
866 #else
867 #define TIMER_RELOAD (TIMER_INTERVAL)
868 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
869 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
870 #endif
871
872 static void timer_set_mode(enum clock_event_mode mode,
873 struct clock_event_device *clk)
874 {
875 unsigned long ctrl;
876
877 switch(mode) {
878 case CLOCK_EVT_MODE_PERIODIC:
879 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
880
881 ctrl = TIMER_CTRL_PERIODIC;
882 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
883 break;
884 case CLOCK_EVT_MODE_ONESHOT:
885 /* period set, and timer enabled in 'next_event' hook */
886 ctrl = TIMER_CTRL_ONESHOT;
887 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
888 break;
889 case CLOCK_EVT_MODE_UNUSED:
890 case CLOCK_EVT_MODE_SHUTDOWN:
891 default:
892 ctrl = 0;
893 }
894
895 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
896 }
897
898 static int timer_set_next_event(unsigned long evt,
899 struct clock_event_device *unused)
900 {
901 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
902
903 writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
904 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
905
906 return 0;
907 }
908
909 static struct clock_event_device timer0_clockevent = {
910 .name = "timer0",
911 .shift = 32,
912 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
913 .set_mode = timer_set_mode,
914 .set_next_event = timer_set_next_event,
915 };
916
917 /*
918 * IRQ handler for the timer
919 */
920 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
921 {
922 struct clock_event_device *evt = &timer0_clockevent;
923
924 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
925
926 evt->event_handler(evt);
927
928 return IRQ_HANDLED;
929 }
930
931 static struct irqaction versatile_timer_irq = {
932 .name = "Versatile Timer Tick",
933 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
934 .handler = versatile_timer_interrupt,
935 };
936
937 static cycle_t versatile_get_cycles(void)
938 {
939 return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
940 }
941
942 static struct clocksource clocksource_versatile = {
943 .name = "timer3",
944 .rating = 200,
945 .read = versatile_get_cycles,
946 .mask = CLOCKSOURCE_MASK(32),
947 .shift = 20,
948 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
949 };
950
951 static int __init versatile_clocksource_init(void)
952 {
953 /* setup timer3 as free-running clocksource */
954 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
955 writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
956 writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
957 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
958 TIMER3_VA_BASE + TIMER_CTRL);
959
960 clocksource_versatile.mult =
961 clocksource_khz2mult(1000, clocksource_versatile.shift);
962 clocksource_register(&clocksource_versatile);
963
964 return 0;
965 }
966
967 /*
968 * Set up timer interrupt, and return the current time in seconds.
969 */
970 static void __init versatile_timer_init(void)
971 {
972 u32 val;
973
974 /*
975 * set clock frequency:
976 * VERSATILE_REFCLK is 32KHz
977 * VERSATILE_TIMCLK is 1MHz
978 */
979 val = readl(__io_address(VERSATILE_SCTL_BASE));
980 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
981 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
982 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
983 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
984 __io_address(VERSATILE_SCTL_BASE));
985
986 /*
987 * Initialise to a known state (all timers off)
988 */
989 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
990 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
991 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
992 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
993
994 /*
995 * Make irqs happen for the system timer
996 */
997 setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
998
999 versatile_clocksource_init();
1000
1001 timer0_clockevent.mult =
1002 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
1003 timer0_clockevent.max_delta_ns =
1004 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
1005 timer0_clockevent.min_delta_ns =
1006 clockevent_delta2ns(0xf, &timer0_clockevent);
1007
1008 timer0_clockevent.cpumask = cpumask_of(0);
1009 clockevents_register_device(&timer0_clockevent);
1010 }
1011
1012 struct sys_timer versatile_timer = {
1013 .init = versatile_timer_init,
1014 };
1015
Nao low-level kernelspace/userspace library that runs on our robots, Nao-Team HTWK