4 * Copyright (C) 2006 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
19 /* interrupt sources */
20 IRL0
, IRL1
, IRL2
, IRL3
,
22 DMAC_DMTE0
, DMAC_DMTE1
, DMAC_DMTE2
, DMAC_DMTE3
,
23 DMAC_DMTE4
, DMAC_DMTE5
, DMAC_DMTE6
, DMAC_DMTE7
,
25 IRQ4
, IRQ5
, IRQ6
, IRQ7
,
31 DMABRG0
, DMABRG1
, DMABRG2
,
32 SCIF0_ERI
, SCIF0_RXI
, SCIF0_BRI
, SCIF0_TXI
,
33 SCIF1_ERI
, SCIF1_RXI
, SCIF1_BRI
, SCIF1_TXI
,
34 SCIF2_ERI
, SCIF2_RXI
, SCIF2_BRI
, SCIF2_TXI
,
35 SIM_ERI
, SIM_RXI
, SIM_TXI
, SIM_TEI
,
37 MMCIF0
, MMCIF1
, MMCIF2
, MMCIF3
,
39 TMU0
, TMU1
, TMU2_TUNI
, TMU2_TICPI
,
43 /* interrupt groups */
44 DMAC
, DMABRG
, SCIF0
, SCIF1
, SCIF2
, SIM
, MMCIF
, TMU2
, REF
,
47 static struct intc_vect vectors
[] __initdata
= {
48 INTC_VECT(HUDI
, 0x600), INTC_VECT(GPIOI
, 0x620),
49 INTC_VECT(DMAC_DMTE0
, 0x640), INTC_VECT(DMAC_DMTE1
, 0x660),
50 INTC_VECT(DMAC_DMTE2
, 0x680), INTC_VECT(DMAC_DMTE3
, 0x6a0),
51 INTC_VECT(DMAC_DMTE4
, 0x780), INTC_VECT(DMAC_DMTE5
, 0x7a0),
52 INTC_VECT(DMAC_DMTE6
, 0x7c0), INTC_VECT(DMAC_DMTE7
, 0x7e0),
53 INTC_VECT(DMAC_DMAE
, 0x6c0),
54 INTC_VECT(IRQ4
, 0x800), INTC_VECT(IRQ5
, 0x820),
55 INTC_VECT(IRQ6
, 0x840), INTC_VECT(IRQ6
, 0x860),
56 INTC_VECT(HCAN20
, 0x900), INTC_VECT(HCAN21
, 0x920),
57 INTC_VECT(SSI0
, 0x940), INTC_VECT(SSI1
, 0x960),
58 INTC_VECT(HAC0
, 0x980), INTC_VECT(HAC1
, 0x9a0),
59 INTC_VECT(I2C0
, 0x9c0), INTC_VECT(I2C1
, 0x9e0),
60 INTC_VECT(USB
, 0xa00), INTC_VECT(LCDC
, 0xa20),
61 INTC_VECT(DMABRG0
, 0xa80), INTC_VECT(DMABRG1
, 0xaa0),
62 INTC_VECT(DMABRG2
, 0xac0),
63 INTC_VECT(SCIF0_ERI
, 0x880), INTC_VECT(SCIF0_RXI
, 0x8a0),
64 INTC_VECT(SCIF0_BRI
, 0x8c0), INTC_VECT(SCIF0_TXI
, 0x8e0),
65 INTC_VECT(SCIF1_ERI
, 0xb00), INTC_VECT(SCIF1_RXI
, 0xb20),
66 INTC_VECT(SCIF1_BRI
, 0xb40), INTC_VECT(SCIF1_TXI
, 0xb60),
67 INTC_VECT(SCIF2_ERI
, 0xb80), INTC_VECT(SCIF2_RXI
, 0xba0),
68 INTC_VECT(SCIF2_BRI
, 0xbc0), INTC_VECT(SCIF2_TXI
, 0xbe0),
69 INTC_VECT(SIM_ERI
, 0xc00), INTC_VECT(SIM_RXI
, 0xc20),
70 INTC_VECT(SIM_TXI
, 0xc40), INTC_VECT(SIM_TEI
, 0xc60),
71 INTC_VECT(HSPI
, 0xc80),
72 INTC_VECT(MMCIF0
, 0xd00), INTC_VECT(MMCIF1
, 0xd20),
73 INTC_VECT(MMCIF2
, 0xd40), INTC_VECT(MMCIF3
, 0xd60),
74 INTC_VECT(MFI
, 0xe80), /* 0xf80 according to data sheet */
75 INTC_VECT(ADC
, 0xf80), INTC_VECT(CMT
, 0xfa0),
76 INTC_VECT(TMU0
, 0x400), INTC_VECT(TMU1
, 0x420),
77 INTC_VECT(TMU2_TUNI
, 0x440), INTC_VECT(TMU2_TICPI
, 0x460),
78 INTC_VECT(WDT
, 0x560),
79 INTC_VECT(REF_RCMI
, 0x580), INTC_VECT(REF_ROVI
, 0x5a0),
82 static struct intc_group groups
[] __initdata
= {
83 INTC_GROUP(DMAC
, DMAC_DMTE0
, DMAC_DMTE1
, DMAC_DMTE2
,
84 DMAC_DMTE3
, DMAC_DMTE4
, DMAC_DMTE5
,
85 DMAC_DMTE6
, DMAC_DMTE7
, DMAC_DMAE
),
86 INTC_GROUP(DMABRG
, DMABRG0
, DMABRG1
, DMABRG2
),
87 INTC_GROUP(SCIF0
, SCIF0_ERI
, SCIF0_RXI
, SCIF0_BRI
, SCIF0_TXI
),
88 INTC_GROUP(SCIF1
, SCIF1_ERI
, SCIF1_RXI
, SCIF1_BRI
, SCIF1_TXI
),
89 INTC_GROUP(SCIF2
, SCIF2_ERI
, SCIF2_RXI
, SCIF2_BRI
, SCIF2_TXI
),
90 INTC_GROUP(SIM
, SIM_ERI
, SIM_RXI
, SIM_TXI
, SIM_TEI
),
91 INTC_GROUP(MMCIF
, MMCIF0
, MMCIF1
, MMCIF2
, MMCIF3
),
92 INTC_GROUP(TMU2
, TMU2_TUNI
, TMU2_TICPI
),
93 INTC_GROUP(REF
, REF_RCMI
, REF_ROVI
),
96 static struct intc_mask_reg mask_registers
[] __initdata
= {
97 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
98 { IRQ4
, IRQ5
, IRQ6
, IRQ7
, 0, 0, HCAN20
, HCAN21
,
99 SSI0
, SSI1
, HAC0
, HAC1
, I2C0
, I2C1
, USB
, LCDC
,
100 0, DMABRG0
, DMABRG1
, DMABRG2
,
101 SCIF0_ERI
, SCIF0_RXI
, SCIF0_BRI
, SCIF0_TXI
,
102 SCIF1_ERI
, SCIF1_RXI
, SCIF1_BRI
, SCIF1_TXI
,
103 SCIF2_ERI
, SCIF2_RXI
, SCIF2_BRI
, SCIF2_TXI
, } },
104 { 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */
105 { 0, 0, 0, 0, 0, 0, 0, 0,
106 SIM_ERI
, SIM_RXI
, SIM_TXI
, SIM_TEI
,
107 HSPI
, MMCIF0
, MMCIF1
, MMCIF2
,
108 MMCIF3
, 0, 0, 0, 0, 0, 0, 0,
109 0, MFI
, 0, 0, 0, 0, ADC
, CMT
, } },
112 static struct intc_prio_reg prio_registers
[] __initdata
= {
113 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0
, TMU1
, TMU2
} },
114 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT
, REF
, 0, 0 } },
115 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI
, DMAC
, 0, HUDI
} },
116 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0
, IRL1
, IRL2
, IRL3
} },
117 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
118 { 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20
, HCAN21
, SSI0
, SSI1
,
119 HAC0
, HAC1
, I2C0
, I2C1
} },
120 { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB
, LCDC
, DMABRG
, SCIF0
,
121 SCIF1
, SCIF2
, SIM
, HSPI
} },
122 { 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF
, 0,
123 MFI
, 0, ADC
, CMT
} },
126 static DECLARE_INTC_DESC(intc_desc
, "sh7760", vectors
, groups
,
127 mask_registers
, prio_registers
, NULL
);
129 static struct intc_vect vectors_irq
[] __initdata
= {
130 INTC_VECT(IRL0
, 0x240), INTC_VECT(IRL1
, 0x2a0),
131 INTC_VECT(IRL2
, 0x300), INTC_VECT(IRL3
, 0x360),
134 static DECLARE_INTC_DESC(intc_desc_irq
, "sh7760-irq", vectors_irq
, groups
,
135 mask_registers
, prio_registers
, NULL
);
137 static struct plat_sci_port sci_platform_data
[] = {
139 .mapbase
= 0xfe600000,
140 .flags
= UPF_BOOT_AUTOCONF
,
142 .irqs
= { 52, 53, 55, 54 },
144 .mapbase
= 0xfe610000,
145 .flags
= UPF_BOOT_AUTOCONF
,
147 .irqs
= { 72, 73, 75, 74 },
149 .mapbase
= 0xfe620000,
150 .flags
= UPF_BOOT_AUTOCONF
,
152 .irqs
= { 76, 77, 79, 78 },
154 .mapbase
= 0xfe480000,
155 .flags
= UPF_BOOT_AUTOCONF
,
157 .irqs
= { 80, 81, 82, 0 },
163 static struct platform_device sci_device
= {
167 .platform_data
= sci_platform_data
,
171 static struct platform_device
*sh7760_devices
[] __initdata
= {
175 static int __init
sh7760_devices_setup(void)
177 return platform_add_devices(sh7760_devices
,
178 ARRAY_SIZE(sh7760_devices
));
180 __initcall(sh7760_devices_setup
);
182 #define INTC_ICR 0xffd00000UL
183 #define INTC_ICR_IRLM (1 << 7)
185 void __init
plat_irq_setup_pins(int mode
)
189 ctrl_outw(ctrl_inw(INTC_ICR
) | INTC_ICR_IRLM
, INTC_ICR
);
190 register_intc_controller(&intc_desc_irq
);
197 void __init
plat_irq_setup(void)
199 register_intc_controller(&intc_desc
);