kernel/2.6.29.6-aldebaran-rt/arch/sh/include/cpu-sh3/cpu/cacheflush.h

   1 /*
   2  * include/asm-sh/cpu-sh3/cacheflush.h
   3  *
   4  * Copyright (C) 1999 Niibe Yutaka
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #ifndef __ASM_CPU_SH3_CACHEFLUSH_H
  11 #define __ASM_CPU_SH3_CACHEFLUSH_H
  12
  13 #if defined(CONFIG_SH7705_CACHE_32KB)
  14 /* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the
  15  * SH4. Unlike the SH4 this is a unified cache so we need to do some work
  16  * in mmap when 'exec'ing a new binary
  17  */
  18  /* 32KB cache, 4kb PAGE sizes need to check bit 12 */
  19 #define CACHE_ALIAS 0x00001000
  20
  21 #define PG_mapped       PG_arch_1
  22
  23 void flush_cache_all(void);
  24 void flush_cache_mm(struct mm_struct *mm);
  25 #define flush_cache_dup_mm(mm) flush_cache_mm(mm)
  26 void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
  27                               unsigned long end);
  28 void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
  29 void flush_dcache_page(struct page *pg);
  30 void flush_icache_range(unsigned long start, unsigned long end);
  31 void flush_icache_page(struct vm_area_struct *vma, struct page *page);
  32
  33 #define flush_dcache_mmap_lock(mapping)         do { } while (0)
  34 #define flush_dcache_mmap_unlock(mapping)       do { } while (0)
  35
  36 /* SH3 has unified cache so no special action needed here */
  37 #define flush_cache_sigtramp(vaddr)             do { } while (0)
  38 #define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
  39
  40 #define p3_cache_init()                         do { } while (0)
  41
  42 #else
  43 #include <cpu-common/cpu/cacheflush.h>
  44 #endif
  45
  46 #endif /* __ASM_CPU_SH3_CACHEFLUSH_H */