kernel/2.6.29.6-aldebaran-rt/arch/arm/mach-davinci/gpio.c

   1 /*
   2  * TI DaVinci GPIO Support
   3  *
   4  * Copyright (c) 2006-2007 David Brownell
   5  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/errno.h>
  14 #include <linux/kernel.h>
  15 #include <linux/list.h>
  16 #include <linux/module.h>
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20 #include <linux/irq.h>
  21 #include <linux/bitops.h>
  22
  23 #include <mach/irqs.h>
  24 #include <mach/hardware.h>
  25 #include <mach/gpio.h>
  26
  27 #include <asm/mach/irq.h>
  28
  29
  30 static DEFINE_SPINLOCK(gpio_lock);
  31
  32 struct davinci_gpio {
  33         struct gpio_chip        chip;
  34         struct gpio_controller  *__iomem regs;
  35 };
  36
  37 static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
  38
  39
  40 /* create a non-inlined version */
  41 static struct gpio_controller *__iomem __init gpio2controller(unsigned gpio)
  42 {
  43         return __gpio_to_controller(gpio);
  44 }
  45
  46
  47 /*--------------------------------------------------------------------------*/
  48
  49 /*
  50  * board setup code *MUST* set PINMUX0 and PINMUX1 as
  51  * needed, and enable the GPIO clock.
  52  */
  53
  54 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
  55 {
  56         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
  57         struct gpio_controller *__iomem g = d->regs;
  58         u32 temp;
  59
  60         spin_lock(&gpio_lock);
  61         temp = __raw_readl(&g->dir);
  62         temp |= (1 << offset);
  63         __raw_writel(temp, &g->dir);
  64         spin_unlock(&gpio_lock);
  65
  66         return 0;
  67 }
  68
  69 /*
  70  * Read the pin's value (works even if it's set up as output);
  71  * returns zero/nonzero.
  72  *
  73  * Note that changes are synched to the GPIO clock, so reading values back
  74  * right after you've set them may give old values.
  75  */
  76 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
  77 {
  78         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
  79         struct gpio_controller *__iomem g = d->regs;
  80
  81         return (1 << offset) & __raw_readl(&g->in_data);
  82 }
  83
  84 static int
  85 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
  86 {
  87         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
  88         struct gpio_controller *__iomem g = d->regs;
  89         u32 temp;
  90         u32 mask = 1 << offset;
  91
  92         spin_lock(&gpio_lock);
  93         temp = __raw_readl(&g->dir);
  94         temp &= ~mask;
  95         __raw_writel(mask, value ? &g->set_data : &g->clr_data);
  96         __raw_writel(temp, &g->dir);
  97         spin_unlock(&gpio_lock);
  98         return 0;
  99 }
 100
 101 /*
 102  * Assuming the pin is muxed as a gpio output, set its output value.
 103  */
 104 static void
 105 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 106 {
 107         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
 108         struct gpio_controller *__iomem g = d->regs;
 109
 110         __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
 111 }
 112
 113 static int __init davinci_gpio_setup(void)
 114 {
 115         int i, base;
 116
 117         for (i = 0, base = 0;
 118                         i < ARRAY_SIZE(chips);
 119                         i++, base += 32) {
 120                 chips[i].chip.label = "DaVinci";
 121
 122                 chips[i].chip.direction_input = davinci_direction_in;
 123                 chips[i].chip.get = davinci_gpio_get;
 124                 chips[i].chip.direction_output = davinci_direction_out;
 125                 chips[i].chip.set = davinci_gpio_set;
 126
 127                 chips[i].chip.base = base;
 128                 chips[i].chip.ngpio = DAVINCI_N_GPIO - base;
 129                 if (chips[i].chip.ngpio > 32)
 130                         chips[i].chip.ngpio = 32;
 131
 132                 chips[i].regs = gpio2controller(base);
 133
 134                 gpiochip_add(&chips[i].chip);
 135         }
 136
 137         return 0;
 138 }
 139 pure_initcall(davinci_gpio_setup);
 140
 141 /*--------------------------------------------------------------------------*/
 142 /*
 143  * We expect irqs will normally be set up as input pins, but they can also be
 144  * used as output pins ... which is convenient for testing.
 145  *
 146  * NOTE:  GPIO0..GPIO7 also have direct INTC hookups, which work in addition
 147  * to their GPIOBNK0 irq (but with a bit less overhead).  But we don't have
 148  * a good way to hook those up ...
 149  *
 150  * All those INTC hookups (GPIO0..GPIO7 plus five IRQ banks) can also
 151  * serve as EDMA event triggers.
 152  */
 153
 154 static void gpio_irq_disable(unsigned irq)
 155 {
 156         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
 157         u32 mask = __gpio_mask(irq_to_gpio(irq));
 158
 159         __raw_writel(mask, &g->clr_falling);
 160         __raw_writel(mask, &g->clr_rising);
 161 }
 162
 163 static void gpio_irq_enable(unsigned irq)
 164 {
 165         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
 166         u32 mask = __gpio_mask(irq_to_gpio(irq));
 167
 168         if (irq_desc[irq].status & IRQ_TYPE_EDGE_FALLING)
 169                 __raw_writel(mask, &g->set_falling);
 170         if (irq_desc[irq].status & IRQ_TYPE_EDGE_RISING)
 171                 __raw_writel(mask, &g->set_rising);
 172 }
 173
 174 static int gpio_irq_type(unsigned irq, unsigned trigger)
 175 {
 176         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
 177         u32 mask = __gpio_mask(irq_to_gpio(irq));
 178
 179         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 180                 return -EINVAL;
 181
 182         irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
 183         irq_desc[irq].status |= trigger;
 184
 185         __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
 186                      ? &g->set_falling : &g->clr_falling);
 187         __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
 188                      ? &g->set_rising : &g->clr_rising);
 189         return 0;
 190 }
 191
 192 static struct irq_chip gpio_irqchip = {
 193         .name           = "GPIO",
 194         .enable         = gpio_irq_enable,
 195         .disable        = gpio_irq_disable,
 196         .set_type       = gpio_irq_type,
 197 };
 198
 199 static void
 200 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 201 {
 202         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
 203         u32 mask = 0xffff;
 204
 205         /* we only care about one bank */
 206         if (irq & 1)
 207                 mask <<= 16;
 208
 209         /* temporarily mask (level sensitive) parent IRQ */
 210         desc->chip->ack(irq);
 211         while (1) {
 212                 u32             status;
 213                 int             n;
 214                 int             res;
 215
 216                 /* ack any irqs */
 217                 status = __raw_readl(&g->intstat) & mask;
 218                 if (!status)
 219                         break;
 220                 __raw_writel(status, &g->intstat);
 221                 if (irq & 1)
 222                         status >>= 16;
 223
 224                 /* now demux them to the right lowlevel handler */
 225                 n = (int)get_irq_data(irq);
 226                 while (status) {
 227                         res = ffs(status);
 228                         n += res;
 229                         generic_handle_irq(n - 1);
 230                         status >>= res;
 231                 }
 232         }
 233         desc->chip->unmask(irq);
 234         /* now it may re-trigger */
 235 }
 236
 237 /*
 238  * NOTE:  for suspend/resume, probably best to make a sysdev (and class)
 239  * with its suspend/resume calls hooking into the results of the set_wake()
 240  * calls ... so if no gpios are wakeup events the clock can be disabled,
 241  * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 242  * can be set appropriately for GPIOV33 pins.
 243  */
 244
 245 static int __init davinci_gpio_irq_setup(void)
 246 {
 247         unsigned        gpio, irq, bank;
 248         struct clk      *clk;
 249
 250         clk = clk_get(NULL, "gpio");
 251         if (IS_ERR(clk)) {
 252                 printk(KERN_ERR "Error %ld getting gpio clock?\n",
 253                        PTR_ERR(clk));
 254                 return 0;
 255         }
 256
 257         clk_enable(clk);
 258
 259         for (gpio = 0, irq = gpio_to_irq(0), bank = IRQ_GPIOBNK0;
 260              gpio < DAVINCI_N_GPIO; bank++) {
 261                 struct gpio_controller  *__iomem g = gpio2controller(gpio);
 262                 unsigned                i;
 263
 264                 __raw_writel(~0, &g->clr_falling);
 265                 __raw_writel(~0, &g->clr_rising);
 266
 267                 /* set up all irqs in this bank */
 268                 set_irq_chained_handler(bank, gpio_irq_handler);
 269                 set_irq_chip_data(bank, g);
 270                 set_irq_data(bank, (void *)irq);
 271
 272                 for (i = 0; i < 16 && gpio < DAVINCI_N_GPIO;
 273                      i++, irq++, gpio++) {
 274                         set_irq_chip(irq, &gpio_irqchip);
 275                         set_irq_chip_data(irq, g);
 276                         set_irq_handler(irq, handle_simple_irq);
 277                         set_irq_flags(irq, IRQF_VALID);
 278                 }
 279         }
 280
 281         /* BINTEN -- per-bank interrupt enable. genirq would also let these
 282          * bits be set/cleared dynamically.
 283          */
 284         __raw_writel(0x1f, (void *__iomem)
 285                      IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08));
 286
 287         printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
 288
 289         return 0;
 290 }
 291
 292 arch_initcall(davinci_gpio_irq_setup);