MyMicroProccessor

Computer Architectures project to design a 16/32 bit microprocessor in VHDL.

This is our design of a 16/32 bit microproccessor in VHDL, as part of the second year Computer Architectures module from the Department of Electronics at the University of York

Authors

The Labs were created by myself @zwrawr and Tom meadows @djw0bbl3. All of the commits are in my name because tom didn't have a github account at the time, but the project is a join effort.

Project

The final assesment of the course was to create a 16/32 bit multi cycle cpu, using vhdl.

Labs

Lab 1

Lab 2

This lab is about creating data paths for single cycle, multi cycle and piplined architectures. We used the registers and the ALU from Lab 1. Here's the RTL schematic of the piplined architecture.

Homework

The homework assignments were manualy calcation caching hit or miss, hand assembling and lots of binary math.

Project

Develop a multicycle proccessor.