3 " Maintainer: Mun Johl <Mun.Johl@emulex.com>
4 " Last Update: Wed Jul 20 16:04:19 PDT 2011
6 " For version 5.x: Clear all syntax items
7 " For version 6.x: Quit when a syntax file was already loaded
10 elseif exists("b:current_syntax")
14 " Set the local value of the 'iskeyword' option.
15 " NOTE: '?' was added so that verilogNumber would be processed correctly when
16 " '?' is the last character of the number.
18 setlocal iskeyword=@,48-57,63,_,192-255
20 set iskeyword=@,48-57,63,_,192-255
23 " A bunch of useful Verilog keywords
25 syn keyword verilogStatement always and assign automatic buf
26 syn keyword verilogStatement bufif0 bufif1 cell cmos
27 syn keyword verilogStatement config deassign defparam design
28 syn keyword verilogStatement disable edge endconfig
29 syn keyword verilogStatement endfunction endgenerate endmodule
30 syn keyword verilogStatement endprimitive endspecify endtable endtask
31 syn keyword verilogStatement event force function
32 syn keyword verilogStatement generate genvar highz0 highz1 ifnone
33 syn keyword verilogStatement incdir include initial inout input
34 syn keyword verilogStatement instance integer large liblist
35 syn keyword verilogStatement library localparam macromodule medium
36 syn keyword verilogStatement module nand negedge nmos nor
37 syn keyword verilogStatement noshowcancelled not notif0 notif1 or
38 syn keyword verilogStatement output parameter pmos posedge primitive
39 syn keyword verilogStatement pull0 pull1 pulldown pullup
40 syn keyword verilogStatement pulsestyle_onevent pulsestyle_ondetect
41 syn keyword verilogStatement rcmos real realtime reg release
42 syn keyword verilogStatement rnmos rpmos rtran rtranif0 rtranif1
43 syn keyword verilogStatement scalared showcancelled signed small
44 syn keyword verilogStatement specify specparam strong0 strong1
45 syn keyword verilogStatement supply0 supply1 table task time tran
46 syn keyword verilogStatement tranif0 tranif1 tri tri0 tri1 triand
47 syn keyword verilogStatement trior trireg unsigned use vectored wait
48 syn keyword verilogStatement wand weak0 weak1 wire wor xnor xor
49 syn keyword verilogLabel begin end fork join
50 syn keyword verilogConditional if else case casex casez default endcase
51 syn keyword verilogRepeat forever repeat while for
53 syn keyword verilogTodo contained TODO FIXME
55 syn match verilogOperator "[&|~><!)(*#%@+/=?:;}{,.\^\-\[\]]"
57 syn region verilogComment start="/\*" end="\*/" contains=verilogTodo,@Spell
58 syn match verilogComment "//.*" contains=verilogTodo,@Spell
60 "syn match verilogGlobal "`[a-zA-Z0-9_]\+\>"
61 syn match verilogGlobal "`celldefine"
62 syn match verilogGlobal "`default_nettype"
63 syn match verilogGlobal "`define"
64 syn match verilogGlobal "`else"
65 syn match verilogGlobal "`elsif"
66 syn match verilogGlobal "`endcelldefine"
67 syn match verilogGlobal "`endif"
68 syn match verilogGlobal "`ifdef"
69 syn match verilogGlobal "`ifndef"
70 syn match verilogGlobal "`include"
71 syn match verilogGlobal "`line"
72 syn match verilogGlobal "`nounconnected_drive"
73 syn match verilogGlobal "`resetall"
74 syn match verilogGlobal "`timescale"
75 syn match verilogGlobal "`unconnected_drive"
76 syn match verilogGlobal "`undef"
77 syn match verilogGlobal "$[a-zA-Z0-9_]\+\>"
79 syn match verilogConstant "\<[A-Z][A-Z0-9_]\+\>"
81 syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[bB]\s*[0-1_xXzZ?]\+\>"
82 syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[oO]\s*[0-7_xXzZ?]\+\>"
83 syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[dD]\s*[0-9_xXzZ?]\+\>"
84 syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[hH]\s*[0-9a-fA-F_xXzZ?]\+\>"
85 syn match verilogNumber "\<[+-]\=[0-9_]\+\(\.[0-9_]*\|\)\(e[0-9_]*\|\)\>"
87 syn region verilogString start=+"+ skip=+\\"+ end=+"+ contains=verilogEscape,@Spell
88 syn match verilogEscape +\\[nt"\\]+ contained
89 syn match verilogEscape "\\\o\o\=\o\=" contained
92 syn match verilogDirective "//\s*synopsys\>.*$"
93 syn region verilogDirective start="/\*\s*synopsys\>" end="\*/"
94 syn region verilogDirective start="//\s*synopsys dc_script_begin\>" end="//\s*synopsys dc_script_end\>"
96 syn match verilogDirective "//\s*\$s\>.*$"
97 syn region verilogDirective start="/\*\s*\$s\>" end="\*/"
98 syn region verilogDirective start="//\s*\$s dc_script_begin\>" end="//\s*\$s dc_script_end\>"
100 "Modify the following as needed. The trade-off is performance versus
104 " Define the default highlighting.
105 " For version 5.7 and earlier: only when not done already
106 " For version 5.8 and later: only when an item doesn't have highlighting yet
107 if version >= 508 || !exists("did_verilog_syn_inits")
109 let did_verilog_syn_inits = 1
110 command -nargs=+ HiLink hi link <args>
112 command -nargs=+ HiLink hi def link <args>
115 " The default highlighting.
116 HiLink verilogCharacter Character
117 HiLink verilogConditional Conditional
118 HiLink verilogRepeat Repeat
119 HiLink verilogString String
120 HiLink verilogTodo Todo
121 HiLink verilogComment Comment
122 HiLink verilogConstant Constant
123 HiLink verilogLabel Label
124 HiLink verilogNumber Number
125 HiLink verilogOperator Special
126 HiLink verilogStatement Statement
127 HiLink verilogGlobal Define
128 HiLink verilogDirective SpecialComment
129 HiLink verilogEscape Special
134 let b:current_syntax = "verilog"