cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #ifdef HAVE_MALLOC_H
   8 #include <malloc.h>
   9 #endif
  10 #include <stdlib.h>
  11
  12 #if defined(ARCH_X86) || defined(ARCH_X86_64)
  13
  14 #include <stdio.h>
  15 #include <string.h>
  16
  17 #if defined (__NetBSD__) || defined(__OpenBSD__)
  18 #include <sys/param.h>
  19 #include <sys/sysctl.h>
  20 #include <machine/cpu.h>
  21 #endif
  22
  23 #if defined(__FreeBSD__) || defined(__DragonFly__)
  24 #include <sys/types.h>
  25 #include <sys/sysctl.h>
  26 #endif
  27
  28 #ifdef __linux__
  29 #include <signal.h>
  30 #endif
  31
  32 #ifdef WIN32
  33 #include <windows.h>
  34 #endif
  35
  36 #ifdef __AMIGAOS4__
  37 #include <proto/exec.h>
  38 #endif
  39
  40 //#define X86_FXSR_MAGIC
  41 /* Thanks to the FreeBSD project for some of this cpuid code, and
  42  * help understanding how to use it.  Thanks to the Mesa
  43  * team for SSE support detection and more cpu detect code.
  44  */
  45
  46 /* I believe this code works.  However, it has only been used on a PII and PIII */
  47
  48 static void check_os_katmai_support( void );
  49
  50 #if 1
  51 // return TRUE if cpuid supported
  52 static int has_cpuid(void)
  53 {
  54         long a, c;
  55
  56 // code from libavcodec:
  57     __asm__ __volatile__ (
  58                           /* See if CPUID instruction is supported ... */
  59                           /* ... Get copies of EFLAGS into eax and ecx */
  60                           "pushf\n\t"
  61                           "pop %0\n\t"
  62                           "mov %0, %1\n\t"
  63
  64                           /* ... Toggle the ID bit in one copy and store */
  65                           /*     to the EFLAGS reg */
  66                           "xor $0x200000, %0\n\t"
  67                           "push %0\n\t"
  68                           "popf\n\t"
  69
  70                           /* ... Get the (hopefully modified) EFLAGS */
  71                           "pushf\n\t"
  72                           "pop %0\n\t"
  73                           : "=a" (a), "=c" (c)
  74                           :
  75                           : "cc"
  76                           );
  77
  78         return (a!=c);
  79 }
  80 #endif
  81
  82 static void
  83 do_cpuid(unsigned int ax, unsigned int *p)
  84 {
  85 #if 0
  86         __asm __volatile(
  87         "cpuid;"
  88         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  89         :  "0" (ax)
  90         );
  91 #else
  92 // code from libavcodec:
  93     __asm __volatile
  94         ("mov %%"REG_b", %%"REG_S"\n\t"
  95          "cpuid\n\t"
  96          "xchg %%"REG_b", %%"REG_S
  97          : "=a" (p[0]), "=S" (p[1]),
  98            "=c" (p[2]), "=d" (p[3])
  99          : "0" (ax));
 100 #endif
 101
 102 }
 103
 104 void GetCpuCaps( CpuCaps *caps)
 105 {
 106         unsigned int regs[4];
 107         unsigned int regs2[4];
 108
 109         memset(caps, 0, sizeof(*caps));
 110         caps->isX86=1;
 111         caps->cl_size=32; /* default */
 112         if (!has_cpuid()) {
 113             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 114             return;
 115         }
 116         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 117         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 118                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 119         if (regs[0]>=0x00000001)
 120         {
 121                 char *tmpstr;
 122                 unsigned cl_size;
 123
 124                 do_cpuid(0x00000001, regs2);
 125
 126                 caps->cpuType=(regs2[0] >> 8)&0xf;
 127
 128 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 129 // System Instructions, Table 3-2: Effective family computation, page 120.
 130                 if(caps->cpuType==0xf){
 131                     // use extended family (P4, IA64, K8)
 132                     caps->cpuType=0xf+((regs2[0]>>20)&255);
 133                 }
 134                 caps->cpuStepping=regs2[0] & 0xf;
 135
 136                 // general feature flags:
 137                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 138                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 139                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 140                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 141                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 142                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 143                 if(cl_size) caps->cl_size = cl_size;
 144
 145                 tmpstr=GetCpuFriendlyName(regs, regs2);
 146                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ",tmpstr);
 147                 free(tmpstr);
 148                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Stepping: %d)\n",
 149                     caps->cpuType, caps->cpuStepping);
 150
 151         }
 152         do_cpuid(0x80000000, regs);
 153         if (regs[0]>=0x80000001) {
 154                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 155                 do_cpuid(0x80000001, regs2);
 156                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 157                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 158                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 159                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 160         }
 161         if(regs[0]>=0x80000006)
 162         {
 163                 do_cpuid(0x80000006, regs2);
 164                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 165                 caps->cl_size  = regs2[2] & 0xFF;
 166         }
 167         mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 168 #if 0
 169         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 170                 gCpuCaps.hasMMX,
 171                 gCpuCaps.hasMMX2,
 172                 gCpuCaps.hasSSE,
 173                 gCpuCaps.hasSSE2,
 174                 gCpuCaps.has3DNow,
 175                 gCpuCaps.has3DNowExt );
 176 #endif
 177
 178                 /* FIXME: Does SSE2 need more OS support, too? */
 179 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__CYGWIN__) || defined(__OpenBSD__) || defined(__DragonFly__)
 180                 if (caps->hasSSE)
 181                         check_os_katmai_support();
 182                 if (!caps->hasSSE)
 183                         caps->hasSSE2 = 0;
 184 #else
 185                 caps->hasSSE=0;
 186                 caps->hasSSE2 = 0;
 187 #endif
 188 //              caps->has3DNow=1;
 189 //              caps->hasMMX2 = 0;
 190 //              caps->hasMMX = 0;
 191
 192 #ifndef HAVE_MMX
 193         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 194         caps->hasMMX=0;
 195 #endif
 196 #ifndef HAVE_MMX2
 197         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 198         caps->hasMMX2=0;
 199 #endif
 200 #ifndef HAVE_SSE
 201         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 202         caps->hasSSE=0;
 203 #endif
 204 #ifndef HAVE_SSE2
 205         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 206         caps->hasSSE2=0;
 207 #endif
 208 #ifndef HAVE_3DNOW
 209         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 210         caps->has3DNow=0;
 211 #endif
 212 #ifndef HAVE_3DNOWEX
 213         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 214         caps->has3DNowExt=0;
 215 #endif
 216 }
 217
 218
 219 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
 220 #define CPUID_EXTMODEL  ((regs2[0] >> 16)&0x0F) /* 19..16 */
 221 #define CPUID_TYPE              ((regs2[0] >> 12)&0x04) /* 13..12 */
 222 #define CPUID_FAMILY    ((regs2[0] >>  8)&0x0F) /* 11..08 */
 223 #define CPUID_MODEL             ((regs2[0] >>  4)&0x0F) /* 07..04 */
 224 #define CPUID_STEPPING  ((regs2[0] >>  0)&0x0F) /* 03..00 */
 225
 226 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 227 #include "cputable.h" /* get cpuname and cpuvendors */
 228         char vendor[17];
 229         char *retname;
 230         int i;
 231
 232         if (NULL==(retname=(char*)malloc(256))) {
 233                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 234                 exit(1);
 235         }
 236
 237         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 238
 239         for(i=0; i<MAX_VENDORS; i++){
 240                 if(!strcmp(cpuvendors[i].string,vendor)){
 241                         if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
 242                                 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
 243                         } else {
 244                                 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
 245                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name);
 246                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor:   %s\n",cpuvendors[i].string);
 247                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type:     %d\n",CPUID_TYPE);
 248                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family:   %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
 249                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model:    %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
 250                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING);
 251                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name"
 252                                        "to the MPlayer-Developers, so we can add it to the list!\n");
 253                         }
 254                 }
 255         }
 256         retname[255] = 0;
 257
 258         //printf("Detected CPU: %s\n", retname);
 259         return retname;
 260 }
 261
 262 #undef CPUID_EXTFAMILY
 263 #undef CPUID_EXTMODEL
 264 #undef CPUID_TYPE
 265 #undef CPUID_FAMILY
 266 #undef CPUID_MODEL
 267 #undef CPUID_STEPPING
 268
 269
 270 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 271 static void sigill_handler_sse( int signal, struct sigcontext sc )
 272 {
 273    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 274
 275    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 276     * instructions are 3 bytes long.  We must increment the instruction
 277     * pointer manually to avoid repeated execution of the offending
 278     * instruction.
 279     *
 280     * If the SIGILL is caused by a divide-by-zero when unmasked
 281     * exceptions aren't supported, the SIMD FPU status and control
 282     * word will be restored at the end of the test, so we don't need
 283     * to worry about doing it here.  Besides, we may not be able to...
 284     */
 285    sc.eip += 3;
 286
 287    gCpuCaps.hasSSE=0;
 288 }
 289
 290 static void sigfpe_handler_sse( int signal, struct sigcontext sc )
 291 {
 292    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " );
 293
 294    if ( sc.fpstate->magic != 0xffff ) {
 295       /* Our signal context has the extended FPU state, so reset the
 296        * divide-by-zero exception mask and clear the divide-by-zero
 297        * exception bit.
 298        */
 299       sc.fpstate->mxcsr |= 0x00000200;
 300       sc.fpstate->mxcsr &= 0xfffffffb;
 301    } else {
 302       /* If we ever get here, we're completely hosed.
 303        */
 304       mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" );
 305       mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" );
 306    }
 307 }
 308 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
 309
 310 #ifdef WIN32
 311 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 312 {
 313    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 314       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 315       ep->ContextRecord->Eip +=3;
 316       gCpuCaps.hasSSE=0;
 317           return EXCEPTION_CONTINUE_EXECUTION;
 318    }
 319    return EXCEPTION_CONTINUE_SEARCH;
 320 }
 321 #endif /* WIN32 */
 322
 323 /* If we're running on a processor that can do SSE, let's see if we
 324  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 325  * haven't been configured for a Pentium III but are running on one,
 326  * and RedHat patched 2.2 kernels that have broken exception handling
 327  * support for user space apps that do SSE.
 328  */
 329 static void check_os_katmai_support( void )
 330 {
 331 #ifdef ARCH_X86_64
 332    gCpuCaps.hasSSE=1;
 333    gCpuCaps.hasSSE2=1;
 334 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 335    int has_sse=0, ret;
 336    size_t len=sizeof(has_sse);
 337
 338    ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0);
 339    if (ret || !has_sse)
 340       gCpuCaps.hasSSE=0;
 341
 342 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 343 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 344    int has_sse, has_sse2, ret, mib[2];
 345    size_t varlen;
 346
 347    mib[0] = CTL_MACHDEP;
 348    mib[1] = CPU_SSE;
 349    varlen = sizeof(has_sse);
 350
 351    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 352    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 353    if (ret < 0 || !has_sse) {
 354       gCpuCaps.hasSSE=0;
 355       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 356    } else {
 357       gCpuCaps.hasSSE=1;
 358       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 359    }
 360
 361    mib[1] = CPU_SSE2;
 362    varlen = sizeof(has_sse2);
 363    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 364    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 365    if (ret < 0 || !has_sse2) {
 366       gCpuCaps.hasSSE2=0;
 367       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 368    } else {
 369       gCpuCaps.hasSSE2=1;
 370       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 371    }
 372 #else
 373    gCpuCaps.hasSSE = 0;
 374    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 375 #endif
 376 #elif defined(WIN32)
 377    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 378    if ( gCpuCaps.hasSSE ) {
 379       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 380       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 381       __asm __volatile ("xorps %xmm0, %xmm0");
 382       SetUnhandledExceptionFilter(exc_fil);
 383       if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 384       else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 385    }
 386 #elif defined(__linux__)
 387 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 388    struct sigaction saved_sigill;
 389    struct sigaction saved_sigfpe;
 390
 391    /* Save the original signal handlers.
 392     */
 393    sigaction( SIGILL, NULL, &saved_sigill );
 394    sigaction( SIGFPE, NULL, &saved_sigfpe );
 395
 396    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 397    signal( SIGFPE, (void (*)(int))sigfpe_handler_sse );
 398
 399    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 400     * supports the extended FPU save and restore required for SSE.  If
 401     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 402     * doesn't support Streaming SIMD Exceptions, even if the processor
 403     * does.
 404     */
 405    if ( gCpuCaps.hasSSE ) {
 406       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 407
 408 //      __asm __volatile ("xorps %%xmm0, %%xmm0");
 409       __asm __volatile ("xorps %xmm0, %xmm0");
 410
 411       if ( gCpuCaps.hasSSE ) {
 412          mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 413       } else {
 414          mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 415       }
 416    }
 417
 418    /* Emulate test for OSXMMEXCPT in CR4.  The OS will set this bit if
 419     * it supports unmasked SIMD FPU exceptions.  If we unmask the
 420     * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
 421     * doesn't support unmasked SIMD FPU exceptions.  If we get a SIGFPE
 422     * as expected, we're okay but we need to clean up after it.
 423     *
 424     * Are we being too stringent in our requirement that the OS support
 425     * unmasked exceptions?  Certain RedHat 2.2 kernels enable SSE by
 426     * setting CR4.OSFXSR but don't support unmasked exceptions.  Win98
 427     * doesn't even support them.  We at least know the user-space SSE
 428     * support is good in kernels that do support unmasked exceptions,
 429     * and therefore to be safe I'm going to leave this test in here.
 430     */
 431    if ( gCpuCaps.hasSSE ) {
 432       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " );
 433
 434 //      test_os_katmai_exception_support();
 435
 436       if ( gCpuCaps.hasSSE ) {
 437          mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 438       } else {
 439          mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 440       }
 441    }
 442
 443    /* Restore the original signal handlers.
 444     */
 445    sigaction( SIGILL, &saved_sigill, NULL );
 446    sigaction( SIGFPE, &saved_sigfpe, NULL );
 447
 448    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 449     * safe to go ahead and hook out the SSE code throughout Mesa.
 450     */
 451    if ( gCpuCaps.hasSSE ) {
 452       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" );
 453    } else {
 454       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" );
 455    }
 456 #else
 457    /* We can't use POSIX signal handling to test the availability of
 458     * SSE, so we disable it by default.
 459     */
 460    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 461    gCpuCaps.hasSSE=0;
 462 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
 463 #else
 464    /* Do nothing on other platforms for now.
 465     */
 466    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 467    gCpuCaps.hasSSE=0;
 468 #endif /* __linux__ */
 469 }
 470 #else /* ARCH_X86 || ARCH_X86_64 */
 471
 472 #ifdef SYS_DARWIN
 473 #include <sys/sysctl.h>
 474 #else
 475 #ifndef __AMIGAOS4__
 476 #include <signal.h>
 477 #include <setjmp.h>
 478
 479 static sigjmp_buf jmpbuf;
 480 static volatile sig_atomic_t canjump = 0;
 481
 482 static void sigill_handler (int sig)
 483 {
 484     if (!canjump) {
 485         signal (sig, SIG_DFL);
 486         raise (sig);
 487     }
 488
 489     canjump = 0;
 490     siglongjmp (jmpbuf, 1);
 491 }
 492 #endif //__AMIGAOS4__
 493 #endif
 494
 495 void GetCpuCaps( CpuCaps *caps)
 496 {
 497         caps->cpuType=0;
 498         caps->cpuStepping=0;
 499         caps->hasMMX=0;
 500         caps->hasMMX2=0;
 501         caps->has3DNow=0;
 502         caps->has3DNowExt=0;
 503         caps->hasSSE=0;
 504         caps->hasSSE2=0;
 505         caps->isX86=0;
 506         caps->hasAltiVec = 0;
 507 #ifdef HAVE_ALTIVEC
 508 #ifdef SYS_DARWIN
 509 /*
 510   rip-off from ffmpeg altivec detection code.
 511   this code also appears on Apple's AltiVec pages.
 512  */
 513         {
 514                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 515                 int has_vu = 0;
 516                 size_t len = sizeof(has_vu);
 517                 int err;
 518
 519                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 520
 521                 if (err == 0)
 522                         if (has_vu != 0)
 523                                 caps->hasAltiVec = 1;
 524         }
 525 #else /* SYS_DARWIN */
 526 #ifdef __AMIGAOS4__
 527         ULONG result = 0;
 528
 529         GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 530         if (result == VECTORTYPE_ALTIVEC)
 531                 caps->hasAltiVec = 1;
 532 #else
 533 /* no Darwin, do it the brute-force way */
 534 /* this is borrowed from the libmpeg2 library */
 535         {
 536           signal (SIGILL, sigill_handler);
 537           if (sigsetjmp (jmpbuf, 1)) {
 538             signal (SIGILL, SIG_DFL);
 539           } else {
 540             canjump = 1;
 541
 542             asm volatile ("mtspr 256, %0\n\t"
 543                           "vand %%v0, %%v0, %%v0"
 544                           :
 545                           : "r" (-1));
 546
 547             signal (SIGILL, SIG_DFL);
 548             caps->hasAltiVec = 1;
 549           }
 550         }
 551 #endif //__AMIGAOS4__
 552 #endif /* SYS_DARWIN */
 553         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 554 #endif /* HAVE_ALTIVEC */
 555
 556 #ifdef ARCH_IA64
 557         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n");
 558 #endif
 559
 560 #ifdef ARCH_SPARC
 561         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n");
 562 #endif
 563
 564 #ifdef ARCH_ARMV4L
 565         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n");
 566 #endif
 567
 568 #ifdef ARCH_POWERPC
 569         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n");
 570 #endif
 571
 572 #ifdef ARCH_ALPHA
 573         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n");
 574 #endif
 575
 576 #ifdef ARCH_SGI_MIPS
 577         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n");
 578 #endif
 579
 580 #ifdef ARCH_PA_RISC
 581         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n");
 582 #endif
 583
 584 #ifdef ARCH_S390
 585         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n");
 586 #endif
 587
 588 #ifdef ARCH_S390X
 589         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n");
 590 #endif
 591
 592 #ifdef ARCH_VAX
 593         mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" );
 594 #endif
 595 }
 596 #endif /* !ARCH_X86 */