cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #ifdef HAVE_MALLOC_H
   8 #include <malloc.h>
   9 #endif
  10 #include <stdlib.h>
  11
  12 #ifdef ARCH_X86
  13
  14 #include <stdio.h>
  15 #include <string.h>
  16
  17 #ifdef __NetBSD__
  18 #include <sys/param.h>
  19 #include <sys/sysctl.h>
  20 #include <machine/cpu.h>
  21 #endif
  22
  23 #ifdef __FreeBSD__
  24 #include <sys/types.h>
  25 #include <sys/sysctl.h>
  26 #endif
  27
  28 #ifdef __linux__
  29 #include <signal.h>
  30 #endif
  31
  32 #ifdef WIN32
  33 #include <windows.h>
  34 #endif
  35
  36 //#define X86_FXSR_MAGIC
  37 /* Thanks to the FreeBSD project for some of this cpuid code, and
  38  * help understanding how to use it.  Thanks to the Mesa
  39  * team for SSE support detection and more cpu detect code.
  40  */
  41
  42 /* I believe this code works.  However, it has only been used on a PII and PIII */
  43
  44 static void check_os_katmai_support( void );
  45
  46 #if 1
  47 // return TRUE if cpuid supported
  48 static int has_cpuid()
  49 {
  50         int a, c;
  51
  52 // code from libavcodec:
  53     __asm__ __volatile__ (
  54                           /* See if CPUID instruction is supported ... */
  55                           /* ... Get copies of EFLAGS into eax and ecx */
  56                           "pushf\n\t"
  57                           "popl %0\n\t"
  58                           "movl %0, %1\n\t"
  59
  60                           /* ... Toggle the ID bit in one copy and store */
  61                           /*     to the EFLAGS reg */
  62                           "xorl $0x200000, %0\n\t"
  63                           "push %0\n\t"
  64                           "popf\n\t"
  65
  66                           /* ... Get the (hopefully modified) EFLAGS */
  67                           "pushf\n\t"
  68                           "popl %0\n\t"
  69                           : "=a" (a), "=c" (c)
  70                           :
  71                           : "cc"
  72                           );
  73
  74         return (a!=c);
  75 }
  76 #endif
  77
  78 static void
  79 do_cpuid(unsigned int ax, unsigned int *p)
  80 {
  81 #if 0
  82         __asm __volatile(
  83         "cpuid;"
  84         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  85         :  "0" (ax)
  86         );
  87 #else
  88 // code from libavcodec:
  89     __asm __volatile
  90         ("movl %%ebx, %%esi\n\t"
  91          "cpuid\n\t"
  92          "xchgl %%ebx, %%esi"
  93          : "=a" (p[0]), "=S" (p[1]),
  94            "=c" (p[2]), "=d" (p[3])
  95          : "0" (ax));
  96 #endif
  97
  98 }
  99
 100 void GetCpuCaps( CpuCaps *caps)
 101 {
 102         unsigned int regs[4];
 103         unsigned int regs2[4];
 104
 105         memset(caps, 0, sizeof(*caps));
 106         caps->isX86=1;
 107         caps->cl_size=32; /* default */
 108         if (!has_cpuid()) {
 109             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 110             return;
 111         }
 112         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 113         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 114                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 115         if (regs[0]>=0x00000001)
 116         {
 117                 char *tmpstr;
 118                 unsigned cl_size;
 119
 120                 do_cpuid(0x00000001, regs2);
 121
 122                 tmpstr=GetCpuFriendlyName(regs, regs2);
 123                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ",tmpstr);
 124                 free(tmpstr);
 125
 126                 caps->cpuType=(regs2[0] >> 8)&0xf;
 127                 if(caps->cpuType==0xf){
 128                     // use extended family (P4, IA64)
 129                     caps->cpuType=8+((regs2[0]>>20)&255);
 130                 }
 131                 caps->cpuStepping=regs2[0] & 0xf;
 132                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Stepping: %d)\n",
 133                     caps->cpuType, caps->cpuStepping);
 134
 135                 // general feature flags:
 136                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 137                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 138                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 139                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 140                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 141                 if(cl_size) caps->cl_size = cl_size;
 142         }
 143         do_cpuid(0x80000000, regs);
 144         if (regs[0]>=0x80000001) {
 145                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 146                 do_cpuid(0x80000001, regs2);
 147                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 148                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 149                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 150                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 151         }
 152         if(regs[0]>=0x80000006)
 153         {
 154                 do_cpuid(0x80000006, regs2);
 155                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 156                 caps->cl_size  = regs2[2] & 0xFF;
 157         }
 158         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"Detected cache-line size is %u bytes\n",caps->cl_size);
 159 #if 0
 160         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 161                 gCpuCaps.hasMMX,
 162                 gCpuCaps.hasMMX2,
 163                 gCpuCaps.hasSSE,
 164                 gCpuCaps.hasSSE2,
 165                 gCpuCaps.has3DNow,
 166                 gCpuCaps.has3DNowExt );
 167 #endif
 168
 169                 /* FIXME: Does SSE2 need more OS support, too? */
 170 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(WIN32)
 171                 if (caps->hasSSE)
 172                         check_os_katmai_support();
 173                 if (!caps->hasSSE)
 174                         caps->hasSSE2 = 0;
 175 #else
 176                 caps->hasSSE=0;
 177                 caps->hasSSE2 = 0;
 178 #endif
 179 //              caps->has3DNow=1;
 180 //              caps->hasMMX2 = 0;
 181 //              caps->hasMMX = 0;
 182
 183 #ifndef HAVE_MMX
 184         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 185         caps->hasMMX=0;
 186 #endif
 187 #ifndef HAVE_MMX2
 188         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 189         caps->hasMMX2=0;
 190 #endif
 191 #ifndef HAVE_SSE
 192         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 193         caps->hasSSE=0;
 194 #endif
 195 #ifndef HAVE_SSE2
 196         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 197         caps->hasSSE2=0;
 198 #endif
 199 #ifndef HAVE_3DNOW
 200         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 201         caps->has3DNow=0;
 202 #endif
 203 #ifndef HAVE_3DNOWEX
 204         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 205         caps->has3DNowExt=0;
 206 #endif
 207 }
 208
 209
 210 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
 211 #define CPUID_EXTMODEL  ((regs2[0] >> 16)&0x0F) /* 19..16 */
 212 #define CPUID_TYPE              ((regs2[0] >> 12)&0x04) /* 13..12 */
 213 #define CPUID_FAMILY    ((regs2[0] >>  8)&0x0F) /* 11..08 */
 214 #define CPUID_MODEL             ((regs2[0] >>  4)&0x0F) /* 07..04 */
 215 #define CPUID_STEPPING  ((regs2[0] >>  0)&0x0F) /* 03..00 */
 216
 217 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 218 #include "cputable.h" /* get cpuname and cpuvendors */
 219         char vendor[17];
 220         char *retname;
 221         int i;
 222
 223         if (NULL==(retname=(char*)malloc(256))) {
 224                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 225                 exit(1);
 226         }
 227
 228         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 229
 230         for(i=0; i<MAX_VENDORS; i++){
 231                 if(!strcmp(cpuvendors[i].string,vendor)){
 232                         if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
 233                                 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
 234                         } else {
 235                                 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
 236                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name);
 237                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor:   %s\n",cpuvendors[i].string);
 238                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type:     %d\n",CPUID_TYPE);
 239                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family:   %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
 240                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model:    %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
 241                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING);
 242                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name"
 243                                        "to the MPlayer-Developers, so we can add it to the list!\n");
 244                         }
 245                 }
 246         }
 247
 248         //printf("Detected CPU: %s\n", retname);
 249         return retname;
 250 }
 251
 252 #undef CPUID_EXTFAMILY
 253 #undef CPUID_EXTMODEL
 254 #undef CPUID_TYPE
 255 #undef CPUID_FAMILY
 256 #undef CPUID_MODEL
 257 #undef CPUID_STEPPING
 258
 259
 260 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 261 static void sigill_handler_sse( int signal, struct sigcontext sc )
 262 {
 263    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 264
 265    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 266     * instructions are 3 bytes long.  We must increment the instruction
 267     * pointer manually to avoid repeated execution of the offending
 268     * instruction.
 269     *
 270     * If the SIGILL is caused by a divide-by-zero when unmasked
 271     * exceptions aren't supported, the SIMD FPU status and control
 272     * word will be restored at the end of the test, so we don't need
 273     * to worry about doing it here.  Besides, we may not be able to...
 274     */
 275    sc.eip += 3;
 276
 277    gCpuCaps.hasSSE=0;
 278 }
 279
 280 static void sigfpe_handler_sse( int signal, struct sigcontext sc )
 281 {
 282    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " );
 283
 284    if ( sc.fpstate->magic != 0xffff ) {
 285       /* Our signal context has the extended FPU state, so reset the
 286        * divide-by-zero exception mask and clear the divide-by-zero
 287        * exception bit.
 288        */
 289       sc.fpstate->mxcsr |= 0x00000200;
 290       sc.fpstate->mxcsr &= 0xfffffffb;
 291    } else {
 292       /* If we ever get here, we're completely hosed.
 293        */
 294       mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" );
 295       mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" );
 296    }
 297 }
 298 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
 299
 300 #ifdef WIN32
 301 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 302 {
 303    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 304       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 305       ep->ContextRecord->Eip +=3;
 306       gCpuCaps.hasSSE=0;
 307           return EXCEPTION_CONTINUE_EXECUTION;
 308    }
 309    return EXCEPTION_CONTINUE_SEARCH;
 310 }
 311 #endif /* WIN32 */
 312
 313 /* If we're running on a processor that can do SSE, let's see if we
 314  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 315  * haven't been configured for a Pentium III but are running on one,
 316  * and RedHat patched 2.2 kernels that have broken exception handling
 317  * support for user space apps that do SSE.
 318  */
 319 static void check_os_katmai_support( void )
 320 {
 321 #if defined(__FreeBSD__)
 322    int has_sse=0, ret;
 323    size_t len=sizeof(has_sse);
 324
 325    ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0);
 326    if (ret || !has_sse)
 327       gCpuCaps.hasSSE=0;
 328
 329 #elif defined(__NetBSD__)
 330 #if __NetBSD_Version__ >= 105250000
 331    int has_sse, has_sse2, ret, mib[2];
 332    size_t varlen;
 333
 334    mib[0] = CTL_MACHDEP;
 335    mib[1] = CPU_SSE;
 336    varlen = sizeof(has_sse);
 337
 338    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 339    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 340    if (ret < 0 || !has_sse) {
 341       gCpuCaps.hasSSE=0;
 342       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 343    } else {
 344       gCpuCaps.hasSSE=1;
 345       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 346    }
 347
 348    mib[1] = CPU_SSE2;
 349    varlen = sizeof(has_sse2);
 350    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 351    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 352    if (ret < 0 || !has_sse2) {
 353       gCpuCaps.hasSSE2=0;
 354       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 355    } else {
 356       gCpuCaps.hasSSE2=1;
 357       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 358    }
 359 #else
 360    gCpuCaps.hasSSE = 0;
 361    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 362 #endif
 363 #elif defined(WIN32)
 364    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 365    if ( gCpuCaps.hasSSE ) {
 366       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 367       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 368       __asm __volatile ("xorps %xmm0, %xmm0");
 369       SetUnhandledExceptionFilter(exc_fil);
 370       if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 371       else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 372    }
 373 #elif defined(__linux__)
 374 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 375    struct sigaction saved_sigill;
 376    struct sigaction saved_sigfpe;
 377
 378    /* Save the original signal handlers.
 379     */
 380    sigaction( SIGILL, NULL, &saved_sigill );
 381    sigaction( SIGFPE, NULL, &saved_sigfpe );
 382
 383    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 384    signal( SIGFPE, (void (*)(int))sigfpe_handler_sse );
 385
 386    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 387     * supports the extended FPU save and restore required for SSE.  If
 388     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 389     * doesn't support Streaming SIMD Exceptions, even if the processor
 390     * does.
 391     */
 392    if ( gCpuCaps.hasSSE ) {
 393       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 394
 395 //      __asm __volatile ("xorps %%xmm0, %%xmm0");
 396       __asm __volatile ("xorps %xmm0, %xmm0");
 397
 398       if ( gCpuCaps.hasSSE ) {
 399          mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 400       } else {
 401          mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 402       }
 403    }
 404
 405    /* Emulate test for OSXMMEXCPT in CR4.  The OS will set this bit if
 406     * it supports unmasked SIMD FPU exceptions.  If we unmask the
 407     * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
 408     * doesn't support unmasked SIMD FPU exceptions.  If we get a SIGFPE
 409     * as expected, we're okay but we need to clean up after it.
 410     *
 411     * Are we being too stringent in our requirement that the OS support
 412     * unmasked exceptions?  Certain RedHat 2.2 kernels enable SSE by
 413     * setting CR4.OSFXSR but don't support unmasked exceptions.  Win98
 414     * doesn't even support them.  We at least know the user-space SSE
 415     * support is good in kernels that do support unmasked exceptions,
 416     * and therefore to be safe I'm going to leave this test in here.
 417     */
 418    if ( gCpuCaps.hasSSE ) {
 419       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " );
 420
 421 //      test_os_katmai_exception_support();
 422
 423       if ( gCpuCaps.hasSSE ) {
 424          mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 425       } else {
 426          mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 427       }
 428    }
 429
 430    /* Restore the original signal handlers.
 431     */
 432    sigaction( SIGILL, &saved_sigill, NULL );
 433    sigaction( SIGFPE, &saved_sigfpe, NULL );
 434
 435    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 436     * safe to go ahead and hook out the SSE code throughout Mesa.
 437     */
 438    if ( gCpuCaps.hasSSE ) {
 439       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" );
 440    } else {
 441       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" );
 442    }
 443 #else
 444    /* We can't use POSIX signal handling to test the availability of
 445     * SSE, so we disable it by default.
 446     */
 447    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 448    gCpuCaps.hasSSE=0;
 449 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
 450 #else
 451    /* Do nothing on other platforms for now.
 452     */
 453    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 454    gCpuCaps.hasSSE=0;
 455 #endif /* __linux__ */
 456 }
 457 #else /* ARCH_X86 */
 458
 459 #ifdef SYS_DARWIN
 460 #include <sys/sysctl.h>
 461 #else
 462 #include <signal.h>
 463 #include <setjmp.h>
 464
 465 static sigjmp_buf jmpbuf;
 466 static volatile sig_atomic_t canjump = 0;
 467
 468 static void sigill_handler (int sig)
 469 {
 470     if (!canjump) {
 471         signal (sig, SIG_DFL);
 472         raise (sig);
 473     }
 474
 475     canjump = 0;
 476     siglongjmp (jmpbuf, 1);
 477 }
 478 #endif
 479
 480 void GetCpuCaps( CpuCaps *caps)
 481 {
 482         caps->cpuType=0;
 483         caps->cpuStepping=0;
 484         caps->hasMMX=0;
 485         caps->hasMMX2=0;
 486         caps->has3DNow=0;
 487         caps->has3DNowExt=0;
 488         caps->hasSSE=0;
 489         caps->hasSSE2=0;
 490         caps->isX86=0;
 491         caps->hasAltiVec = 0;
 492 #ifdef HAVE_ALTIVEC
 493 #ifdef SYS_DARWIN
 494 /*
 495   rip-off from ffmpeg altivec detection code.
 496   this code also appears on Apple's AltiVec pages.
 497  */
 498         {
 499                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 500                 int has_vu = 0;
 501                 size_t len = sizeof(has_vu);
 502                 int err;
 503
 504                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 505
 506                 if (err == 0)
 507                         if (has_vu != 0)
 508                                 caps->hasAltiVec = 1;
 509         }
 510 #else /* SYS_DARWIN */
 511 /* no Darwin, do it the brute-force way */
 512 /* this is borrowed from the libmpeg2 library */
 513         {
 514           signal (SIGILL, sigill_handler);
 515           if (sigsetjmp (jmpbuf, 1)) {
 516             signal (SIGILL, SIG_DFL);
 517           } else {
 518             canjump = 1;
 519
 520             asm volatile ("mtspr 256, %0\n\t"
 521                           "vand %%v0, %%v0, %%v0"
 522                           :
 523                           : "r" (-1));
 524
 525             signal (SIGILL, SIG_DFL);
 526             caps->hasAltiVec = 1;
 527           }
 528         }
 529 #endif /* SYS_DARWIN */
 530         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 531 #endif /* HAVE_ALTIVEC */
 532 }
 533 #endif /* !ARCH_X86 */