cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #ifdef HAVE_MALLOC_H
   8 #include <malloc.h>
   9 #endif
  10 #include <stdlib.h>
  11
  12 #ifdef ARCH_X86
  13
  14 #include <stdio.h>
  15 #include <string.h>
  16
  17 #ifdef __NetBSD__
  18 #include <sys/param.h>
  19 #include <sys/sysctl.h>
  20 #include <machine/cpu.h>
  21 #endif
  22
  23 #ifdef __FreeBSD__
  24 #include <sys/types.h>
  25 #include <sys/sysctl.h>
  26 #endif
  27
  28 #ifdef __linux__
  29 #include <signal.h>
  30 #endif
  31
  32 //#define X86_FXSR_MAGIC
  33 /* Thanks to the FreeBSD project for some of this cpuid code, and
  34  * help understanding how to use it.  Thanks to the Mesa
  35  * team for SSE support detection and more cpu detect code.
  36  */
  37
  38 /* I believe this code works.  However, it has only been used on a PII and PIII */
  39
  40 static void check_os_katmai_support( void );
  41
  42 #if 1
  43 // return TRUE if cpuid supported
  44 static int has_cpuid()
  45 {
  46         int a, c;
  47
  48 // code from libavcodec:
  49     __asm__ __volatile__ (
  50                           /* See if CPUID instruction is supported ... */
  51                           /* ... Get copies of EFLAGS into eax and ecx */
  52                           "pushf\n\t"
  53                           "popl %0\n\t"
  54                           "movl %0, %1\n\t"
  55
  56                           /* ... Toggle the ID bit in one copy and store */
  57                           /*     to the EFLAGS reg */
  58                           "xorl $0x200000, %0\n\t"
  59                           "push %0\n\t"
  60                           "popf\n\t"
  61
  62                           /* ... Get the (hopefully modified) EFLAGS */
  63                           "pushf\n\t"
  64                           "popl %0\n\t"
  65                           : "=a" (a), "=c" (c)
  66                           :
  67                           : "cc"
  68                           );
  69
  70         return (a!=c);
  71 }
  72 #endif
  73
  74 static void
  75 do_cpuid(unsigned int ax, unsigned int *p)
  76 {
  77 #if 0
  78         __asm __volatile(
  79         "cpuid;"
  80         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  81         :  "0" (ax)
  82         );
  83 #else
  84 // code from libavcodec:
  85     __asm __volatile
  86         ("movl %%ebx, %%esi\n\t"
  87          "cpuid\n\t"
  88          "xchgl %%ebx, %%esi"
  89          : "=a" (p[0]), "=S" (p[1]),
  90            "=c" (p[2]), "=d" (p[3])
  91          : "0" (ax));
  92 #endif
  93
  94 }
  95
  96 void GetCpuCaps( CpuCaps *caps)
  97 {
  98         unsigned int regs[4];
  99         unsigned int regs2[4];
 100
 101         memset(caps, 0, sizeof(*caps));
 102         caps->isX86=1;
 103         caps->cl_size=32; /* default */
 104         if (!has_cpuid()) {
 105             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 106             return;
 107         }
 108         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 109         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 110                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 111         if (regs[0]>=0x00000001)
 112         {
 113                 char *tmpstr;
 114                 unsigned cl_size;
 115
 116                 do_cpuid(0x00000001, regs2);
 117
 118                 tmpstr=GetCpuFriendlyName(regs, regs2);
 119                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ",tmpstr);
 120                 free(tmpstr);
 121
 122                 caps->cpuType=(regs2[0] >> 8)&0xf;
 123                 if(caps->cpuType==0xf){
 124                     // use extended family (P4, IA64)
 125                     caps->cpuType=8+((regs2[0]>>20)&255);
 126                 }
 127                 caps->cpuStepping=regs2[0] & 0xf;
 128                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Stepping: %d)\n",
 129                     caps->cpuType, caps->cpuStepping);
 130
 131                 // general feature flags:
 132                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 133                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 134                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 135                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 136                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 137                 if(cl_size) caps->cl_size = cl_size;
 138         }
 139         do_cpuid(0x80000000, regs);
 140         if (regs[0]>=0x80000001) {
 141                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 142                 do_cpuid(0x80000001, regs2);
 143                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 144                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 145                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 146                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 147         }
 148         if(regs[0]>=0x80000006)
 149         {
 150                 do_cpuid(0x80000006, regs2);
 151                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 152                 caps->cl_size  = regs2[2] & 0xFF;
 153         }
 154         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"Detected cache-line size is %u bytes\n",caps->cl_size);
 155 #if 0
 156         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 157                 gCpuCaps.hasMMX,
 158                 gCpuCaps.hasMMX2,
 159                 gCpuCaps.hasSSE,
 160                 gCpuCaps.hasSSE2,
 161                 gCpuCaps.has3DNow,
 162                 gCpuCaps.has3DNowExt );
 163 #endif
 164
 165                 /* FIXME: Does SSE2 need more OS support, too? */
 166 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__)
 167                 if (caps->hasSSE)
 168                         check_os_katmai_support();
 169                 if (!caps->hasSSE)
 170                         caps->hasSSE2 = 0;
 171 #else
 172                 caps->hasSSE=0;
 173                 caps->hasSSE2 = 0;
 174 #endif
 175 //              caps->has3DNow=1;
 176 //              caps->hasMMX2 = 0;
 177 //              caps->hasMMX = 0;
 178
 179 #ifndef HAVE_MMX
 180         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 181         caps->hasMMX=0;
 182 #endif
 183 #ifndef HAVE_MMX2
 184         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 185         caps->hasMMX2=0;
 186 #endif
 187 #ifndef HAVE_SSE
 188         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 189         caps->hasSSE=0;
 190 #endif
 191 #ifndef HAVE_SSE2
 192         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 193         caps->hasSSE2=0;
 194 #endif
 195 #ifndef HAVE_3DNOW
 196         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 197         caps->has3DNow=0;
 198 #endif
 199 #ifndef HAVE_3DNOWEX
 200         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 201         caps->has3DNowExt=0;
 202 #endif
 203 }
 204
 205
 206 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
 207 #define CPUID_EXTMODEL  ((regs2[0] >> 16)&0x0F) /* 19..16 */
 208 #define CPUID_TYPE              ((regs2[0] >> 12)&0x04) /* 13..12 */
 209 #define CPUID_FAMILY    ((regs2[0] >>  8)&0x0F) /* 11..08 */
 210 #define CPUID_MODEL             ((regs2[0] >>  4)&0x0F) /* 07..04 */
 211 #define CPUID_STEPPING  ((regs2[0] >>  0)&0x0F) /* 03..00 */
 212
 213 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 214 #include "cputable.h" /* get cpuname and cpuvendors */
 215         char vendor[17];
 216         char *retname;
 217         int i;
 218
 219         if (NULL==(retname=(char*)malloc(256))) {
 220                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 221                 exit(1);
 222         }
 223
 224         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 225
 226         for(i=0; i<MAX_VENDORS; i++){
 227                 if(!strcmp(cpuvendors[i].string,vendor)){
 228                         if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
 229                                 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
 230                         } else {
 231                                 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
 232                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name);
 233                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor:   %s\n",cpuvendors[i].string);
 234                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type:     %d\n",CPUID_TYPE);
 235                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family:   %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
 236                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model:    %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
 237                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING);
 238                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name"
 239                                        "to the MPlayer-Developers, so we can add it to the list!\n");
 240                         }
 241                 }
 242         }
 243
 244         //printf("Detected CPU: %s\n", retname);
 245         return retname;
 246 }
 247
 248 #undef CPUID_EXTFAMILY
 249 #undef CPUID_EXTMODEL
 250 #undef CPUID_TYPE
 251 #undef CPUID_FAMILY
 252 #undef CPUID_MODEL
 253 #undef CPUID_STEPPING
 254
 255
 256 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 257 static void sigill_handler_sse( int signal, struct sigcontext sc )
 258 {
 259    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 260
 261    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 262     * instructions are 3 bytes long.  We must increment the instruction
 263     * pointer manually to avoid repeated execution of the offending
 264     * instruction.
 265     *
 266     * If the SIGILL is caused by a divide-by-zero when unmasked
 267     * exceptions aren't supported, the SIMD FPU status and control
 268     * word will be restored at the end of the test, so we don't need
 269     * to worry about doing it here.  Besides, we may not be able to...
 270     */
 271    sc.eip += 3;
 272
 273    gCpuCaps.hasSSE=0;
 274 }
 275
 276 static void sigfpe_handler_sse( int signal, struct sigcontext sc )
 277 {
 278    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " );
 279
 280    if ( sc.fpstate->magic != 0xffff ) {
 281       /* Our signal context has the extended FPU state, so reset the
 282        * divide-by-zero exception mask and clear the divide-by-zero
 283        * exception bit.
 284        */
 285       sc.fpstate->mxcsr |= 0x00000200;
 286       sc.fpstate->mxcsr &= 0xfffffffb;
 287    } else {
 288       /* If we ever get here, we're completely hosed.
 289        */
 290       mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" );
 291       mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" );
 292    }
 293 }
 294 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
 295
 296 /* If we're running on a processor that can do SSE, let's see if we
 297  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 298  * haven't been configured for a Pentium III but are running on one,
 299  * and RedHat patched 2.2 kernels that have broken exception handling
 300  * support for user space apps that do SSE.
 301  */
 302 static void check_os_katmai_support( void )
 303 {
 304 #if defined(__FreeBSD__)
 305    int has_sse=0, ret;
 306    size_t len=sizeof(has_sse);
 307
 308    ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0);
 309    if (ret || !has_sse)
 310       gCpuCaps.hasSSE=0;
 311
 312 #elif defined(__NetBSD__)
 313 #if __NetBSD_Version__ >= 105250000
 314    int has_sse, has_sse2, ret, mib[2];
 315    size_t varlen;
 316
 317    mib[0] = CTL_MACHDEP;
 318    mib[1] = CPU_SSE;
 319    varlen = sizeof(has_sse);
 320
 321    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 322    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 323    if (ret < 0 || !has_sse) {
 324       gCpuCaps.hasSSE=0;
 325       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 326    } else {
 327       gCpuCaps.hasSSE=1;
 328       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 329    }
 330
 331    mib[1] = CPU_SSE2;
 332    varlen = sizeof(has_sse2);
 333    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 334    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 335    if (ret < 0 || !has_sse2) {
 336       gCpuCaps.hasSSE2=0;
 337       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 338    } else {
 339       gCpuCaps.hasSSE2=1;
 340       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 341    }
 342 #else
 343    gCpuCaps.hasSSE = 0;
 344    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 345 #endif
 346 #elif defined(__linux__)
 347 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 348    struct sigaction saved_sigill;
 349    struct sigaction saved_sigfpe;
 350
 351    /* Save the original signal handlers.
 352     */
 353    sigaction( SIGILL, NULL, &saved_sigill );
 354    sigaction( SIGFPE, NULL, &saved_sigfpe );
 355
 356    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 357    signal( SIGFPE, (void (*)(int))sigfpe_handler_sse );
 358
 359    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 360     * supports the extended FPU save and restore required for SSE.  If
 361     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 362     * doesn't support Streaming SIMD Exceptions, even if the processor
 363     * does.
 364     */
 365    if ( gCpuCaps.hasSSE ) {
 366       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 367
 368 //      __asm __volatile ("xorps %%xmm0, %%xmm0");
 369       __asm __volatile ("xorps %xmm0, %xmm0");
 370
 371       if ( gCpuCaps.hasSSE ) {
 372          mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 373       } else {
 374          mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 375       }
 376    }
 377
 378    /* Emulate test for OSXMMEXCPT in CR4.  The OS will set this bit if
 379     * it supports unmasked SIMD FPU exceptions.  If we unmask the
 380     * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
 381     * doesn't support unmasked SIMD FPU exceptions.  If we get a SIGFPE
 382     * as expected, we're okay but we need to clean up after it.
 383     *
 384     * Are we being too stringent in our requirement that the OS support
 385     * unmasked exceptions?  Certain RedHat 2.2 kernels enable SSE by
 386     * setting CR4.OSFXSR but don't support unmasked exceptions.  Win98
 387     * doesn't even support them.  We at least know the user-space SSE
 388     * support is good in kernels that do support unmasked exceptions,
 389     * and therefore to be safe I'm going to leave this test in here.
 390     */
 391    if ( gCpuCaps.hasSSE ) {
 392       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " );
 393
 394 //      test_os_katmai_exception_support();
 395
 396       if ( gCpuCaps.hasSSE ) {
 397          mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 398       } else {
 399          mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 400       }
 401    }
 402
 403    /* Restore the original signal handlers.
 404     */
 405    sigaction( SIGILL, &saved_sigill, NULL );
 406    sigaction( SIGFPE, &saved_sigfpe, NULL );
 407
 408    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 409     * safe to go ahead and hook out the SSE code throughout Mesa.
 410     */
 411    if ( gCpuCaps.hasSSE ) {
 412       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" );
 413    } else {
 414       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" );
 415    }
 416 #else
 417    /* We can't use POSIX signal handling to test the availability of
 418     * SSE, so we disable it by default.
 419     */
 420    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 421    gCpuCaps.hasSSE=0;
 422 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
 423 #else
 424    /* Do nothing on other platforms for now.
 425     */
 426    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 427    gCpuCaps.hasSSE=0;
 428 #endif /* __linux__ */
 429 }
 430 #else /* ARCH_X86 */
 431
 432 void GetCpuCaps( CpuCaps *caps)
 433 {
 434         caps->cpuType=0;
 435         caps->cpuStepping=0;
 436         caps->hasMMX=0;
 437         caps->hasMMX2=0;
 438         caps->has3DNow=0;
 439         caps->has3DNowExt=0;
 440         caps->hasSSE=0;
 441         caps->hasSSE2=0;
 442         caps->isX86=0;
 443 }
 444 #endif /* !ARCH_X86 */