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Comment out the correct #endif directive.
[mplayer/greg.git] / vidix / mga_vid.c
blobb0cef043d57c4d92968c9808d394b417e6b335db
1 /*
2 * VIDIX driver for Matrox chipsets.
3 * Copyright (C) 2002 Alex Beregszaszi
4 *
5 * This file is part of MPlayer.
6 *
7 * MPlayer is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * MPlayer is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with MPlayer; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 * Original sources from Aaron Holtzman (C) 1999.
22 * Module skeleton based on gutted agpgart module by Jeff Hartmann
23 * <slicer@ionet.net>
24 * YUY2 support added by A'rpi/ESP-team
25 double buffering added by A'rpi/ESP-team
26 * Brightness/contrast support by Nick Kurshev/Dariush Pietrzak (eyck)
27 *
28 * TODO:
29 * - fix memory size detection (current reading pci userconfig isn't
30 * working as requested - returns the max avail. ram on arch?)
31 * - translate all non-english comments to english
32 */
33
34 //#define CRTC2
35
36 // Set this value, if autodetection fails! (video ram size in megabytes)
37 //#define MGA_MEMORY_SIZE 16
38
39 /* No irq support in userspace implemented yet, do not enable this! */
40 /* disable irq */
41 #undef MGA_ALLOW_IRQ
42
43 #define MGA_VSYNC_POS 2
44
45 #undef MGA_PCICONFIG_MEMDETECT
46
47 #define MGA_DEFAULT_FRAMES 4
48
49 #include <errno.h>
50 #include <stdio.h>
51 #include <stdlib.h>
52 #include <string.h>
53 #include <math.h>
54 #include <inttypes.h>
55
56 #include "vidix.h"
57 #include "vidixlib.h"
58 #include "fourcc.h"
59 #include "dha.h"
60 #include "pci_ids.h"
61 #include "pci_names.h"
62
63 #ifdef __MINGW32__
64 #define ENOTSUP 134
65 #endif
66
67 #if !defined(ENOTSUP) && defined(EOPNOTSUPP)
68 #define ENOTSUP EOPNOTSUPP
69 #endif
70
71 /* from radeon_vid */
72 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ))))
73 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL
74
75 #define readb(addr) GETREG(uint8_t,(uint32_t)(addr),0)
76 #define writeb(val,addr) SETREG(uint8_t,(uint32_t)(addr),0,val)
77 #define readl(addr) GETREG(uint32_t,(uint32_t)(addr),0)
78 #define writel(val,addr) SETREG(uint32_t,(uint32_t)(addr),0,val)
79
80 static int mga_verbose = 0;
81
82 /* for device detection */
83 static int probed = 0;
84 static pciinfo_t pci_info;
85
86 /* internal booleans */
87 static int mga_vid_in_use = 0;
88 static int is_g400 = 0;
89 static int vid_src_ready = 0;
90 static int vid_overlay_on = 0;
91
92 /* mapped physical addresses */
93 static uint8_t *mga_mmio_base = 0;
94 static uint8_t *mga_mem_base = 0;
95
96 static int mga_src_base = 0; /* YUV buffer position in video memory */
97
98 static uint32_t mga_ram_size = 0; /* how much megabytes videoram we have */
99
100 /* Graphic keys */
101 static vidix_grkey_t mga_grkey;
102
103 static int colkey_saved = 0;
104 static int colkey_on = 0;
105 static unsigned char colkey_color[4];
106 static unsigned char colkey_mask[4];
107
108 /* for IRQ */
109 static int mga_irq = -1;
110
111 static int mga_next_frame = 0;
112
113 static vidix_capability_t mga_cap =
114 {
115 "Matrox MGA G200/G4x0/G5x0 YUV Video",
116 "Aaron Holtzman, Arpad Gereoffy, Alex Beregszaszi, Nick Kurshev",
117 TYPE_OUTPUT,
118 { 0, 0, 0, 0 },
119 2048,
120 2048,
121 4,
122 4,
123 -1,
124 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER,
125 VENDOR_MATROX,
126 -1, /* will be set in vixProbe */
127 { 0, 0, 0, 0}
128 };
129
130 /* MATROX BES registers */
131 typedef struct bes_registers_s
132 {
133 //BES Control
134 uint32_t besctl;
135 //BES Global control
136 uint32_t besglobctl;
137 //Luma control (brightness and contrast)
138 uint32_t beslumactl;
139 //Line pitch
140 uint32_t bespitch;
141
142 //Buffer A-1 Chroma 3 plane org
143 uint32_t besa1c3org;
144 //Buffer A-1 Chroma org
145 uint32_t besa1corg;
146 //Buffer A-1 Luma org
147 uint32_t besa1org;
148
149 //Buffer A-2 Chroma 3 plane org
150 uint32_t besa2c3org;
151 //Buffer A-2 Chroma org
152 uint32_t besa2corg;
153 //Buffer A-2 Luma org
154 uint32_t besa2org;
155
156 //Buffer B-1 Chroma 3 plane org
157 uint32_t besb1c3org;
158 //Buffer B-1 Chroma org
159 uint32_t besb1corg;
160 //Buffer B-1 Luma org
161 uint32_t besb1org;
162
163 //Buffer B-2 Chroma 3 plane org
164 uint32_t besb2c3org;
165 //Buffer B-2 Chroma org
166 uint32_t besb2corg;
167 //Buffer B-2 Luma org
168 uint32_t besb2org;
169
170 //BES Horizontal coord
171 uint32_t beshcoord;
172 //BES Horizontal inverse scaling [5.14]
173 uint32_t beshiscal;
174 //BES Horizontal source start [10.14] (for scaling)
175 uint32_t beshsrcst;
176 //BES Horizontal source ending [10.14] (for scaling)
177 uint32_t beshsrcend;
178 //BES Horizontal source last
179 uint32_t beshsrclst;
180
181
182 //BES Vertical coord
183 uint32_t besvcoord;
184 //BES Vertical inverse scaling [5.14]
185 uint32_t besviscal;
186 //BES Field 1 vertical source last position
187 uint32_t besv1srclst;
188 //BES Field 1 weight start
189 uint32_t besv1wght;
190 //BES Field 2 vertical source last position
191 uint32_t besv2srclst;
192 //BES Field 2 weight start
193 uint32_t besv2wght;
194
195 } bes_registers_t;
196 static bes_registers_t regs;
197
198 #ifdef CRTC2
199 typedef struct crtc2_registers_s
200 {
201 uint32_t c2ctl;
202 uint32_t c2datactl;
203 uint32_t c2misc;
204 uint32_t c2hparam;
205 uint32_t c2hsync;
206 uint32_t c2offset;
207 uint32_t c2pl2startadd0;
208 uint32_t c2pl2startadd1;
209 uint32_t c2pl3startadd0;
210 uint32_t c2pl3startadd1;
211 uint32_t c2preload;
212 uint32_t c2spicstartadd0;
213 uint32_t c2spicstartadd1;
214 uint32_t c2startadd0;
215 uint32_t c2startadd1;
216 uint32_t c2subpiclut;
217 uint32_t c2vcount;
218 uint32_t c2vparam;
219 uint32_t c2vsync;
220 } crtc2_registers_t;
221 static crtc2_registers_t cregs;
222 #endif
223
224 //All register offsets are converted to word aligned offsets (32 bit)
225 //because we want all our register accesses to be 32 bits
226 #define VCOUNT 0x1e20
227
228 #define PALWTADD 0x3c00 // Index register for X_DATAREG port
229 #define X_DATAREG 0x3c0a
230
231 #define XMULCTRL 0x19
232 #define BPP_8 0x00
233 #define BPP_15 0x01
234 #define BPP_16 0x02
235 #define BPP_24 0x03
236 #define BPP_32_DIR 0x04
237 #define BPP_32_PAL 0x07
238
239 #define XCOLMSK 0x40
240 #define X_COLKEY 0x42
241 #define XKEYOPMODE 0x51
242 #define XCOLMSK0RED 0x52
243 #define XCOLMSK0GREEN 0x53
244 #define XCOLMSK0BLUE 0x54
245 #define XCOLKEY0RED 0x55
246 #define XCOLKEY0GREEN 0x56
247 #define XCOLKEY0BLUE 0x57
248
249 #ifdef CRTC2
250 /*CRTC2 registers*/
251 #define XMISCCTRL 0x1e
252 #define C2CTL 0x3c10
253 #define C2DATACTL 0x3c4c
254 #define C2MISC 0x3c44
255 #define C2HPARAM 0x3c14
256 #define C2HSYNC 0x3c18
257 #define C2OFFSET 0x3c40
258 #define C2PL2STARTADD0 0x3c30 // like BESA1CORG
259 #define C2PL2STARTADD1 0x3c34 // like BESA2CORG
260 #define C2PL3STARTADD0 0x3c38 // like BESA1C3ORG
261 #define C2PL3STARTADD1 0x3c3c // like BESA2C3ORG
262 #define C2PRELOAD 0x3c24
263 #define C2SPICSTARTADD0 0x3c54
264 #define C2SPICSTARTADD1 0x3c58
265 #define C2STARTADD0 0x3c28 // like BESA1ORG
266 #define C2STARTADD1 0x3c2c // like BESA2ORG
267 #define C2SUBPICLUT 0x3c50
268 #define C2VCOUNT 0x3c48
269 #define C2VPARAM 0x3c1c
270 #define C2VSYNC 0x3c20
271 #endif /* CRTC2 */
272
273 // Backend Scaler registers
274 #define BESCTL 0x3d20
275 #define BESGLOBCTL 0x3dc0
276 #define BESLUMACTL 0x3d40
277 #define BESPITCH 0x3d24
278
279 #define BESA1C3ORG 0x3d60
280 #define BESA1CORG 0x3d10
281 #define BESA1ORG 0x3d00
282
283 #define BESA2C3ORG 0x3d64
284 #define BESA2CORG 0x3d14
285 #define BESA2ORG 0x3d04
286
287 #define BESB1C3ORG 0x3d68
288 #define BESB1CORG 0x3d18
289 #define BESB1ORG 0x3d08
290
291 #define BESB2C3ORG 0x3d6C
292 #define BESB2CORG 0x3d1C
293 #define BESB2ORG 0x3d0C
294
295 #define BESHCOORD 0x3d28
296 #define BESHISCAL 0x3d30
297 #define BESHSRCEND 0x3d3C
298 #define BESHSRCLST 0x3d50
299 #define BESHSRCST 0x3d38
300 #define BESV1WGHT 0x3d48
301 #define BESV2WGHT 0x3d4c
302 #define BESV1SRCLST 0x3d54
303 #define BESV2SRCLST 0x3d58
304 #define BESVISCAL 0x3d34
305 #define BESVCOORD 0x3d2c
306 #define BESSTATUS 0x3dc4
307
308 #define CRTCX 0x1fd4
309 #define CRTCD 0x1fd5
310 #define IEN 0x1e1c
311 #define ICLEAR 0x1e18
312 #define STATUS 0x1e14
313
314
315 #ifdef CRTC2
316 static void crtc2_frame_sel(int frame)
317 {
318 switch(frame) {
319 case 0:
320 cregs.c2pl2startadd0=regs.besa1corg;
321 cregs.c2pl3startadd0=regs.besa1c3org;
322 cregs.c2startadd0=regs.besa1org;
323 break;
324 case 1:
325 cregs.c2pl2startadd0=regs.besa2corg;
326 cregs.c2pl3startadd0=regs.besa2c3org;
327 cregs.c2startadd0=regs.besa2org;
328 break;
329 case 2:
330 cregs.c2pl2startadd0=regs.besb1corg;
331 cregs.c2pl3startadd0=regs.besb1c3org;
332 cregs.c2startadd0=regs.besb1org;
333 break;
334 case 3:
335 cregs.c2pl2startadd0=regs.besb2corg;
336 cregs.c2pl3startadd0=regs.besb2c3org;
337 cregs.c2startadd0=regs.besb2org;
338 break;
339 }
340 writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0);
341 writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0);
342 writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0);
343 }
344 #endif
345
346 static int mga_frame_select(unsigned int frame)
347 {
348 mga_next_frame = frame;
349 if (mga_verbose>1) printf("[mga] frameselect: %d\n", mga_next_frame);
350 #if MGA_ALLOW_IRQ
351 if (mga_irq == -1)
352 #endif
353 {
354 //we don't need the vcount protection as we're only hitting
355 //one register (and it doesn't seem to be double buffered)
356 regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25);
357 writel( regs.besctl, mga_mmio_base + BESCTL );
358
359 // writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16),
360 writel( regs.besglobctl + (MGA_VSYNC_POS<<16),
361 mga_mmio_base + BESGLOBCTL);
362 #ifdef CRTC2
363 crtc2_frame_sel(mga_next_frame);
364 #endif
365 }
366
367 return(0);
368 }
369
370
371 static void mga_vid_write_regs(int restore)
372 {
373 //Make sure internal registers don't get updated until we're done
374 writel( (readl(mga_mmio_base + VCOUNT)-1)<<16,
375 mga_mmio_base + BESGLOBCTL);
376
377 // color or coordinate keying
378
379 if(restore && colkey_saved){
380 // restore it
381 colkey_saved=0;
382
383 // Set color key registers:
384 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
385 writeb( colkey_on, mga_mmio_base + X_DATAREG);
386
387 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD);
388 writeb( colkey_color[0], mga_mmio_base + X_DATAREG);
389 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD);
390 writeb( colkey_color[1], mga_mmio_base + X_DATAREG);
391 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD);
392 writeb( colkey_color[2], mga_mmio_base + X_DATAREG);
393 writeb( X_COLKEY, mga_mmio_base + PALWTADD);
394 writeb( colkey_color[3], mga_mmio_base + X_DATAREG);
395
396 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD);
397 writeb( colkey_mask[0], mga_mmio_base + X_DATAREG);
398 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD);
399 writeb( colkey_mask[1], mga_mmio_base + X_DATAREG);
400 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD);
401 writeb( colkey_mask[2], mga_mmio_base + X_DATAREG);
402 writeb( XCOLMSK, mga_mmio_base + PALWTADD);
403 writeb( colkey_mask[3], mga_mmio_base + X_DATAREG);
404
405 } else if(!colkey_saved){
406 // save it
407 colkey_saved=1;
408 // Get color key registers:
409 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
410 colkey_on=(unsigned char)readb(mga_mmio_base + X_DATAREG) & 1;
411
412 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD);
413 colkey_color[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
414 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD);
415 colkey_color[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
416 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD);
417 colkey_color[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
418 writeb( X_COLKEY, mga_mmio_base + PALWTADD);
419 colkey_color[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
420
421 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD);
422 colkey_mask[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
423 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD);
424 colkey_mask[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
425 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD);
426 colkey_mask[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
427 writeb( XCOLMSK, mga_mmio_base + PALWTADD);
428 colkey_mask[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
429 }
430
431 if(!restore){
432 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
433 writeb( mga_grkey.ckey.op == CKEY_TRUE, mga_mmio_base + X_DATAREG);
434 if ( mga_grkey.ckey.op == CKEY_TRUE )
435 {
436 uint32_t r=0, g=0, b=0;
437
438 writeb( XMULCTRL, mga_mmio_base + PALWTADD);
439 switch (readb (mga_mmio_base + X_DATAREG))
440 {
441 case BPP_8:
442 /* Need to look up the color index, just using
443 color 0 for now. */
444 break;
445
446 case BPP_15:
447 r = mga_grkey.ckey.red >> 3;
448 g = mga_grkey.ckey.green >> 3;
449 b = mga_grkey.ckey.blue >> 3;
450 break;
451
452 case BPP_16:
453 r = mga_grkey.ckey.red >> 3;
454 g = mga_grkey.ckey.green >> 2;
455 b = mga_grkey.ckey.blue >> 3;
456 break;
457
458 case BPP_24:
459 case BPP_32_DIR:
460 case BPP_32_PAL:
461 r = mga_grkey.ckey.red;
462 g = mga_grkey.ckey.green;
463 b = mga_grkey.ckey.blue;
464 break;
465 }
466
467 // Enable colorkeying
468 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
469 writeb( 1, mga_mmio_base + X_DATAREG);
470
471 // Disable color keying on alpha channel
472 writeb( XCOLMSK, mga_mmio_base + PALWTADD);
473 writeb( 0x00, mga_mmio_base + X_DATAREG);
474 writeb( X_COLKEY, mga_mmio_base + PALWTADD);
475 writeb( 0x00, mga_mmio_base + X_DATAREG);
476
477
478 // Set up color key registers
479 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD);
480 writeb( r, mga_mmio_base + X_DATAREG);
481 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD);
482 writeb( g, mga_mmio_base + X_DATAREG);
483 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD);
484 writeb( b, mga_mmio_base + X_DATAREG);
485
486 // Set up color key mask registers
487 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD);
488 writeb( 0xff, mga_mmio_base + X_DATAREG);
489 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD);
490 writeb( 0xff, mga_mmio_base + X_DATAREG);
491 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD);
492 writeb( 0xff, mga_mmio_base + X_DATAREG);
493 }
494 else
495 {
496 // Disable colorkeying
497 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
498 writeb( 0, mga_mmio_base + X_DATAREG);
499 }
500 }
501
502 // Backend Scaler
503 writel( regs.besctl, mga_mmio_base + BESCTL);
504 if(is_g400)
505 writel( regs.beslumactl, mga_mmio_base + BESLUMACTL);
506 writel( regs.bespitch, mga_mmio_base + BESPITCH);
507
508 writel( regs.besa1org, mga_mmio_base + BESA1ORG);
509 writel( regs.besa1corg, mga_mmio_base + BESA1CORG);
510 writel( regs.besa2org, mga_mmio_base + BESA2ORG);
511 writel( regs.besa2corg, mga_mmio_base + BESA2CORG);
512 writel( regs.besb1org, mga_mmio_base + BESB1ORG);
513 writel( regs.besb1corg, mga_mmio_base + BESB1CORG);
514 writel( regs.besb2org, mga_mmio_base + BESB2ORG);
515 writel( regs.besb2corg, mga_mmio_base + BESB2CORG);
516 if(is_g400)
517 {
518 writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG);
519 writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG);
520 writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG);
521 writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG);
522 }
523
524 writel( regs.beshcoord, mga_mmio_base + BESHCOORD);
525 writel( regs.beshiscal, mga_mmio_base + BESHISCAL);
526 writel( regs.beshsrcst, mga_mmio_base + BESHSRCST);
527 writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND);
528 writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST);
529
530 writel( regs.besvcoord, mga_mmio_base + BESVCOORD);
531 writel( regs.besviscal, mga_mmio_base + BESVISCAL);
532
533 writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST);
534 writel( regs.besv1wght, mga_mmio_base + BESV1WGHT);
535 writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST);
536 writel( regs.besv2wght, mga_mmio_base + BESV2WGHT);
537
538 //update the registers somewhere between 1 and 2 frames from now.
539 writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16),
540 mga_mmio_base + BESGLOBCTL);
541
542 if (mga_verbose > 1)
543 {
544 printf("[mga] wrote BES registers\n");
545 printf("[mga] BESCTL = 0x%08x\n",
546 readl(mga_mmio_base + BESCTL));
547 printf("[mga] BESGLOBCTL = 0x%08x\n",
548 readl(mga_mmio_base + BESGLOBCTL));
549 printf("[mga] BESSTATUS= 0x%08x\n",
550 readl(mga_mmio_base + BESSTATUS));
551 }
552 #ifdef CRTC2
553 writel(((readl(mga_mmio_base + C2CTL) & ~0x03e00000) + (cregs.c2ctl & 0x03e00000)), mga_mmio_base + C2CTL);
554 writel(((readl(mga_mmio_base + C2DATACTL) & ~0x000000ff) + (cregs.c2datactl & 0x000000ff)), mga_mmio_base + C2DATACTL);
555 // ctrc2
556 // disable CRTC2 acording to specs
557 writel(cregs.c2misc, mga_mmio_base + C2MISC);
558
559 if (mga_verbose > 1) printf("[mga] c2offset = %d\n",cregs.c2offset);
560
561 writel(cregs.c2offset, mga_mmio_base + C2OFFSET);
562 writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0);
563 writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0);
564 writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0);
565 writel(cregs.c2spicstartadd0, mga_mmio_base + C2SPICSTARTADD0);
566 #endif
567 }
568
569 #ifdef MGA_ALLOW_IRQ
570 static void enable_irq(){
571 long int cc;
572
573 cc = readl(mga_mmio_base + IEN);
574
575 writeb( 0x11, mga_mmio_base + CRTCX);
576
577 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */
578 writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */
579 writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */
580
581 writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL);
582
583 return;
584 }
585
586 static void disable_irq()
587 {
588 writeb( 0x11, mga_mmio_base + CRTCX);
589 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */
590
591 return;
592 }
593
594 void mga_handle_irq(int irq, void *dev_id/*, struct pt_regs *pregs*/) {
595 long int cc;
596
597 if ( irq != -1 ) {
598
599 cc = readl(mga_mmio_base + STATUS);
600 if ( ! (cc & 0x10) ) return; /* vsyncpen */
601 }
602
603 regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25);
604 writel( regs.besctl, mga_mmio_base + BESCTL );
605
606 #ifdef CRTC2
607 // sem pridat vyber obrazku !!!!
608 crtc2_frame_sel(mga_next_frame);
609 #endif
610
611 if ( irq != -1 ) {
612 writeb( 0x11, mga_mmio_base + CRTCX);
613 writeb( 0, mga_mmio_base + CRTCD );
614 writeb( 0x10, mga_mmio_base + CRTCD );
615 }
616
617 return;
618
619 }
620 #endif /* MGA_ALLOW_IRQ */
621
622 static int mga_config_playback(vidix_playback_t *config)
623 {
624 unsigned int i;
625 int x, y, sw, sh, dw, dh;
626 int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights;
627 #ifdef CRTC2
628 #define right_margin 0
629 #define left_margin 18
630 #define hsync_len 46
631 #define lower_margin 10
632 #define vsync_len 4
633 #define upper_margin 39
634
635 unsigned int hdispend = (config->src.w + 31) & ~31;
636 unsigned int hsyncstart = hdispend + (right_margin & ~7);
637 unsigned int hsyncend = hsyncstart + (hsync_len & ~7);
638 unsigned int htotal = hsyncend + (left_margin & ~7);
639 unsigned int vdispend = config->src.h;
640 unsigned int vsyncstart = vdispend + lower_margin;
641 unsigned int vsyncend = vsyncstart + vsync_len;
642 unsigned int vtotal = vsyncend + upper_margin;
643 #endif
644
645 if ((config->num_frames < 1) || (config->num_frames > 4))
646 {
647 printf("[mga] illegal num_frames: %d, setting to %d\n",
648 config->num_frames, MGA_DEFAULT_FRAMES);
649 config->num_frames = MGA_DEFAULT_FRAMES;
650 }
651
652 x = config->dest.x;
653 y = config->dest.y;
654 sw = config->src.w;
655 sh = config->src.h;
656 dw = config->dest.w;
657 dh = config->dest.h;
658
659 config->dest.pitch.y=32;
660 config->dest.pitch.u=config->dest.pitch.v=32;
661
662 if (mga_verbose) printf("[mga] Setting up a %dx%d-%dx%d video window (src %dx%d) format %X\n",
663 dw, dh, x, y, sw, sh, config->fourcc);
664
665 if ((sw < 4) || (sh < 4) || (dw < 4) || (dh < 4))
666 {
667 printf("[mga] Invalid src/dest dimensions\n");
668 return(EINVAL);
669 }
670
671 //FIXME check that window is valid and inside desktop
672
673 sw+=sw&1;
674 switch(config->fourcc)
675 {
676 case IMGFMT_I420:
677 case IMGFMT_IYUV:
678 case IMGFMT_YV12:
679 sh+=sh&1;
680 config->frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2;
681 break;
682 case IMGFMT_YUY2:
683 case IMGFMT_UYVY:
684 config->frame_size = ((sw + 31) & ~31) * sh * 2;
685 break;
686 default:
687 printf("[mga] Unsupported pixel format: %x\n", config->fourcc);
688 return(ENOTSUP);
689 }
690
691 config->offsets[0] = 0;
692 for (i = 1; i < config->num_frames+1; i++)
693 config->offsets[i] = i*config->frame_size;
694
695 config->offset.y=0;
696 if(config->fourcc == IMGFMT_I420 || config->fourcc == IMGFMT_IYUV)
697 {
698 config->offset.u=((sw + 31) & ~31) * sh;
699 config->offset.v=config->offset.u+((sw + 31) & ~31) * sh /4;
700 }
701 else {
702 config->offset.v=((sw + 31) & ~31) * sh;
703 config->offset.u=config->offset.v+((sw + 31) & ~31) * sh /4;
704 }
705
706 mga_src_base = (mga_ram_size*0x100000-config->num_frames*config->frame_size);
707 if (mga_src_base < 0)
708 {
709 printf("[mga] not enough memory for frames!\n");
710 return(EFAULT);
711 }
712 mga_src_base &= (~0xFFFF); /* 64k boundary */
713 if (mga_verbose > 1) printf("[mga] YUV buffer base: %#x\n", mga_src_base);
714
715 config->dga_addr = mga_mem_base + mga_src_base;
716
717 /* for G200 set Interleaved UV planes */
718 if (!is_g400)
719 config->flags = VID_PLAY_INTERLEAVED_UV | INTERLEAVING_UV;
720
721 //Setup the BES registers for a three plane 4:2:0 video source
722
723 regs.besglobctl = 0;
724
725 switch(config->fourcc)
726 {
727 case IMGFMT_YV12:
728 case IMGFMT_I420:
729 case IMGFMT_IYUV:
730 regs.besctl = 1 // BES enabled
731 + (0<<6) // even start polarity
732 + (1<<10) // x filtering enabled
733 + (1<<11) // y filtering enabled
734 + (1<<16) // chroma upsampling
735 + (1<<17) // 4:2:0 mode
736 + (1<<18); // dither enabled
737 break;
738
739 case IMGFMT_YUY2:
740 regs.besctl = 1 // BES enabled
741 + (0<<6) // even start polarity
742 + (1<<10) // x filtering enabled
743 + (1<<11) // y filtering enabled
744 + (1<<16) // chroma upsampling
745 + (0<<17) // 4:2:2 mode
746 + (1<<18); // dither enabled
747
748 regs.besglobctl = 0; // YUY2 format selected
749 break;
750
751 case IMGFMT_UYVY:
752 regs.besctl = 1 // BES enabled
753 + (0<<6) // even start polarity
754 + (1<<10) // x filtering enabled
755 + (1<<11) // y filtering enabled
756 + (1<<16) // chroma upsampling
757 + (0<<17) // 4:2:2 mode
758 + (1<<18); // dither enabled
759
760 regs.besglobctl = 1<<6; // UYVY format selected
761 break;
762
763 }
764
765 //Disable contrast and brightness control
766 regs.besglobctl |= (1<<5) + (1<<7);
767 regs.beslumactl = (0x7f << 16) + (0x80<<0);
768 regs.beslumactl = 0x80<<0;
769
770 //Setup destination window boundaries
771 besleft = x > 0 ? x : 0;
772 bestop = y > 0 ? y : 0;
773 regs.beshcoord = (besleft<<16) + (x + dw-1);
774 regs.besvcoord = (bestop<<16) + (y + dh-1);
775
776 //Setup source dimensions
777 regs.beshsrclst = (sw - 1) << 16;
778 regs.bespitch = (sw + 31) & ~31 ;
779
780 //Setup horizontal scaling
781 ifactor = ((sw-1)<<14)/(dw-1);
782 ofsleft = besleft - x;
783
784 regs.beshiscal = ifactor<<2;
785 regs.beshsrcst = (ofsleft*ifactor)<<2;
786 regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2);
787
788 //Setup vertical scaling
789 ifactor = ((sh-1)<<14)/(dh-1);
790 ofstop = bestop - y;
791
792 regs.besviscal = ifactor<<2;
793
794 baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch;
795 regs.besa1org = (uint32_t) mga_src_base + baseadrofs;
796 regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size;
797 regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size;
798 regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size;
799
800 if(config->fourcc==IMGFMT_YV12
801 ||config->fourcc==IMGFMT_IYUV
802 ||config->fourcc==IMGFMT_I420
803 ){
804 // planar YUV frames:
805 if (is_g400)
806 baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch;
807 else
808 baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch;
809
810 if(config->fourcc==IMGFMT_YV12){
811 regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ;
812 regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh;
813 regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh;
814 regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh;
815 regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4);
816 regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4);
817 regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4);
818 regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4);
819 } else {
820 regs.besa1c3org = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ;
821 regs.besa2c3org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh;
822 regs.besb1c3org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh;
823 regs.besb2c3org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh;
824 regs.besa1corg = regs.besa1c3org + ((regs.bespitch * sh) / 4);
825 regs.besa2corg = regs.besa2c3org + ((regs.bespitch * sh) / 4);
826 regs.besb1corg = regs.besb1c3org + ((regs.bespitch * sh) / 4);
827 regs.besb2corg = regs.besb2c3org + ((regs.bespitch * sh) / 4);
828 }
829
830 }
831
832 weight = ofstop * (regs.besviscal >> 2);
833 weights = weight < 0 ? 1 : 0;
834 regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2);
835 regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF);
836
837 #ifdef CRTC2
838 // pridat hlavni registry - tj. casovani ...
839
840
841 switch(config->fourcc){
842 case IMGFMT_YV12:
843 case IMGFMT_I420:
844 case IMGFMT_IYUV:
845 cregs.c2ctl = 1 // CRTC2 enabled
846 + (1<<1) // external clock
847 + (0<<2) // external clock
848 + (1<<3) // pixel clock enable - not needed ???
849 + (0<<4) // high prioryty req
850 + (1<<5) // high prioryty req
851 + (0<<6) // high prioryty req
852 + (1<<8) // high prioryty req max
853 + (0<<9) // high prioryty req max
854 + (0<<10) // high prioryty req max
855 + (0<<20) // CRTC1 to DAC
856 + (1<<21) // 420 mode
857 + (1<<22) // 420 mode
858 + (1<<23) // 420 mode
859 + (0<<24) // single chroma line for 420 mode - need to be corrected
860 + (0<<25) /*/ interlace mode - need to be corrected*/
861 + (0<<26) // field legth polariry
862 + (0<<27) // field identification polariry
863 + (1<<28) // VIDRST detection mode
864 + (0<<29) // VIDRST detection mode
865 + (1<<30) // Horizontal counter preload
866 + (1<<31) // Vertical counter preload
867 ;
868 cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode
869 + (1<<1) // Y filter enable
870 + (1<<2) // CbCr filter enable
871 + (0<<3) // subpicture enable (disabled)
872 + (0<<4) // NTSC enable (disabled - PAL)
873 + (0<<5) // C2 static subpicture enable (disabled)
874 + (0<<6) // C2 subpicture offset division (disabled)
875 + (0<<7) // 422 subformat selection !
876 /* + (0<<8) // 15 bpp high alpha
877 + (0<<9) // 15 bpp high alpha
878 + (0<<10) // 15 bpp high alpha
879 + (0<<11) // 15 bpp high alpha
880 + (0<<12) // 15 bpp high alpha
881 + (0<<13) // 15 bpp high alpha
882 + (0<<14) // 15 bpp high alpha
883 + (0<<15) // 15 bpp high alpha
884 + (0<<16) // 15 bpp low alpha
885 + (0<<17) // 15 bpp low alpha
886 + (0<<18) // 15 bpp low alpha
887 + (0<<19) // 15 bpp low alpha
888 + (0<<20) // 15 bpp low alpha
889 + (0<<21) // 15 bpp low alpha
890 + (0<<22) // 15 bpp low alpha
891 + (0<<23) // 15 bpp low alpha
892 + (0<<24) // static subpicture key
893 + (0<<25) // static subpicture key
894 + (0<<26) // static subpicture key
895 + (0<<27) // static subpicture key
896 + (0<<28) // static subpicture key
897 */ ;
898 break;
899
900 case IMGFMT_YUY2:
901 cregs.c2ctl = 1 // CRTC2 enabled
902 + (1<<1) // external clock
903 + (0<<2) // external clock
904 + (1<<3) // pixel clock enable - not needed ???
905 + (0<<4) // high prioryty req - acc to spec
906 + (1<<5) // high prioryty req
907 + (0<<6) // high prioryty req
908 // 7 reserved
909 + (1<<8) // high prioryty req max
910 + (0<<9) // high prioryty req max
911 + (0<<10) // high prioryty req max
912 // 11-19 reserved
913 + (0<<20) // CRTC1 to DAC
914 + (1<<21) // 422 mode
915 + (0<<22) // 422 mode
916 + (1<<23) // 422 mode
917 + (0<<24) // single chroma line for 420 mode - need to be corrected
918 + (0<<25) /*/ interlace mode - need to be corrected*/
919 + (0<<26) // field legth polariry
920 + (0<<27) // field identification polariry
921 + (1<<28) // VIDRST detection mode
922 + (0<<29) // VIDRST detection mode
923 + (1<<30) // Horizontal counter preload
924 + (1<<31) // Vertical counter preload
925 ;
926 cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode
927 + (1<<1) // Y filter enable
928 + (1<<2) // CbCr filter enable
929 + (0<<3) // subpicture enable (disabled)
930 + (0<<4) // NTSC enable (disabled - PAL)
931 + (0<<5) // C2 static subpicture enable (disabled)
932 + (0<<6) // C2 subpicture offset division (disabled)
933 + (0<<7) // 422 subformat selection !
934 /* + (0<<8) // 15 bpp high alpha
935 + (0<<9) // 15 bpp high alpha
936 + (0<<10) // 15 bpp high alpha
937 + (0<<11) // 15 bpp high alpha
938 + (0<<12) // 15 bpp high alpha
939 + (0<<13) // 15 bpp high alpha
940 + (0<<14) // 15 bpp high alpha
941 + (0<<15) // 15 bpp high alpha
942 + (0<<16) // 15 bpp low alpha
943 + (0<<17) // 15 bpp low alpha
944 + (0<<18) // 15 bpp low alpha
945 + (0<<19) // 15 bpp low alpha
946 + (0<<20) // 15 bpp low alpha
947 + (0<<21) // 15 bpp low alpha
948 + (0<<22) // 15 bpp low alpha
949 + (0<<23) // 15 bpp low alpha
950 + (0<<24) // static subpicture key
951 + (0<<25) // static subpicture key
952 + (0<<26) // static subpicture key
953 + (0<<27) // static subpicture key
954 + (0<<28) // static subpicture key
955 */ ;
956 break;
957
958 case IMGFMT_UYVY:
959 cregs.c2ctl = 1 // CRTC2 enabled
960 + (1<<1) // external clock
961 + (0<<2) // external clock
962 + (1<<3) // pixel clock enable - not needed ???
963 + (0<<4) // high prioryty req
964 + (1<<5) // high prioryty req
965 + (0<<6) // high prioryty req
966 + (1<<8) // high prioryty req max
967 + (0<<9) // high prioryty req max
968 + (0<<10) // high prioryty req max
969 + (0<<20) // CRTC1 to DAC
970 + (1<<21) // 422 mode
971 + (0<<22) // 422 mode
972 + (1<<23) // 422 mode
973 + (1<<24) // single chroma line for 420 mode - need to be corrected
974 + (1<<25) /*/ interlace mode - need to be corrected*/
975 + (0<<26) // field legth polariry
976 + (0<<27) // field identification polariry
977 + (1<<28) // VIDRST detection mode
978 + (0<<29) // VIDRST detection mode
979 + (1<<30) // Horizontal counter preload
980 + (1<<31) // Vertical counter preload
981 ;
982 cregs.c2datactl = 0 // enable dither - propably not needed, we are already in YUV mode
983 + (1<<1) // Y filter enable
984 + (1<<2) // CbCr filter enable
985 + (0<<3) // subpicture enable (disabled)
986 + (0<<4) // NTSC enable (disabled - PAL)
987 + (0<<5) // C2 static subpicture enable (disabled)
988 + (0<<6) // C2 subpicture offset division (disabled)
989 + (1<<7) // 422 subformat selection !
990 /* + (0<<8) // 15 bpp high alpha
991 + (0<<9) // 15 bpp high alpha
992 + (0<<10) // 15 bpp high alpha
993 + (0<<11) // 15 bpp high alpha
994 + (0<<12) // 15 bpp high alpha
995 + (0<<13) // 15 bpp high alpha
996 + (0<<14) // 15 bpp high alpha
997 + (0<<15) // 15 bpp high alpha
998 + (0<<16) // 15 bpp low alpha
999 + (0<<17) // 15 bpp low alpha
1000 + (0<<18) // 15 bpp low alpha
1001 + (0<<19) // 15 bpp low alpha
1002 + (0<<20) // 15 bpp low alpha
1003 + (0<<21) // 15 bpp low alpha
1004 + (0<<22) // 15 bpp low alpha
1005 + (0<<23) // 15 bpp low alpha
1006 + (0<<24) // static subpicture key
1007 + (0<<25) // static subpicture key
1008 + (0<<26) // static subpicture key
1009 + (0<<27) // static subpicture key
1010 + (0<<28) // static subpicture key
1011 */ ;
1012 break;
1013 }
1014
1015 cregs.c2hparam=((hdispend - 8) << 16) | (htotal - 8);
1016 cregs.c2hsync=((hsyncend - 8) << 16) | (hsyncstart - 8);
1017
1018 cregs.c2misc=0 // CRTCV2 656 togg f0
1019 +(0<<1) // CRTCV2 656 togg f0
1020 +(0<<2) // CRTCV2 656 togg f0
1021 +(0<<4) // CRTCV2 656 togg f1
1022 +(0<<5) // CRTCV2 656 togg f1
1023 +(0<<6) // CRTCV2 656 togg f1
1024 +(0<<8) // Hsync active high
1025 +(0<<9) // Vsync active high
1026 // 16-27 c2vlinecomp - nevim co tam dat
1027 ;
1028 cregs.c2offset=(regs.bespitch << 1);
1029
1030 cregs.c2pl2startadd0=regs.besa1corg;
1031 cregs.c2pl3startadd0=regs.besa1c3org;
1032
1033 cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from
1034
1035 cregs.c2spicstartadd0=0; // not used
1036
1037 cregs.c2startadd0=regs.besa1org;
1038
1039 cregs.c2subpiclut=0; //not used
1040
1041 cregs.c2vparam=((vdispend - 1) << 16) | (vtotal - 1);
1042 cregs.c2vsync=((vsyncend - 1) << 16) | (vsyncstart - 1);
1043 #endif /* CRTC2 */
1044
1045 mga_vid_write_regs(0);
1046 return(0);
1047 }
1048
1049 static int mga_playback_on(void)
1050 {
1051 if (mga_verbose) printf("[mga] playback on\n");
1052
1053 vid_src_ready = 1;
1054 if(vid_overlay_on)
1055 {
1056 regs.besctl |= 1;
1057 mga_vid_write_regs(0);
1058 }
1059 #ifdef MGA_ALLOW_IRQ
1060 if (mga_irq != -1)
1061 enable_irq();
1062 #endif
1063 mga_next_frame=0;
1064
1065 return(0);
1066 }
1067
1068 static int mga_playback_off(void)
1069 {
1070 if (mga_verbose) printf("[mga] playback off\n");
1071
1072 vid_src_ready = 0;
1073 #ifdef MGA_ALLOW_IRQ
1074 if (mga_irq != -1)
1075 disable_irq();
1076 #endif
1077 regs.besctl &= ~1;
1078 regs.besglobctl &= ~(1<<6); /* UYVY format selected */
1079 mga_vid_write_regs(0);
1080
1081 return(0);
1082 }
1083
1084 static int mga_probe(int verbose,int force)
1085 {
1086 pciinfo_t lst[MAX_PCI_DEVICES];
1087 unsigned int i, num_pci;
1088 int err;
1089
1090 if (verbose) printf("[mga] probe\n");
1091
1092 mga_verbose = verbose;
1093
1094 is_g400 = -1;
1095
1096 err = pci_scan(lst, &num_pci);
1097 if (err)
1098 {
1099 printf("[mga] Error occurred during pci scan: %s\n", strerror(err));
1100 return(err);
1101 }
1102
1103 if (mga_verbose)
1104 printf("[mga] found %d pci devices\n", num_pci);
1105
1106 for (i = 0; i < num_pci; i++)
1107 {
1108 if (mga_verbose > 1)
1109 printf("[mga] pci[%d] vendor: %d device: %d\n",
1110 i, lst[i].vendor, lst[i].device);
1111 if (lst[i].vendor == VENDOR_MATROX)
1112 {
1113 #if 0
1114 if ((lst[i].command & PCI_COMMAND_IO) == 0)
1115 {
1116 printf("[mga] Device is disabled, ignoring\n");
1117 continue;
1118 }
1119 #endif
1120 switch(lst[i].device)
1121 {
1122 case DEVICE_MATROX_MGA_G550_AGP:
1123 printf("[mga] Found MGA G550\n");
1124 is_g400 = 1;
1125 goto card_found;
1126 case DEVICE_MATROX_MGA_G400_G450:
1127 printf("[mga] Found MGA G400/G450\n");
1128 is_g400 = 1;
1129 goto card_found;
1130 case DEVICE_MATROX_MGA_G200_AGP:
1131 printf("[mga] Found MGA G200 AGP\n");
1132 is_g400 = 0;
1133 goto card_found;
1134 case DEVICE_MATROX_MGA_G200:
1135 printf("[mga] Found MGA G200 PCI\n");
1136 is_g400 = 0;
1137 goto card_found;
1138 }
1139 }
1140 }
1141
1142 if (is_g400 == -1)
1143 {
1144 if (verbose) printf("[mga] Can't find chip\n");
1145 return(ENXIO);
1146 }
1147
1148 card_found:
1149 probed = 1;
1150 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
1151
1152 mga_cap.device_id = pci_info.device; /* set device id in capabilites */
1153
1154 return(0);
1155 }
1156
1157 static int mga_init(void)
1158 {
1159 unsigned int card_option = 0;
1160 int err;
1161
1162 if (mga_verbose) printf("[mga] init\n");
1163
1164 mga_vid_in_use = 0;
1165
1166 printf("Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n");
1167 #ifdef CRTC2
1168 printf("Driver compiled with TV-out (second-head) support\n");
1169 #endif
1170
1171 if (!probed)
1172 {
1173 printf("[mga] driver was not probed but is being initializing\n");
1174 return(EINTR);
1175 }
1176
1177 #ifdef MGA_PCICONFIG_MEMDETECT
1178 pci_config_read(pci_info.bus, pci_info.card, pci_info.func,
1179 0x40, 4, &card_option);
1180 if (mga_verbose > 1) printf("[mga] OPTION word: 0x%08X mem: 0x%02X %s\n", card_option,
1181 (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM");
1182 #endif
1183
1184 if (mga_ram_size)
1185 {
1186 printf("[mga] RAMSIZE forced to %d MB\n", mga_ram_size);
1187 }
1188 else
1189 {
1190 #ifdef MGA_MEMORY_SIZE
1191 mga_ram_size = MGA_MEMORY_SIZE;
1192 printf("[mga] hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size);
1193 #else
1194 if (is_g400)
1195 {
1196 switch((card_option>>10)&0x17)
1197 {
1198 // SDRAM:
1199 case 0x00:
1200 case 0x04: mga_ram_size = 16; break;
1201 case 0x03: mga_ram_size = 32; break;
1202 // SGRAM:
1203 case 0x10:
1204 case 0x14: mga_ram_size = 32; break;
1205 case 0x11:
1206 case 0x12: mga_ram_size = 16; break;
1207 default:
1208 mga_ram_size = 16;
1209 printf("[mga] Couldn't detect RAMSIZE, assuming 16MB!\n");
1210 }
1211 }
1212 else
1213 {
1214 switch((card_option>>10)&0x17)
1215 {
1216 default: mga_ram_size = 8;
1217 }
1218 }
1219
1220 printf("[mga] detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size);
1221 #endif
1222 }
1223
1224 if (mga_ram_size)
1225 {
1226 if ((mga_ram_size < 4) || (mga_ram_size > 64))
1227 {
1228 printf("[mga] invalid RAMSIZE: %d MB\n", mga_ram_size);
1229 return(EINVAL);
1230 }
1231 }
1232
1233 if (mga_verbose > 1) printf("[mga] hardware addresses: mmio: %#x, framebuffer: %#x\n",
1234 pci_info.base1, pci_info.base0);
1235
1236 mga_mmio_base = map_phys_mem(pci_info.base1,0x4000);
1237 mga_mem_base = map_phys_mem(pci_info.base0,mga_ram_size*1024*1024);
1238
1239 if (mga_verbose > 1) printf("[mga] MMIO at %p, IRQ: %d, framebuffer: %p\n",
1240 mga_mmio_base, mga_irq, mga_mem_base);
1241 err = mtrr_set_type(pci_info.base0,mga_ram_size*1024*1024,MTRR_TYPE_WRCOMB);
1242 if(!err) printf("[mga] Set write-combining type of video memory\n");
1243 #ifdef MGA_ALLOW_IRQ
1244 if (mga_irq != -1)
1245 {
1246 int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq);
1247 if (tmp)
1248 {
1249 printf("syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp);
1250 mga_irq=-1;
1251 }
1252 else
1253 {
1254 printf("syncfb (mga): registered irq %d\n", mga_irq);
1255 }
1256 }
1257 else
1258 {
1259 printf("syncfb (mga): No valid irq was found\n");
1260 mga_irq=-1;
1261 }
1262 #else
1263 printf("syncfb (mga): IRQ disabled in mga_vid.c\n");
1264 mga_irq=-1;
1265 #endif
1266
1267 return(0);
1268 }
1269
1270 static void mga_destroy(void)
1271 {
1272 if (mga_verbose) printf("[mga] destroy\n");
1273
1274 /* FIXME turn off BES */
1275 vid_src_ready = 0;
1276 regs.besctl &= ~1;
1277 regs.besglobctl &= ~(1<<6); // UYVY format selected
1278 mga_vid_write_regs(1);
1279 mga_vid_in_use = 0;
1280
1281 #ifdef MGA_ALLOW_IRQ
1282 if (mga_irq != -1)
1283 free_irq(mga_irq, &mga_irq);
1284 #endif
1285
1286 if (mga_mmio_base)
1287 unmap_phys_mem(mga_mmio_base, 0x4000);
1288 if (mga_mem_base)
1289 unmap_phys_mem(mga_mem_base, mga_ram_size);
1290 return;
1291 }
1292
1293 static int mga_query_fourcc(vidix_fourcc_t *to)
1294 {
1295 if (mga_verbose) printf("[mga] query fourcc (%x)\n", to->fourcc);
1296
1297 switch(to->fourcc)
1298 {
1299 case IMGFMT_YV12:
1300 case IMGFMT_IYUV:
1301 case IMGFMT_I420:
1302 case IMGFMT_YUY2:
1303 case IMGFMT_UYVY:
1304 break;
1305 default:
1306 to->depth = to->flags = 0;
1307 return(ENOTSUP);
1308 }
1309
1310 to->depth = VID_DEPTH_12BPP |
1311 VID_DEPTH_15BPP | VID_DEPTH_16BPP |
1312 VID_DEPTH_24BPP | VID_DEPTH_32BPP;
1313 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
1314 return(0);
1315 }
1316
1317 static int mga_get_caps(vidix_capability_t *to)
1318 {
1319 memcpy(to, &mga_cap, sizeof(vidix_capability_t));
1320 return(0);
1321 }
1322
1323 static int mga_get_gkeys(vidix_grkey_t *grkey)
1324 {
1325 memcpy(grkey, &mga_grkey, sizeof(vidix_grkey_t));
1326 return(0);
1327 }
1328
1329 static int mga_set_gkeys(const vidix_grkey_t *grkey)
1330 {
1331 memcpy(&mga_grkey, grkey, sizeof(vidix_grkey_t));
1332 mga_vid_write_regs(0);
1333 return(0);
1334 }
1335
1336 static int mga_set_eq( const vidix_video_eq_t * eq)
1337 {
1338 /* contrast and brightness control isn't supported on G200 - alex */
1339 if (!is_g400)
1340 {
1341 if (mga_verbose) printf("[mga] equalizer isn't supported with G200\n");
1342 return(ENOTSUP);
1343 }
1344
1345 // only brightness&contrast are supported:
1346 if(!(eq->cap & (VEQ_CAP_BRIGHTNESS|VEQ_CAP_CONTRAST)))
1347 return(ENOTSUP);
1348
1349 //regs.beslumactl = readl(mga_mmio_base + BESLUMACTL);
1350 if (eq->cap & VEQ_CAP_BRIGHTNESS) {
1351 regs.beslumactl &= 0xFFFF;
1352 regs.beslumactl |= (eq->brightness*255/2000)<<16;
1353 }
1354 if (eq->cap & VEQ_CAP_CONTRAST) {
1355 regs.beslumactl &= 0xFFFF0000;
1356 regs.beslumactl |= (128+eq->contrast*255/2000)&0xFFFF;
1357 }
1358 writel(regs.beslumactl,mga_mmio_base + BESLUMACTL);
1359
1360 return(0);
1361 }
1362
1363 static int mga_get_eq( vidix_video_eq_t * eq)
1364 {
1365 /* contrast and brightness control isn't supported on G200 - alex */
1366 if (!is_g400)
1367 {
1368 if (mga_verbose) printf("[mga] equalizer isn't supported with G200\n");
1369 return(ENOTSUP);
1370 }
1371
1372 eq->brightness = (signed short int)(regs.beslumactl >> 16) * 1000 / 128;
1373 eq->contrast = (signed short int)(regs.beslumactl & 0xFFFF) * 1000 / 128 - 1000;
1374 eq->cap = VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST;
1375
1376 printf("MGA GET_EQ: br=%d c=%d \n",eq->brightness,eq->contrast);
1377
1378 return(0);
1379 }
1380
1381 #ifndef CRTC2
1382 VDXDriver mga_drv = {
1383 "mga",
1384 #else
1385 VDXDriver mga_crtc2_drv = {
1386 "mga_crtc2",
1387 #endif
1388 NULL,
1389
1390 .probe = mga_probe,
1391 .get_caps = mga_get_caps,
1392 .query_fourcc = mga_query_fourcc,
1393 .init = mga_init,
1394 .destroy = mga_destroy,
1395 .config_playback = mga_config_playback,
1396 .playback_on = mga_playback_on,
1397 .playback_off = mga_playback_off,
1398 .frame_sel = mga_frame_select,
1399 .get_eq = mga_get_eq,
1400 .set_eq = mga_set_eq,
1401 .get_gkey = mga_get_gkeys,
1402 .set_gkey = mga_set_gkeys,
1403 };