cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #ifdef HAVE_MALLOC_H
   8 #include <malloc.h>
   9 #endif
  10 #include <stdlib.h>
  11
  12 #ifdef ARCH_X86
  13
  14 #include <stdio.h>
  15 #include <string.h>
  16 #include "osdep/timer.h"
  17
  18 #ifdef __NetBSD__
  19 #include <sys/param.h>
  20 #include <sys/sysctl.h>
  21 #include <machine/cpu.h>
  22 #endif
  23
  24 #ifdef __FreeBSD__
  25 #include <sys/types.h>
  26 #include <sys/sysctl.h>
  27 #endif
  28
  29 #ifdef __linux__
  30 #include <signal.h>
  31 #endif
  32
  33 #ifdef WIN32
  34 #include <windows.h>
  35 #endif
  36
  37 //#define X86_FXSR_MAGIC
  38 /* Thanks to the FreeBSD project for some of this cpuid code, and
  39  * help understanding how to use it.  Thanks to the Mesa
  40  * team for SSE support detection and more cpu detect code.
  41  */
  42
  43 /* I believe this code works.  However, it has only been used on a PII and PIII */
  44
  45 static void check_os_katmai_support( void );
  46
  47 #if 1
  48 // return TRUE if cpuid supported
  49 static int has_cpuid()
  50 {
  51         int a, c;
  52
  53 // code from libavcodec:
  54     __asm__ __volatile__ (
  55                           /* See if CPUID instruction is supported ... */
  56                           /* ... Get copies of EFLAGS into eax and ecx */
  57                           "pushf\n\t"
  58                           "popl %0\n\t"
  59                           "movl %0, %1\n\t"
  60
  61                           /* ... Toggle the ID bit in one copy and store */
  62                           /*     to the EFLAGS reg */
  63                           "xorl $0x200000, %0\n\t"
  64                           "push %0\n\t"
  65                           "popf\n\t"
  66
  67                           /* ... Get the (hopefully modified) EFLAGS */
  68                           "pushf\n\t"
  69                           "popl %0\n\t"
  70                           : "=a" (a), "=c" (c)
  71                           :
  72                           : "cc"
  73                           );
  74
  75         return (a!=c);
  76 }
  77 #endif
  78
  79 static void
  80 do_cpuid(unsigned int ax, unsigned int *p)
  81 {
  82 #if 0
  83         __asm __volatile(
  84         "cpuid;"
  85         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  86         :  "0" (ax)
  87         );
  88 #else
  89 // code from libavcodec:
  90     __asm __volatile
  91         ("movl %%ebx, %%esi\n\t"
  92          "cpuid\n\t"
  93          "xchgl %%ebx, %%esi"
  94          : "=a" (p[0]), "=S" (p[1]),
  95            "=c" (p[2]), "=d" (p[3])
  96          : "0" (ax));
  97 #endif
  98
  99 }
 100
 101 void GetCpuCaps( CpuCaps *caps)
 102 {
 103         unsigned int regs[4];
 104         unsigned int regs2[4];
 105
 106         memset(caps, 0, sizeof(*caps));
 107         caps->isX86=1;
 108         caps->cl_size=32; /* default */
 109         if (!has_cpuid()) {
 110             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 111             return;
 112         }
 113         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 114         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 115                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 116         if (regs[0]>=0x00000001)
 117         {
 118                 char *tmpstr;
 119                 unsigned cl_size;
 120
 121                 do_cpuid(0x00000001, regs2);
 122
 123                 caps->cpuType=(regs2[0] >> 8)&0xf;
 124                 if(caps->cpuType==0xf){
 125                     // use extended family (P4, IA64)
 126                     caps->cpuType=8+((regs2[0]>>20)&255);
 127                 }
 128                 caps->cpuStepping=regs2[0] & 0xf;
 129
 130                 // general feature flags:
 131                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 132                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 133                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 134                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 135                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 136                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 137                 if(cl_size) caps->cl_size = cl_size;
 138
 139                 tmpstr=GetCpuFriendlyName(regs, regs2);
 140                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ",tmpstr);
 141                 free(tmpstr);
 142                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Stepping: %d)\n",
 143                     caps->cpuType, caps->cpuStepping);
 144
 145         }
 146         do_cpuid(0x80000000, regs);
 147         if (regs[0]>=0x80000001) {
 148                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 149                 do_cpuid(0x80000001, regs2);
 150                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 151                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 152                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 153                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 154         }
 155         if(regs[0]>=0x80000006)
 156         {
 157                 do_cpuid(0x80000006, regs2);
 158                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 159                 caps->cl_size  = regs2[2] & 0xFF;
 160         }
 161         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"Detected cache-line size is %u bytes\n",caps->cl_size);
 162 #if 0
 163         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 164                 gCpuCaps.hasMMX,
 165                 gCpuCaps.hasMMX2,
 166                 gCpuCaps.hasSSE,
 167                 gCpuCaps.hasSSE2,
 168                 gCpuCaps.has3DNow,
 169                 gCpuCaps.has3DNowExt );
 170 #endif
 171
 172                 /* FIXME: Does SSE2 need more OS support, too? */
 173 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__CYGWIN__)
 174                 if (caps->hasSSE)
 175                         check_os_katmai_support();
 176                 if (!caps->hasSSE)
 177                         caps->hasSSE2 = 0;
 178 #else
 179                 caps->hasSSE=0;
 180                 caps->hasSSE2 = 0;
 181 #endif
 182 //              caps->has3DNow=1;
 183 //              caps->hasMMX2 = 0;
 184 //              caps->hasMMX = 0;
 185
 186 #ifndef HAVE_MMX
 187         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 188         caps->hasMMX=0;
 189 #endif
 190 #ifndef HAVE_MMX2
 191         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 192         caps->hasMMX2=0;
 193 #endif
 194 #ifndef HAVE_SSE
 195         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 196         caps->hasSSE=0;
 197 #endif
 198 #ifndef HAVE_SSE2
 199         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 200         caps->hasSSE2=0;
 201 #endif
 202 #ifndef HAVE_3DNOW
 203         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 204         caps->has3DNow=0;
 205 #endif
 206 #ifndef HAVE_3DNOWEX
 207         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 208         caps->has3DNowExt=0;
 209 #endif
 210 }
 211
 212
 213 static inline unsigned long long int rdtsc( void )
 214 {
 215   unsigned long long int retval;
 216   __asm __volatile ("rdtsc":"=A"(retval)::"memory");
 217   return retval;
 218 }
 219
 220 /* Returns CPU clock in khz */
 221 static unsigned int GetCpuSpeed(void)
 222 {
 223         unsigned long long int tscstart, tscstop;
 224         unsigned int start, stop;
 225
 226         tscstart = rdtsc();
 227         start = GetTimer();
 228         usec_sleep(50000);
 229         stop = GetTimer();
 230         tscstop = rdtsc();
 231
 232         return((tscstop-tscstart)/((stop-start)/1000.0));
 233 }
 234
 235
 236 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
 237 #define CPUID_EXTMODEL  ((regs2[0] >> 16)&0x0F) /* 19..16 */
 238 #define CPUID_TYPE              ((regs2[0] >> 12)&0x04) /* 13..12 */
 239 #define CPUID_FAMILY    ((regs2[0] >>  8)&0x0F) /* 11..08 */
 240 #define CPUID_MODEL             ((regs2[0] >>  4)&0x0F) /* 07..04 */
 241 #define CPUID_STEPPING  ((regs2[0] >>  0)&0x0F) /* 03..00 */
 242
 243 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 244 #include "cputable.h" /* get cpuname and cpuvendors */
 245         char vendor[17], cpuspeed[16];
 246         char *retname;
 247         int i=0;
 248
 249         if (NULL==(retname=(char*)malloc(256))) {
 250                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 251                 exit(1);
 252         }
 253
 254         /* Measure CPU speed */
 255         if (gCpuCaps.hasTSC && (i = GetCpuSpeed()) > 0) {
 256                 if (i < 1000000) {
 257                         i += 50; /* for rounding */
 258                         snprintf(cpuspeed,15, " %d.%d MHz", i/1000, (i/100)%10);
 259                 } else {
 260                         //i += 500; /* for rounding */
 261                         snprintf(cpuspeed,15, " %d MHz", i/1000);
 262                 }
 263         } else { /* No TSC Support */
 264                 cpuspeed[0]='\0';
 265         }
 266
 267
 268         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 269
 270         for(i=0; i<MAX_VENDORS; i++){
 271                 if(!strcmp(cpuvendors[i].string,vendor)){
 272                         if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
 273                                 snprintf(retname,255,"%s %s%s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL],cpuspeed);
 274                         } else {
 275                                 snprintf(retname,255,"unknown %s %d. Generation CPU%s",cpuvendors[i].name,CPUID_FAMILY,cpuspeed);
 276                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name);
 277                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor:   %s\n",cpuvendors[i].string);
 278                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type:     %d\n",CPUID_TYPE);
 279                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family:   %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
 280                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model:    %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
 281                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING);
 282                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name"
 283                                        "to the MPlayer-Developers, so we can add it to the list!\n");
 284                         }
 285                 }
 286         }
 287
 288         //printf("Detected CPU: %s\n", retname);
 289         return retname;
 290 }
 291
 292 #undef CPUID_EXTFAMILY
 293 #undef CPUID_EXTMODEL
 294 #undef CPUID_TYPE
 295 #undef CPUID_FAMILY
 296 #undef CPUID_MODEL
 297 #undef CPUID_STEPPING
 298
 299
 300 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 301 static void sigill_handler_sse( int signal, struct sigcontext sc )
 302 {
 303    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 304
 305    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 306     * instructions are 3 bytes long.  We must increment the instruction
 307     * pointer manually to avoid repeated execution of the offending
 308     * instruction.
 309     *
 310     * If the SIGILL is caused by a divide-by-zero when unmasked
 311     * exceptions aren't supported, the SIMD FPU status and control
 312     * word will be restored at the end of the test, so we don't need
 313     * to worry about doing it here.  Besides, we may not be able to...
 314     */
 315    sc.eip += 3;
 316
 317    gCpuCaps.hasSSE=0;
 318 }
 319
 320 static void sigfpe_handler_sse( int signal, struct sigcontext sc )
 321 {
 322    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " );
 323
 324    if ( sc.fpstate->magic != 0xffff ) {
 325       /* Our signal context has the extended FPU state, so reset the
 326        * divide-by-zero exception mask and clear the divide-by-zero
 327        * exception bit.
 328        */
 329       sc.fpstate->mxcsr |= 0x00000200;
 330       sc.fpstate->mxcsr &= 0xfffffffb;
 331    } else {
 332       /* If we ever get here, we're completely hosed.
 333        */
 334       mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" );
 335       mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" );
 336    }
 337 }
 338 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
 339
 340 #ifdef WIN32
 341 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 342 {
 343    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 344       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 345       ep->ContextRecord->Eip +=3;
 346       gCpuCaps.hasSSE=0;
 347           return EXCEPTION_CONTINUE_EXECUTION;
 348    }
 349    return EXCEPTION_CONTINUE_SEARCH;
 350 }
 351 #endif /* WIN32 */
 352
 353 /* If we're running on a processor that can do SSE, let's see if we
 354  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 355  * haven't been configured for a Pentium III but are running on one,
 356  * and RedHat patched 2.2 kernels that have broken exception handling
 357  * support for user space apps that do SSE.
 358  */
 359 static void check_os_katmai_support( void )
 360 {
 361 #if defined(__FreeBSD__)
 362    int has_sse=0, ret;
 363    size_t len=sizeof(has_sse);
 364
 365    ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0);
 366    if (ret || !has_sse)
 367       gCpuCaps.hasSSE=0;
 368
 369 #elif defined(__NetBSD__)
 370 #if __NetBSD_Version__ >= 105250000
 371    int has_sse, has_sse2, ret, mib[2];
 372    size_t varlen;
 373
 374    mib[0] = CTL_MACHDEP;
 375    mib[1] = CPU_SSE;
 376    varlen = sizeof(has_sse);
 377
 378    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 379    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 380    if (ret < 0 || !has_sse) {
 381       gCpuCaps.hasSSE=0;
 382       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 383    } else {
 384       gCpuCaps.hasSSE=1;
 385       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 386    }
 387
 388    mib[1] = CPU_SSE2;
 389    varlen = sizeof(has_sse2);
 390    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 391    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 392    if (ret < 0 || !has_sse2) {
 393       gCpuCaps.hasSSE2=0;
 394       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 395    } else {
 396       gCpuCaps.hasSSE2=1;
 397       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 398    }
 399 #else
 400    gCpuCaps.hasSSE = 0;
 401    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 402 #endif
 403 #elif defined(WIN32)
 404    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 405    if ( gCpuCaps.hasSSE ) {
 406       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 407       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 408       __asm __volatile ("xorps %xmm0, %xmm0");
 409       SetUnhandledExceptionFilter(exc_fil);
 410       if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 411       else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 412    }
 413 #elif defined(__linux__)
 414 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 415    struct sigaction saved_sigill;
 416    struct sigaction saved_sigfpe;
 417
 418    /* Save the original signal handlers.
 419     */
 420    sigaction( SIGILL, NULL, &saved_sigill );
 421    sigaction( SIGFPE, NULL, &saved_sigfpe );
 422
 423    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 424    signal( SIGFPE, (void (*)(int))sigfpe_handler_sse );
 425
 426    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 427     * supports the extended FPU save and restore required for SSE.  If
 428     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 429     * doesn't support Streaming SIMD Exceptions, even if the processor
 430     * does.
 431     */
 432    if ( gCpuCaps.hasSSE ) {
 433       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 434
 435 //      __asm __volatile ("xorps %%xmm0, %%xmm0");
 436       __asm __volatile ("xorps %xmm0, %xmm0");
 437
 438       if ( gCpuCaps.hasSSE ) {
 439          mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 440       } else {
 441          mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 442       }
 443    }
 444
 445    /* Emulate test for OSXMMEXCPT in CR4.  The OS will set this bit if
 446     * it supports unmasked SIMD FPU exceptions.  If we unmask the
 447     * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
 448     * doesn't support unmasked SIMD FPU exceptions.  If we get a SIGFPE
 449     * as expected, we're okay but we need to clean up after it.
 450     *
 451     * Are we being too stringent in our requirement that the OS support
 452     * unmasked exceptions?  Certain RedHat 2.2 kernels enable SSE by
 453     * setting CR4.OSFXSR but don't support unmasked exceptions.  Win98
 454     * doesn't even support them.  We at least know the user-space SSE
 455     * support is good in kernels that do support unmasked exceptions,
 456     * and therefore to be safe I'm going to leave this test in here.
 457     */
 458    if ( gCpuCaps.hasSSE ) {
 459       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " );
 460
 461 //      test_os_katmai_exception_support();
 462
 463       if ( gCpuCaps.hasSSE ) {
 464          mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 465       } else {
 466          mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 467       }
 468    }
 469
 470    /* Restore the original signal handlers.
 471     */
 472    sigaction( SIGILL, &saved_sigill, NULL );
 473    sigaction( SIGFPE, &saved_sigfpe, NULL );
 474
 475    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 476     * safe to go ahead and hook out the SSE code throughout Mesa.
 477     */
 478    if ( gCpuCaps.hasSSE ) {
 479       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" );
 480    } else {
 481       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" );
 482    }
 483 #else
 484    /* We can't use POSIX signal handling to test the availability of
 485     * SSE, so we disable it by default.
 486     */
 487    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 488    gCpuCaps.hasSSE=0;
 489 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
 490 #else
 491    /* Do nothing on other platforms for now.
 492     */
 493    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 494    gCpuCaps.hasSSE=0;
 495 #endif /* __linux__ */
 496 }
 497 #else /* ARCH_X86 */
 498
 499 #ifdef SYS_DARWIN
 500 #include <sys/sysctl.h>
 501 #else
 502 #include <signal.h>
 503 #include <setjmp.h>
 504
 505 static sigjmp_buf jmpbuf;
 506 static volatile sig_atomic_t canjump = 0;
 507
 508 static void sigill_handler (int sig)
 509 {
 510     if (!canjump) {
 511         signal (sig, SIG_DFL);
 512         raise (sig);
 513     }
 514
 515     canjump = 0;
 516     siglongjmp (jmpbuf, 1);
 517 }
 518 #endif
 519
 520 void GetCpuCaps( CpuCaps *caps)
 521 {
 522         caps->cpuType=0;
 523         caps->cpuStepping=0;
 524         caps->hasMMX=0;
 525         caps->hasMMX2=0;
 526         caps->has3DNow=0;
 527         caps->has3DNowExt=0;
 528         caps->hasSSE=0;
 529         caps->hasSSE2=0;
 530         caps->isX86=0;
 531         caps->hasAltiVec = 0;
 532 #ifdef HAVE_ALTIVEC
 533 #ifdef SYS_DARWIN
 534 /*
 535   rip-off from ffmpeg altivec detection code.
 536   this code also appears on Apple's AltiVec pages.
 537  */
 538         {
 539                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 540                 int has_vu = 0;
 541                 size_t len = sizeof(has_vu);
 542                 int err;
 543
 544                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 545
 546                 if (err == 0)
 547                         if (has_vu != 0)
 548                                 caps->hasAltiVec = 1;
 549         }
 550 #else /* SYS_DARWIN */
 551 /* no Darwin, do it the brute-force way */
 552 /* this is borrowed from the libmpeg2 library */
 553         {
 554           signal (SIGILL, sigill_handler);
 555           if (sigsetjmp (jmpbuf, 1)) {
 556             signal (SIGILL, SIG_DFL);
 557           } else {
 558             canjump = 1;
 559
 560             asm volatile ("mtspr 256, %0\n\t"
 561                           "vand %%v0, %%v0, %%v0"
 562                           :
 563                           : "r" (-1));
 564
 565             signal (SIGILL, SIG_DFL);
 566             caps->hasAltiVec = 1;
 567           }
 568         }
 569 #endif /* SYS_DARWIN */
 570         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 571 #endif /* HAVE_ALTIVEC */
 572 }
 573 #endif /* !ARCH_X86 */