17 #if defined (__NetBSD__) || defined(__OpenBSD__)
18 #include <sys/param.h>
19 #include <sys/sysctl.h>
20 #include <machine/cpu.h>
23 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
24 #include <sys/types.h>
25 #include <sys/sysctl.h>
42 #include <proto/exec.h>
45 /* Thanks to the FreeBSD project for some of this cpuid code, and
46 * help understanding how to use it. Thanks to the Mesa
47 * team for SSE support detection and more cpu detect code.
50 /* I believe this code works. However, it has only been used on a PII and PIII */
52 static void check_os_katmai_support( void );
55 // return TRUE if cpuid supported
56 static int has_cpuid(void)
60 // code from libavcodec:
61 __asm__
__volatile__ (
62 /* See if CPUID instruction is supported ... */
63 /* ... Get copies of EFLAGS into eax and ecx */
68 /* ... Toggle the ID bit in one copy and store */
69 /* to the EFLAGS reg */
70 "xor $0x200000, %0\n\t"
74 /* ... Get the (hopefully modified) EFLAGS */
87 do_cpuid(unsigned int ax
, unsigned int *p
)
92 : "=a" (p
[0]), "=b" (p
[1]), "=c" (p
[2]), "=d" (p
[3])
96 // code from libavcodec:
98 ("mov %%"REG_b
", %%"REG_S
"\n\t"
100 "xchg %%"REG_b
", %%"REG_S
101 : "=a" (p
[0]), "=S" (p
[1]),
102 "=c" (p
[2]), "=d" (p
[3])
108 void GetCpuCaps( CpuCaps
*caps
)
110 unsigned int regs
[4];
111 unsigned int regs2
[4];
113 memset(caps
, 0, sizeof(*caps
));
115 caps
->cl_size
=32; /* default */
117 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"CPUID not supported!??? (maybe an old 486?)\n");
120 do_cpuid(0x00000000, regs
); // get _max_ cpuid level and vendor name
121 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n",
122 (char*) (regs
+1),(char*) (regs
+3),(char*) (regs
+2), regs
[0]);
123 if (regs
[0]>=0x00000001)
125 char *tmpstr
, *ptmpstr
;
128 do_cpuid(0x00000001, regs2
);
130 caps
->cpuType
=(regs2
[0] >> 8)&0xf;
131 caps
->cpuModel
=(regs2
[0] >> 4)&0xf;
133 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
134 // System Instructions, Table 3-2: Effective family computation, page 120.
135 if(caps
->cpuType
==0xf){
136 // use extended family (P4, IA64, K8)
137 caps
->cpuType
=0xf+((regs2
[0]>>20)&255);
139 if(caps
->cpuType
==0xf || caps
->cpuType
==6)
140 caps
->cpuModel
|= ((regs2
[0]>>16)&0xf) << 4;
142 caps
->cpuStepping
=regs2
[0] & 0xf;
144 // general feature flags:
145 caps
->hasTSC
= (regs2
[3] & (1 << 8 )) >> 8; // 0x0000010
146 caps
->hasMMX
= (regs2
[3] & (1 << 23 )) >> 23; // 0x0800000
147 caps
->hasSSE
= (regs2
[3] & (1 << 25 )) >> 25; // 0x2000000
148 caps
->hasSSE2
= (regs2
[3] & (1 << 26 )) >> 26; // 0x4000000
149 caps
->hasMMX2
= caps
->hasSSE
; // SSE cpus supports mmxext too
150 cl_size
= ((regs2
[1] >> 8) & 0xFF)*8;
151 if(cl_size
) caps
->cl_size
= cl_size
;
153 ptmpstr
=tmpstr
=GetCpuFriendlyName(regs
, regs2
);
154 while(*ptmpstr
== ' ') // strip leading spaces
156 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: %s ", ptmpstr
);
158 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"(Family: %d, Model: %d, Stepping: %d)\n",
159 caps
->cpuType
, caps
->cpuModel
, caps
->cpuStepping
);
162 do_cpuid(0x80000000, regs
);
163 if (regs
[0]>=0x80000001) {
164 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"extended cpuid-level: %d\n",regs
[0]&0x7FFFFFFF);
165 do_cpuid(0x80000001, regs2
);
166 caps
->hasMMX
|= (regs2
[3] & (1 << 23 )) >> 23; // 0x0800000
167 caps
->hasMMX2
|= (regs2
[3] & (1 << 22 )) >> 22; // 0x400000
168 caps
->has3DNow
= (regs2
[3] & (1 << 31 )) >> 31; //0x80000000
169 caps
->has3DNowExt
= (regs2
[3] & (1 << 30 )) >> 30;
171 if(regs
[0]>=0x80000006)
173 do_cpuid(0x80000006, regs2
);
174 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"extended cache-info: %d\n",regs2
[2]&0x7FFFFFFF);
175 caps
->cl_size
= regs2
[2] & 0xFF;
177 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"Detected cache-line size is %u bytes\n",caps
->cl_size
);
179 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
185 gCpuCaps
.has3DNowExt
);
188 /* FIXME: Does SSE2 need more OS support, too? */
189 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \
190 || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \
191 || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \
194 check_os_katmai_support();
202 // caps->hasMMX2 = 0;
205 #ifndef RUNTIME_CPUDETECT
207 if(caps
->hasMMX
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"MMX supported but disabled\n");
211 if(caps
->hasMMX2
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"MMX2 supported but disabled\n");
215 if(caps
->hasSSE
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"SSE supported but disabled\n");
219 if(caps
->hasSSE2
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"SSE2 supported but disabled\n");
223 if(caps
->has3DNow
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"3DNow supported but disabled\n");
227 if(caps
->has3DNowExt
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"3DNowExt supported but disabled\n");
230 #endif // RUNTIME_CPUDETECT
234 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
235 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */
236 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */
237 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */
238 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */
239 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */
241 char *GetCpuFriendlyName(unsigned int regs
[], unsigned int regs2
[]){
242 #include "cputable.h" /* get cpuname and cpuvendors */
247 if (NULL
==(retname
=malloc(256))) {
248 mp_msg(MSGT_CPUDETECT
,MSGL_FATAL
,"Error: GetCpuFriendlyName() not enough memory\n");
252 sprintf(vendor
,"%.4s%.4s%.4s",(char*)(regs
+1),(char*)(regs
+3),(char*)(regs
+2));
254 do_cpuid(0x80000000,regs
);
255 if (regs
[0] >= 0x80000004)
257 // CPU has built-in namestring
259 for (i
= 0x80000002; i
<= 0x80000004; i
++)
262 strncat(retname
, (char*)regs
, 16);
267 for(i
=0; i
<MAX_VENDORS
; i
++){
268 if(!strcmp(cpuvendors
[i
].string
,vendor
)){
269 if(cpuname
[i
][CPUID_FAMILY
][CPUID_MODEL
]){
270 snprintf(retname
,255,"%s %s",cpuvendors
[i
].name
,cpuname
[i
][CPUID_FAMILY
][CPUID_MODEL
]);
272 snprintf(retname
,255,"unknown %s %d. Generation CPU",cpuvendors
[i
].name
,CPUID_FAMILY
);
273 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"unknown %s CPU:\n",cpuvendors
[i
].name
);
274 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Vendor: %s\n",cpuvendors
[i
].string
);
275 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Type: %d\n",CPUID_TYPE
);
276 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Family: %d (ext: %d)\n",CPUID_FAMILY
,CPUID_EXTFAMILY
);
277 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Model: %d (ext: %d)\n",CPUID_MODEL
,CPUID_EXTMODEL
);
278 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Stepping: %d\n",CPUID_STEPPING
);
279 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Please send the above info along with the exact CPU name"
280 "to the MPlayer-Developers, so we can add it to the list!\n");
286 //printf("Detected CPU: %s\n", retname);
290 #undef CPUID_EXTFAMILY
291 #undef CPUID_EXTMODEL
295 #undef CPUID_STEPPING
298 #if defined(__linux__) && defined(_POSIX_SOURCE) && !defined(ARCH_X86_64)
299 static void sigill_handler_sse( int signal
, struct sigcontext sc
)
301 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "SIGILL, " );
303 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
304 * instructions are 3 bytes long. We must increment the instruction
305 * pointer manually to avoid repeated execution of the offending
308 * If the SIGILL is caused by a divide-by-zero when unmasked
309 * exceptions aren't supported, the SIMD FPU status and control
310 * word will be restored at the end of the test, so we don't need
311 * to worry about doing it here. Besides, we may not be able to...
317 #endif /* __linux__ && _POSIX_SOURCE */
320 LONG CALLBACK
win32_sig_handler_sse(EXCEPTION_POINTERS
* ep
)
322 if(ep
->ExceptionRecord
->ExceptionCode
==EXCEPTION_ILLEGAL_INSTRUCTION
){
323 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "SIGILL, " );
324 ep
->ContextRecord
->Eip
+=3;
326 return EXCEPTION_CONTINUE_EXECUTION
;
328 return EXCEPTION_CONTINUE_SEARCH
;
333 ULONG _System
os2_sig_handler_sse( PEXCEPTIONREPORTRECORD p1
,
334 PEXCEPTIONREGISTRATIONRECORD p2
,
338 if(p1
->ExceptionNum
== XCPT_ILLEGAL_INSTRUCTION
){
339 mp_msg(MSGT_CPUDETECT
, MSGL_V
, "SIGILL, ");
344 return XCPT_CONTINUE_EXECUTION
;
346 return XCPT_CONTINUE_SEARCH
;
350 /* If we're running on a processor that can do SSE, let's see if we
351 * are allowed to or not. This will catch 2.4.0 or later kernels that
352 * haven't been configured for a Pentium III but are running on one,
353 * and RedHat patched 2.2 kernels that have broken exception handling
354 * support for user space apps that do SSE.
357 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
358 #define SSE_SYSCTL_NAME "hw.instruction_sse"
359 #elif defined(__APPLE__)
360 #define SSE_SYSCTL_NAME "hw.optional.sse"
363 static void check_os_katmai_support( void )
368 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
370 size_t len
=sizeof(has_sse
);
372 ret
= sysctlbyname(SSE_SYSCTL_NAME
, &has_sse
, &len
, NULL
, 0);
376 #elif defined(__NetBSD__) || defined (__OpenBSD__)
377 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
378 int has_sse
, has_sse2
, ret
, mib
[2];
381 mib
[0] = CTL_MACHDEP
;
383 varlen
= sizeof(has_sse
);
385 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE... " );
386 ret
= sysctl(mib
, 2, &has_sse
, &varlen
, NULL
, 0);
387 if (ret
< 0 || !has_sse
) {
389 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "no!\n" );
392 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "yes!\n" );
396 varlen
= sizeof(has_sse2
);
397 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE2... " );
398 ret
= sysctl(mib
, 2, &has_sse2
, &varlen
, NULL
, 0);
399 if (ret
< 0 || !has_sse2
) {
401 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "no!\n" );
404 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "yes!\n" );
408 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
, "No OS support for SSE, disabling to be safe.\n" );
411 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil
;
412 if ( gCpuCaps
.hasSSE
) {
413 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE... " );
414 exc_fil
= SetUnhandledExceptionFilter(win32_sig_handler_sse
);
415 __asm
__volatile ("xorps %xmm0, %xmm0");
416 SetUnhandledExceptionFilter(exc_fil
);
417 if ( gCpuCaps
.hasSSE
) mp_msg(MSGT_CPUDETECT
,MSGL_V
, "yes.\n" );
418 else mp_msg(MSGT_CPUDETECT
,MSGL_V
, "no!\n" );
420 #elif defined(__OS2__)
421 EXCEPTIONREGISTRATIONRECORD RegRec
= { 0, &os2_sig_handler_sse
};
422 if ( gCpuCaps
.hasSSE
) {
423 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE... " );
424 DosSetExceptionHandler( &RegRec
);
425 __asm
__volatile ("xorps %xmm0, %xmm0");
426 DosUnsetExceptionHandler( &RegRec
);
427 if ( gCpuCaps
.hasSSE
) mp_msg(MSGT_CPUDETECT
,MSGL_V
, "yes.\n" );
428 else mp_msg(MSGT_CPUDETECT
,MSGL_V
, "no!\n" );
430 #elif defined(__linux__)
431 #if defined(_POSIX_SOURCE)
432 struct sigaction saved_sigill
;
434 /* Save the original signal handlers.
436 sigaction( SIGILL
, NULL
, &saved_sigill
);
438 signal( SIGILL
, (void (*)(int))sigill_handler_sse
);
440 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it
441 * supports the extended FPU save and restore required for SSE. If
442 * we execute an SSE instruction on a PIII and get a SIGILL, the OS
443 * doesn't support Streaming SIMD Exceptions, even if the processor
446 if ( gCpuCaps
.hasSSE
) {
447 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE... " );
449 // __asm __volatile ("xorps %%xmm0, %%xmm0");
450 __asm
__volatile ("xorps %xmm0, %xmm0");
452 if ( gCpuCaps
.hasSSE
) {
453 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "yes.\n" );
455 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "no!\n" );
459 /* Restore the original signal handlers.
461 sigaction( SIGILL
, &saved_sigill
, NULL
);
463 /* If we've gotten to here and the XMM CPUID bit is still set, we're
464 * safe to go ahead and hook out the SSE code throughout Mesa.
466 if ( gCpuCaps
.hasSSE
) {
467 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Tests of OS support for SSE passed.\n" );
469 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Tests of OS support for SSE failed!\n" );
472 /* We can't use POSIX signal handling to test the availability of
473 * SSE, so we disable it by default.
475 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
, "Cannot test OS support for SSE, disabling to be safe.\n" );
477 #endif /* _POSIX_SOURCE */
479 /* Do nothing on other platforms for now.
481 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
, "Cannot test OS support for SSE, leaving disabled.\n" );
483 #endif /* __linux__ */
488 #include <sys/sysctl.h>
495 static sigjmp_buf jmpbuf
;
496 static volatile sig_atomic_t canjump
= 0;
498 static void sigill_handler (int sig
)
501 signal (sig
, SIG_DFL
);
506 siglongjmp (jmpbuf
, 1);
508 #endif /* __APPLE__ */
510 void GetCpuCaps( CpuCaps
*caps
)
522 caps
->hasAltiVec
= 0;
526 rip-off from ffmpeg altivec detection code.
527 this code also appears on Apple's AltiVec pages.
530 int sels
[2] = {CTL_HW
, HW_VECTORUNIT
};
532 size_t len
= sizeof(has_vu
);
535 err
= sysctl(sels
, 2, &has_vu
, &len
, NULL
, 0);
539 caps
->hasAltiVec
= 1;
544 GetCPUInfoTags(GCIT_VectorUnit
, &result
, TAG_DONE
);
545 if (result
== VECTORTYPE_ALTIVEC
)
546 caps
->hasAltiVec
= 1;
548 /* no Darwin, do it the brute-force way */
549 /* this is borrowed from the libmpeg2 library */
551 signal (SIGILL
, sigill_handler
);
552 if (sigsetjmp (jmpbuf
, 1)) {
553 signal (SIGILL
, SIG_DFL
);
557 asm volatile ("mtspr 256, %0\n\t"
558 "vand %%v0, %%v0, %%v0"
562 signal (SIGILL
, SIG_DFL
);
563 caps
->hasAltiVec
= 1;
566 #endif /* __APPLE__ */
567 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"AltiVec %sfound\n", (caps
->hasAltiVec
? "" : "not "));
568 #endif /* HAVE_ALTIVEC */
571 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: Intel Itanium\n");
575 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: Sun Sparc\n");
579 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: ARM\n");
583 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: PowerPC\n");
587 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: Digital Alpha\n");
591 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: SGI MIPS\n");
595 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: Hewlett-Packard PA-RISC\n");
599 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: IBM S/390\n");
603 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: IBM S/390X\n");
607 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
, "CPU: Digital VAX\n" );
611 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
, "CPU: Tensilica Xtensa\n" );
614 #endif /* !ARCH_X86 */