cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #if HAVE_MALLOC_H
   8 #include <malloc.h>
   9 #endif
  10 #include <stdlib.h>
  11
  12 #if ARCH_X86
  13
  14 #include <stdio.h>
  15 #include <string.h>
  16
  17 #if defined (__NetBSD__) || defined(__OpenBSD__)
  18 #include <sys/param.h>
  19 #include <sys/sysctl.h>
  20 #include <machine/cpu.h>
  21 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
  22 #include <sys/types.h>
  23 #include <sys/sysctl.h>
  24 #elif defined(__linux__)
  25 #include <signal.h>
  26 #elif defined(__MINGW32__) || defined(__CYGWIN__)
  27 #include <windows.h>
  28 #elif defined(__OS2__)
  29 #define INCL_DOS
  30 #include <os2.h>
  31 #elif defined(__AMIGAOS4__)
  32 #include <proto/exec.h>
  33 #endif
  34
  35 /* Thanks to the FreeBSD project for some of this cpuid code, and
  36  * help understanding how to use it.  Thanks to the Mesa
  37  * team for SSE support detection and more cpu detect code.
  38  */
  39
  40 /* I believe this code works.  However, it has only been used on a PII and PIII */
  41
  42 static void check_os_katmai_support( void );
  43
  44 // return TRUE if cpuid supported
  45 static int has_cpuid(void)
  46 {
  47         long a, c;
  48
  49 // code from libavcodec:
  50 #if ARCH_X86_64
  51 #define PUSHF "pushfq\n\t"
  52 #define POPF "popfq\n\t"
  53 #else
  54 #define PUSHF "pushfl\n\t"
  55 #define POPF "popfl\n\t"
  56 #endif
  57     __asm__ volatile (
  58                           /* See if CPUID instruction is supported ... */
  59                           /* ... Get copies of EFLAGS into eax and ecx */
  60                           PUSHF
  61                           "pop %0\n\t"
  62                           "mov %0, %1\n\t"
  63
  64                           /* ... Toggle the ID bit in one copy and store */
  65                           /*     to the EFLAGS reg */
  66                           "xor $0x200000, %0\n\t"
  67                           "push %0\n\t"
  68                           POPF
  69
  70                           /* ... Get the (hopefully modified) EFLAGS */
  71                           PUSHF
  72                           "pop %0\n\t"
  73                           : "=a" (a), "=c" (c)
  74                           :
  75                           : "cc"
  76                           );
  77 #undef PUSHF
  78 #undef POPF
  79
  80         return a != c;
  81 }
  82
  83 static void
  84 do_cpuid(unsigned int ax, unsigned int *p)
  85 {
  86 #if 0
  87         __asm__ volatile(
  88         "cpuid;"
  89         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  90         :  "0" (ax)
  91         );
  92 #else
  93 // code from libavcodec:
  94     __asm__ volatile
  95         ("mov %%"REG_b", %%"REG_S"\n\t"
  96          "cpuid\n\t"
  97          "xchg %%"REG_b", %%"REG_S
  98          : "=a" (p[0]), "=S" (p[1]),
  99            "=c" (p[2]), "=d" (p[3])
 100          : "0" (ax));
 101 #endif
 102
 103 }
 104
 105 void GetCpuCaps( CpuCaps *caps)
 106 {
 107         unsigned int regs[4];
 108         unsigned int regs2[4];
 109
 110         memset(caps, 0, sizeof(*caps));
 111         caps->isX86=1;
 112         caps->cl_size=32; /* default */
 113         if (!has_cpuid()) {
 114             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 115             return;
 116         }
 117         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 118         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 119                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 120         if (regs[0]>=0x00000001)
 121         {
 122                 char *tmpstr, *ptmpstr;
 123                 unsigned cl_size;
 124
 125                 do_cpuid(0x00000001, regs2);
 126
 127                 caps->cpuType=(regs2[0] >> 8)&0xf;
 128                 caps->cpuModel=(regs2[0] >> 4)&0xf;
 129
 130 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 131 // System Instructions, Table 3-2: Effective family computation, page 120.
 132                 if(caps->cpuType==0xf){
 133                     // use extended family (P4, IA64, K8)
 134                     caps->cpuType=0xf+((regs2[0]>>20)&255);
 135                 }
 136                 if(caps->cpuType==0xf || caps->cpuType==6)
 137                     caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 138
 139                 caps->cpuStepping=regs2[0] & 0xf;
 140
 141                 // general feature flags:
 142                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 143                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 144                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 145                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 146                 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >>  9; // 0x0000200
 147                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 148                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 149                 if(cl_size) caps->cl_size = cl_size;
 150
 151                 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 152                 while(*ptmpstr == ' ')        // strip leading spaces
 153                     ptmpstr++;
 154                 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr);
 155                 free(tmpstr);
 156                 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n",
 157                     caps->cpuType, caps->cpuModel, caps->cpuStepping);
 158
 159         }
 160         do_cpuid(0x80000000, regs);
 161         if (regs[0]>=0x80000001) {
 162                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 163                 do_cpuid(0x80000001, regs2);
 164                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 165                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 166                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 167                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 168                 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >>  6; // 0x0000040
 169         }
 170         if(regs[0]>=0x80000006)
 171         {
 172                 do_cpuid(0x80000006, regs2);
 173                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 174                 caps->cl_size  = regs2[2] & 0xFF;
 175         }
 176         mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 177 #if 0
 178         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 179                 gCpuCaps.hasMMX,
 180                 gCpuCaps.hasMMX2,
 181                 gCpuCaps.hasSSE,
 182                 gCpuCaps.hasSSE2,
 183                 gCpuCaps.has3DNow,
 184                 gCpuCaps.has3DNowExt );
 185 #endif
 186
 187                 /* FIXME: Does SSE2 need more OS support, too? */
 188 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \
 189   || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \
 190   || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \
 191   || defined(__OS2__)
 192                 if (caps->hasSSE)
 193                         check_os_katmai_support();
 194                 if (!caps->hasSSE)
 195                         caps->hasSSE2 = 0;
 196 #else
 197                 caps->hasSSE=0;
 198                 caps->hasSSE2 = 0;
 199 #endif
 200 //              caps->has3DNow=1;
 201 //              caps->hasMMX2 = 0;
 202 //              caps->hasMMX = 0;
 203
 204 #ifndef RUNTIME_CPUDETECT
 205 #if !HAVE_MMX
 206         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 207         caps->hasMMX=0;
 208 #endif
 209 #if !HAVE_MMX2
 210         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 211         caps->hasMMX2=0;
 212 #endif
 213 #if !HAVE_SSE
 214         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 215         caps->hasSSE=0;
 216 #endif
 217 #if !HAVE_SSE2
 218         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 219         caps->hasSSE2=0;
 220 #endif
 221 #if !HAVE_AMD3DNOW
 222         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 223         caps->has3DNow=0;
 224 #endif
 225 #if !HAVE_AMD3DNOWEXT
 226         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 227         caps->has3DNowExt=0;
 228 #endif
 229 #endif  // RUNTIME_CPUDETECT
 230 }
 231
 232
 233 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
 234 #define CPUID_EXTMODEL  ((regs2[0] >> 16)&0x0F) /* 19..16 */
 235 #define CPUID_TYPE              ((regs2[0] >> 12)&0x04) /* 13..12 */
 236 #define CPUID_FAMILY    ((regs2[0] >>  8)&0x0F) /* 11..08 */
 237 #define CPUID_MODEL             ((regs2[0] >>  4)&0x0F) /* 07..04 */
 238 #define CPUID_STEPPING  ((regs2[0] >>  0)&0x0F) /* 03..00 */
 239
 240 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 241 #include "cputable.h" /* get cpuname and cpuvendors */
 242         char vendor[13];
 243         char *retname;
 244         int i;
 245
 246         if (NULL==(retname=malloc(256))) {
 247                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 248                 exit(1);
 249         }
 250
 251         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 252
 253         do_cpuid(0x80000000,regs);
 254         if (regs[0] >= 0x80000004)
 255         {
 256                 // CPU has built-in namestring
 257                 retname[0] = '\0';
 258                 for (i = 0x80000002; i <= 0x80000004; i++)
 259                 {
 260                         do_cpuid(i, regs);
 261                         strncat(retname, (char*)regs, 16);
 262                 }
 263                 return retname;
 264         }
 265
 266         for(i=0; i<MAX_VENDORS; i++){
 267                 if(!strcmp(cpuvendors[i].string,vendor)){
 268                         if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
 269                                 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
 270                         } else {
 271                                 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
 272                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name);
 273                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor:   %s\n",cpuvendors[i].string);
 274                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type:     %d\n",CPUID_TYPE);
 275                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family:   %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
 276                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model:    %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
 277                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING);
 278                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name"
 279                                        "to the MPlayer-Developers, so we can add it to the list!\n");
 280                         }
 281                 }
 282         }
 283         retname[255] = 0;
 284
 285         //printf("Detected CPU: %s\n", retname);
 286         return retname;
 287 }
 288
 289 #undef CPUID_EXTFAMILY
 290 #undef CPUID_EXTMODEL
 291 #undef CPUID_TYPE
 292 #undef CPUID_FAMILY
 293 #undef CPUID_MODEL
 294 #undef CPUID_STEPPING
 295
 296
 297 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64
 298 static void sigill_handler_sse( int signal, struct sigcontext sc )
 299 {
 300    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 301
 302    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 303     * instructions are 3 bytes long.  We must increment the instruction
 304     * pointer manually to avoid repeated execution of the offending
 305     * instruction.
 306     *
 307     * If the SIGILL is caused by a divide-by-zero when unmasked
 308     * exceptions aren't supported, the SIMD FPU status and control
 309     * word will be restored at the end of the test, so we don't need
 310     * to worry about doing it here.  Besides, we may not be able to...
 311     */
 312    sc.eip += 3;
 313
 314    gCpuCaps.hasSSE=0;
 315 }
 316 #endif /* __linux__ && _POSIX_SOURCE */
 317
 318 #if defined(__MINGW32__) || defined(__CYGWIN__)
 319 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 320 {
 321    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 322       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 323       ep->ContextRecord->Eip +=3;
 324       gCpuCaps.hasSSE=0;
 325           return EXCEPTION_CONTINUE_EXECUTION;
 326    }
 327    return EXCEPTION_CONTINUE_SEARCH;
 328 }
 329 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
 330
 331 #ifdef __OS2__
 332 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD       p1,
 333                                    PEXCEPTIONREGISTRATIONRECORD p2,
 334                                    PCONTEXTRECORD               p3,
 335                                    PVOID                        p4 )
 336 {
 337    if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
 338       mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
 339
 340       p3->ctx_RegEip += 3;
 341       gCpuCaps.hasSSE = 0;
 342
 343       return XCPT_CONTINUE_EXECUTION;
 344    }
 345    return XCPT_CONTINUE_SEARCH;
 346 }
 347 #endif
 348
 349 /* If we're running on a processor that can do SSE, let's see if we
 350  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 351  * haven't been configured for a Pentium III but are running on one,
 352  * and RedHat patched 2.2 kernels that have broken exception handling
 353  * support for user space apps that do SSE.
 354  */
 355
 356 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
 357 #define SSE_SYSCTL_NAME "hw.instruction_sse"
 358 #elif defined(__APPLE__)
 359 #define SSE_SYSCTL_NAME "hw.optional.sse"
 360 #endif
 361
 362 static void check_os_katmai_support( void )
 363 {
 364 #if ARCH_X86_64
 365    gCpuCaps.hasSSE=1;
 366    gCpuCaps.hasSSE2=1;
 367 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 368    int has_sse=0, ret;
 369    size_t len=sizeof(has_sse);
 370
 371    ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 372    if (ret || !has_sse)
 373       gCpuCaps.hasSSE=0;
 374
 375 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 376 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 377    int has_sse, has_sse2, ret, mib[2];
 378    size_t varlen;
 379
 380    mib[0] = CTL_MACHDEP;
 381    mib[1] = CPU_SSE;
 382    varlen = sizeof(has_sse);
 383
 384    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 385    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 386    gCpuCaps.hasSSE = ret >= 0 && has_sse;
 387    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 388
 389    mib[1] = CPU_SSE2;
 390    varlen = sizeof(has_sse2);
 391    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 392    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 393    gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
 394    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
 395 #else
 396    gCpuCaps.hasSSE = 0;
 397    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 398 #endif
 399 #elif defined(__MINGW32__) || defined(__CYGWIN__)
 400    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 401    if ( gCpuCaps.hasSSE ) {
 402       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 403       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 404       __asm__ volatile ("xorps %xmm0, %xmm0");
 405       SetUnhandledExceptionFilter(exc_fil);
 406       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 407    }
 408 #elif defined(__OS2__)
 409    EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
 410    if ( gCpuCaps.hasSSE ) {
 411       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 412       DosSetExceptionHandler( &RegRec );
 413       __asm__ volatile ("xorps %xmm0, %xmm0");
 414       DosUnsetExceptionHandler( &RegRec );
 415       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 416    }
 417 #elif defined(__linux__)
 418 #if defined(_POSIX_SOURCE)
 419    struct sigaction saved_sigill;
 420
 421    /* Save the original signal handlers.
 422     */
 423    sigaction( SIGILL, NULL, &saved_sigill );
 424
 425    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 426
 427    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 428     * supports the extended FPU save and restore required for SSE.  If
 429     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 430     * doesn't support Streaming SIMD Exceptions, even if the processor
 431     * does.
 432     */
 433    if ( gCpuCaps.hasSSE ) {
 434       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 435
 436 //      __asm__ volatile ("xorps %%xmm0, %%xmm0");
 437       __asm__ volatile ("xorps %xmm0, %xmm0");
 438
 439       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 440    }
 441
 442    /* Restore the original signal handlers.
 443     */
 444    sigaction( SIGILL, &saved_sigill, NULL );
 445
 446    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 447     * safe to go ahead and hook out the SSE code throughout Mesa.
 448     */
 449    mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
 450 #else
 451    /* We can't use POSIX signal handling to test the availability of
 452     * SSE, so we disable it by default.
 453     */
 454    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 455    gCpuCaps.hasSSE=0;
 456 #endif /* _POSIX_SOURCE */
 457 #else
 458    /* Do nothing on other platforms for now.
 459     */
 460    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 461    gCpuCaps.hasSSE=0;
 462 #endif /* __linux__ */
 463 }
 464 #else /* ARCH_X86 */
 465
 466 #ifdef __APPLE__
 467 #include <sys/sysctl.h>
 468 #elif defined(__AMIGAOS4__)
 469 /* nothing */
 470 #else
 471 #include <signal.h>
 472 #include <setjmp.h>
 473
 474 static sigjmp_buf jmpbuf;
 475 static volatile sig_atomic_t canjump = 0;
 476
 477 static void sigill_handler (int sig)
 478 {
 479     if (!canjump) {
 480         signal (sig, SIG_DFL);
 481         raise (sig);
 482     }
 483
 484     canjump = 0;
 485     siglongjmp (jmpbuf, 1);
 486 }
 487 #endif /* __APPLE__ */
 488
 489 void GetCpuCaps( CpuCaps *caps)
 490 {
 491         caps->cpuType=0;
 492         caps->cpuModel=0;
 493         caps->cpuStepping=0;
 494         caps->hasMMX=0;
 495         caps->hasMMX2=0;
 496         caps->has3DNow=0;
 497         caps->has3DNowExt=0;
 498         caps->hasSSE=0;
 499         caps->hasSSE2=0;
 500         caps->hasSSSE3=0;
 501         caps->hasSSE4a=0;
 502         caps->isX86=0;
 503         caps->hasAltiVec = 0;
 504 #if HAVE_ALTIVEC
 505 #ifdef __APPLE__
 506 /*
 507   rip-off from ffmpeg altivec detection code.
 508   this code also appears on Apple's AltiVec pages.
 509  */
 510         {
 511                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 512                 int has_vu = 0;
 513                 size_t len = sizeof(has_vu);
 514                 int err;
 515
 516                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 517
 518                 if (err == 0)
 519                         if (has_vu != 0)
 520                                 caps->hasAltiVec = 1;
 521         }
 522 #elif defined(__AMIGAOS4__)
 523         ULONG result = 0;
 524
 525         GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 526         if (result == VECTORTYPE_ALTIVEC)
 527                 caps->hasAltiVec = 1;
 528 #else
 529 /* no Darwin, do it the brute-force way */
 530 /* this is borrowed from the libmpeg2 library */
 531         {
 532           signal (SIGILL, sigill_handler);
 533           if (sigsetjmp (jmpbuf, 1)) {
 534             signal (SIGILL, SIG_DFL);
 535           } else {
 536             canjump = 1;
 537
 538             __asm__ volatile ("mtspr 256, %0\n\t"
 539                           "vand %%v0, %%v0, %%v0"
 540                           :
 541                           : "r" (-1));
 542
 543             signal (SIGILL, SIG_DFL);
 544             caps->hasAltiVec = 1;
 545           }
 546         }
 547 #endif /* __APPLE__ */
 548         mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 549 #endif /* HAVE_ALTIVEC */
 550
 551 if (ARCH_IA64)
 552         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n");
 553
 554 if (ARCH_SPARC)
 555         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n");
 556
 557 if (ARCH_ARM)
 558         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n");
 559
 560 if (ARCH_PPC)
 561         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n");
 562
 563 if (ARCH_ALPHA)
 564         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n");
 565
 566 if (ARCH_SGI_MIPS)
 567         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: SGI MIPS\n");
 568
 569 if (ARCH_PA_RISC)
 570         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n");
 571
 572 if (ARCH_S390)
 573         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n");
 574
 575 if (ARCH_S390X)
 576         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n");
 577
 578 if (ARCH_VAX)
 579         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" );
 580
 581 if (ARCH_XTENSA)
 582         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" );
 583 }
 584 #endif /* !ARCH_X86 */