vidix/nvidia_vid.c

   1 /*
   2  * VIDIX driver for nVidia chipsets.
   3  *
   4  * Copyright (C) 2003-2004 Sascha Sommer
   5  * This file is based on sources from RIVATV (rivatv.sf.net)
   6  * Multi buffer support and TNT2 fixes by Dmitry Baryshkov.
   7  *
   8  * This file is part of MPlayer.
   9  *
  10  * MPlayer is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * MPlayer is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with MPlayer; if not, write to the Free Software Foundation, Inc.,
  22  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  23  */
  24
  25 #include <errno.h>
  26 #include <stdio.h>
  27 #include <stdlib.h>
  28 #include <string.h>
  29 #include <math.h>
  30 #include <inttypes.h>
  31 #include <unistd.h>
  32
  33
  34 #include "config.h"
  35 #include "vidix.h"
  36 #include "fourcc.h"
  37 #include "dha.h"
  38 #include "pci_ids.h"
  39 #include "pci_names.h"
  40 #include "libavutil/common.h"
  41 #include "mpbswap.h"
  42
  43
  44 static pciinfo_t pci_info;
  45
  46
  47 #define MAX_FRAMES 3
  48 #define NV04_BES_SIZE 1024*2000*4
  49
  50
  51 static vidix_capability_t nvidia_cap = {
  52     "NVIDIA RIVA OVERLAY DRIVER",
  53     "Sascha Sommer <saschasommer@freenet.de>",
  54     TYPE_OUTPUT,
  55     { 0, 0, 0, 0 },
  56     2046,
  57     2046,
  58     4,
  59     4,
  60     -1,
  61     FLAG_UPSCALER|FLAG_DOWNSCALER,
  62     VENDOR_NVIDIA2,
  63     -1,
  64     { 0, 0, 0, 0 }
  65 };
  66
  67 #define NV_ARCH_03  0x03
  68 #define NV_ARCH_04  0x04
  69 #define NV_ARCH_10  0x10
  70 #define NV_ARCH_20  0x20
  71 #define NV_ARCH_30  0x30
  72 #define NV_ARCH_40  0x40
  73
  74 // since no useful information whatsoever is passed
  75 // to the equalizer functions we need this
  76 static struct {
  77   uint32_t lum; // luminance (brightness + contrast)
  78   uint32_t chrom; // chrominance (saturation + hue)
  79   uint8_t red_off; // for NV03/NV04
  80   uint8_t green_off;
  81   uint8_t blue_off;
  82   vidix_video_eq_t vals;
  83 } eq;
  84
  85 struct nvidia_cards {
  86   unsigned short chip_id;
  87   unsigned short arch;
  88 };
  89
  90
  91 static struct nvidia_cards nvidia_card_ids[] = {
  92   /*NV03*/
  93   {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03},
  94   {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03},
  95   /*NV04*/
  96   {DEVICE_NVIDIA_NV4_RIVA_TNT,NV_ARCH_04},
  97   {DEVICE_NVIDIA_NV5_RIVA_TNT2_TNT2,NV_ARCH_04},
  98   {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04},
  99   {DEVICE_NVIDIA_NV5_RIVA_TNT22,NV_ARCH_04},
 100   {DEVICE_NVIDIA_NV5_RIVA_TNT23,NV_ARCH_04},
 101   {DEVICE_NVIDIA_NV6_VANTA_VANTA_LT,NV_ARCH_04},
 102   {DEVICE_NVIDIA_NV5M64_RIVA_TNT2,NV_ARCH_04},
 103   {DEVICE_NVIDIA_NV6_VANTA,NV_ARCH_04},
 104   {DEVICE_NVIDIA_NV6_VANTA2,NV_ARCH_04},
 105   {DEVICE_NVIDIA2_TNT,NV_ARCH_04},
 106   {DEVICE_NVIDIA2_TNT2,NV_ARCH_04},
 107   {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04},
 108   {DEVICE_NVIDIA2_UTNT2 ,NV_ARCH_04},
 109   {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04},
 110   {DEVICE_NVIDIA_NV5_ALADDIN_TNT2,NV_ARCH_04},
 111   /*NV10*/
 112   {DEVICE_NVIDIA_NV18_GEFORCE_PCX,NV_ARCH_10},
 113   {DEVICE_NVIDIA_NV10_GEFORCE_256,NV_ARCH_10},
 114   {DEVICE_NVIDIA_NV10DDR_GEFORCE_256,NV_ARCH_10},
 115   {DEVICE_NVIDIA_NV10GL_QUADRO,NV_ARCH_10},
 116   {DEVICE_NVIDIA_NV11_GEFORCE2_MX_MX,NV_ARCH_10},
 117   {DEVICE_NVIDIA_NV11DDR_GEFORCE2_MX,NV_ARCH_10},
 118   {DEVICE_NVIDIA_NV11_GEFORCE2_GO,NV_ARCH_10},
 119   {DEVICE_NVIDIA_NV11GL_QUADRO2_MXR_EX_GO,NV_ARCH_10},
 120   {DEVICE_NVIDIA_NV15_GEFORCE2_GTS_PRO,NV_ARCH_10},
 121   {DEVICE_NVIDIA_NV15DDR_GEFORCE2_TI,NV_ARCH_10},
 122   {DEVICE_NVIDIA_NV15BR_GEFORCE2_ULTRA,NV_ARCH_10},
 123   {DEVICE_NVIDIA_NV15GL_QUADRO2_PRO,NV_ARCH_10},
 124   {DEVICE_NVIDIA_NV17_GEFORCE4_MX,NV_ARCH_10},
 125   {DEVICE_NVIDIA_NV17_GEFORCE4_MX2,NV_ARCH_10},
 126   {DEVICE_NVIDIA_NV17_GEFORCE4_MX3,NV_ARCH_10},
 127   {DEVICE_NVIDIA_NV17_GEFORCE4_MX4,NV_ARCH_10},
 128   {DEVICE_NVIDIA_NV17_GEFORCE4_440,NV_ARCH_10},
 129   {DEVICE_NVIDIA_NV17_GEFORCE4_420,NV_ARCH_10},
 130   {DEVICE_NVIDIA_NV17_GEFORCE4_4202,NV_ARCH_10},
 131   {DEVICE_NVIDIA_NV17_GEFORCE4_460,NV_ARCH_10},
 132   {DEVICE_NVIDIA_NV17GL_QUADRO4_550,NV_ARCH_10},
 133   {DEVICE_NVIDIA_NV17_GEFORCE4_4203,NV_ARCH_10},
 134   {DEVICE_NVIDIA_NV17GL_QUADRO4_200_400,NV_ARCH_10},
 135   {DEVICE_NVIDIA_NV17GL_QUADRO4_5502,NV_ARCH_10},
 136   {DEVICE_NVIDIA_NV17GL_QUADRO4_550,NV_ARCH_10},
 137   {DEVICE_NVIDIA_NV17_GEFORCE4_410,NV_ARCH_10},
 138   {DEVICE_NVIDIA_NV18_GEFORCE4_MX,NV_ARCH_10},
 139   {DEVICE_NVIDIA_NV18_GEFORCE4_MX2,NV_ARCH_10},
 140   {DEVICE_NVIDIA_NV18_GEFORCE4_MX3,NV_ARCH_10},
 141   {DEVICE_NVIDIA_NV18_GEFORCE4_MX4,NV_ARCH_10},
 142   {DEVICE_NVIDIA_NV18_GEFORCE4_MX5,NV_ARCH_10},
 143   {DEVICE_NVIDIA_NV18M_GEFORCE4_448,NV_ARCH_10},
 144   {DEVICE_NVIDIA_NV18M_GEFORCE4_488,NV_ARCH_10},
 145   {DEVICE_NVIDIA_NV18GL_QUADRO_FX,NV_ARCH_10},
 146   {DEVICE_NVIDIA_NV18GL_QUADRO4_580,NV_ARCH_10},
 147   {DEVICE_NVIDIA_NV18GL_QUADRO4_NVS,NV_ARCH_10},
 148   {DEVICE_NVIDIA_NV18GL_QUADRO4_380,NV_ARCH_10},
 149   {DEVICE_NVIDIA_NV18M_GEFORCE4_4482,NV_ARCH_10},
 150   {DEVICE_NVIDIA_NVCRUSH11_GEFORCE2_MX,NV_ARCH_10},
 151   {DEVICE_NVIDIA_NV18_GEFORCE4_MX5,NV_ARCH_10},
 152   {DEVICE_NVIDIA_NV18_GEFORCE_PCX,NV_ARCH_10},
 153   /*NV20*/
 154   {DEVICE_NVIDIA_NV20_GEFORCE3,NV_ARCH_20},
 155   {DEVICE_NVIDIA_NV20_GEFORCE3_TI,NV_ARCH_20},
 156   {DEVICE_NVIDIA_NV20_GEFORCE3_TI2,NV_ARCH_20},
 157   {DEVICE_NVIDIA_NV20DCC_QUADRO_DCC,NV_ARCH_20},
 158   {DEVICE_NVIDIA_NV25_GEFORCE4_TI,NV_ARCH_20},
 159   {DEVICE_NVIDIA_NV25_GEFORCE4_TI2,NV_ARCH_20},
 160   {DEVICE_NVIDIA_NV25_GEFORCE4_TI3,NV_ARCH_20},
 161   {DEVICE_NVIDIA_NV25_GEFORCE4_TI4,NV_ARCH_20},
 162   {DEVICE_NVIDIA_NV25GL_QUADRO4_900,NV_ARCH_20},
 163   {DEVICE_NVIDIA_NV25GL_QUADRO4_750,NV_ARCH_20},
 164   {DEVICE_NVIDIA_NV25GL_QUADRO4_700,NV_ARCH_20},
 165   {DEVICE_NVIDIA_NV28_GEFORCE4_TI,NV_ARCH_20},
 166   {DEVICE_NVIDIA_NV28_GEFORCE4_TI2,NV_ARCH_20},
 167   {DEVICE_NVIDIA_NV28_GEFORCE4_TI3,NV_ARCH_20},
 168   {DEVICE_NVIDIA_NV28_GEFORCE4_TI4,NV_ARCH_20},
 169   {DEVICE_NVIDIA_NV28GL_QUADRO4_980,NV_ARCH_20},
 170   {DEVICE_NVIDIA_NV28GL_QUADRO4_780,NV_ARCH_20},
 171   {DEVICE_NVIDIA_NV28GLM_QUADRO4_700,NV_ARCH_20},
 172   /*NV30*/
 173   {DEVICE_NVIDIA_NV30_GEFORCE_FX,NV_ARCH_30},
 174   {DEVICE_NVIDIA_NV30_GEFORCE_FX2,NV_ARCH_30},
 175   {DEVICE_NVIDIA_NV30_GEFORCE_FX3,NV_ARCH_30},
 176   {DEVICE_NVIDIA_NV30GL_QUADRO_FX,NV_ARCH_30},
 177   {DEVICE_NVIDIA_NV30GL_QUADRO_FX2,NV_ARCH_30},
 178   {DEVICE_NVIDIA_NV31_GEFORCE_FX,NV_ARCH_30},
 179   {DEVICE_NVIDIA_NV31_GEFORCE_FX2,NV_ARCH_30},
 180   {DEVICE_NVIDIA_NV31,NV_ARCH_30},
 181   {DEVICE_NVIDIA_NV31_GEFORCE_FX3,NV_ARCH_30},
 182   {DEVICE_NVIDIA_NV31M,NV_ARCH_30},
 183   {DEVICE_NVIDIA_NV31M_PRO,NV_ARCH_30},
 184   {DEVICE_NVIDIA_NV31M_GEFORCE_FX,NV_ARCH_30},
 185   {DEVICE_NVIDIA_NV31M_GEFORCE_FX2,NV_ARCH_30},
 186   {DEVICE_NVIDIA_NVIDIA_QUADRO_FX,NV_ARCH_30},
 187   {DEVICE_NVIDIA_NV31GLM,NV_ARCH_30},
 188   {DEVICE_NVIDIA_NV31GLM_PRO,NV_ARCH_30},
 189   {DEVICE_NVIDIA_NV31GLM_PRO2,NV_ARCH_30},
 190   {DEVICE_NVIDIA_NV34_GEFORCE_FX,NV_ARCH_30},
 191   {DEVICE_NVIDIA_NV34_GEFORCE_FX2,NV_ARCH_30},
 192   {DEVICE_NVIDIA_NV34_GEFORCE_FX3,NV_ARCH_30},
 193   {DEVICE_NVIDIA_NV34_GEFORCE_FX4,NV_ARCH_30},
 194   {DEVICE_NVIDIA_NV34M_GEFORCE_FX,NV_ARCH_30},
 195   {DEVICE_NVIDIA_NV34M_GEFORCE_FX2,NV_ARCH_30},
 196   {DEVICE_NVIDIA_NV34_GEFORCE_FX5,NV_ARCH_30},
 197   {DEVICE_NVIDIA_NV34_GEFORCE_FX6,NV_ARCH_30},
 198   {DEVICE_NVIDIA_NV34M_GEFORCE_FX3,NV_ARCH_30},
 199   {DEVICE_NVIDIA_NV34M_GEFORCE_FX4,NV_ARCH_30},
 200   {DEVICE_NVIDIA_NV34GL_QUADRO_NVS,NV_ARCH_30},
 201   {DEVICE_NVIDIA_NV34GL_QUADRO_FX,NV_ARCH_30},
 202   {DEVICE_NVIDIA_NV34GLM_GEFORCE_FX,NV_ARCH_30},
 203   {DEVICE_NVIDIA_NV34_GEFORCE_FX7,NV_ARCH_30},
 204   {DEVICE_NVIDIA_NV34GL,NV_ARCH_30},
 205   {DEVICE_NVIDIA_NV35_GEFORCE_FX,NV_ARCH_30},
 206   {DEVICE_NVIDIA_NV35_GEFORCE_FX2,NV_ARCH_30},
 207   {DEVICE_NVIDIA_NV35_GEFORCE_FX3,NV_ARCH_30},
 208   {DEVICE_NVIDIA_NV38_GEFORCE_FX,NV_ARCH_30},
 209   {DEVICE_NVIDIA_NV35_GEFORCE_FX4,NV_ARCH_30},
 210   {DEVICE_NVIDIA_NV35GL_QUADRO_FX,NV_ARCH_30},
 211   {DEVICE_NVIDIA_NV35GL_QUADRO_FX2,NV_ARCH_30},
 212   {DEVICE_NVIDIA_NV35_GEFORCE_PCX,NV_ARCH_30},
 213   {DEVICE_NVIDIA_NV36_1_GEFORCE_FX,NV_ARCH_30},
 214   {DEVICE_NVIDIA_NV36_2_GEFORCE_FX,NV_ARCH_30},
 215   {DEVICE_NVIDIA_NV36_GEFORCE_FX,NV_ARCH_30},
 216   {DEVICE_NVIDIA_NV36_4_GEFORCE_FX,NV_ARCH_30},
 217   {DEVICE_NVIDIA_NV36_5,NV_ARCH_30},
 218   {DEVICE_NVIDIA_NV36_GEFORCE_FX2,NV_ARCH_30},
 219   {DEVICE_NVIDIA_NV36_GEFORCE_FX3,NV_ARCH_30},
 220   {DEVICE_NVIDIA_NV36_GEFORCE_PCX,NV_ARCH_30},
 221   {DEVICE_NVIDIA_NV36M_PRO,NV_ARCH_30},
 222   {DEVICE_NVIDIA_NV36MAP,NV_ARCH_30},
 223   {DEVICE_NVIDIA_NV36_QUADRO_FX,NV_ARCH_30},
 224   {DEVICE_NVIDIA_NV36GL_QUADRO_FX,NV_ARCH_30},
 225   {DEVICE_NVIDIA_NV36GL,NV_ARCH_30},
 226   {DEVICE_NVIDIA_NV36_GEFORCE_PCX,NV_ARCH_30},
 227   {DEVICE_NVIDIA_NV35_GEFORCE_PCX,NV_ARCH_30},
 228   {DEVICE_NVIDIA_NV37GL_QUADRO_FX,NV_ARCH_30},
 229   {DEVICE_NVIDIA_NV37GL_QUADRO_FX2,NV_ARCH_30},
 230   {DEVICE_NVIDIA_NV38GL_QUADRO_FX,NV_ARCH_30},
 231   /* NV40: GeForce 6x00 to 7x00 */
 232   {DEVICE_NVIDIA_NV40_GEFORCE_6800,NV_ARCH_40},
 233   {DEVICE_NVIDIA_NV40_GEFORCE_68002,NV_ARCH_40},
 234   {DEVICE_NVIDIA_NV40_2_GEFORCE_6800,NV_ARCH_40},
 235   {DEVICE_NVIDIA_NV40_3,NV_ARCH_40},
 236   {DEVICE_NVIDIA_NV40_GEFORCE_68003,NV_ARCH_40},
 237   {DEVICE_NVIDIA_NV40_GEFORCE_68004,NV_ARCH_40},
 238   {DEVICE_NVIDIA_NV40_GEFORCE_68005,NV_ARCH_40},
 239   {DEVICE_NVIDIA_NV40_GEFORCE_68006,NV_ARCH_40},
 240   {DEVICE_NVIDIA_NV40_GEFORCE_68007,NV_ARCH_40},
 241   {DEVICE_NVIDIA_NV40_GEFORCE_68008,NV_ARCH_40},
 242   {DEVICE_NVIDIA_NV40_GEFORCE_68009,NV_ARCH_40},
 243   {DEVICE_NVIDIA_NV40_GEFORCE_680010,NV_ARCH_40},
 244   {DEVICE_NVIDIA_NV40_GEFORCE_680011,NV_ARCH_40},
 245   {DEVICE_NVIDIA_NV40_GEFORCE_680012,NV_ARCH_40},
 246   {DEVICE_NVIDIA_NV40_GEFORCE_68008,NV_ARCH_40},
 247   {DEVICE_NVIDIA_NV40GL,NV_ARCH_40},
 248   {DEVICE_NVIDIA_NV40GL_QUADRO_FX,NV_ARCH_40},
 249   {DEVICE_NVIDIA_NV40GL_QUADRO_FX2,NV_ARCH_40},
 250   {DEVICE_NVIDIA_NV41_GEFORCE_6800,NV_ARCH_40},
 251   {DEVICE_NVIDIA_NV41_1_GEFORCE_6800,NV_ARCH_40},
 252   {DEVICE_NVIDIA_NV41_2_GEFORCE_6800,NV_ARCH_40},
 253   {DEVICE_NVIDIA_NV41_8_GEFORCE_GO,NV_ARCH_40},
 254   {DEVICE_NVIDIA_NV41_9_GEFORCE_GO,NV_ARCH_40},
 255   {DEVICE_NVIDIA_NV41_QUADRO_FX,NV_ARCH_40},
 256   {DEVICE_NVIDIA_NV41_QUADRO_FX2,NV_ARCH_40},
 257   {DEVICE_NVIDIA_NV41GL_QUADRO_FX,NV_ARCH_40},
 258   {DEVICE_NVIDIA_NV40_GEFORCE_6800_GEFORCE,NV_ARCH_40},
 259   {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE,NV_ARCH_40},
 260   {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE2,NV_ARCH_40},
 261   {DEVICE_NVIDIA_NV43_GEFORCE_6200,NV_ARCH_40},
 262   {DEVICE_NVIDIA_NV43_GEFORCE_62002,NV_ARCH_40},
 263   {DEVICE_NVIDIA_NV43_GEFORCE_6600,NV_ARCH_40},
 264   {DEVICE_NVIDIA_NV43_GEFORCE_66002,NV_ARCH_40},
 265   {DEVICE_NVIDIA_NV43_GEFORCE_66003,NV_ARCH_40},
 266   {DEVICE_NVIDIA_NV43_GEFORCE_66004,NV_ARCH_40},
 267   {DEVICE_NVIDIA_NV43_GEFORCE_66005,NV_ARCH_40},
 268   {DEVICE_NVIDIA_NV43_GEFORCE_GO,NV_ARCH_40},
 269   {DEVICE_NVIDIA_NV43_GEFORCE_GO2,NV_ARCH_40},
 270   {DEVICE_NVIDIA_NV43_GEFORCE_GO3,NV_ARCH_40},
 271   {DEVICE_NVIDIA_NV43_GEFORCE_GO4,NV_ARCH_40},
 272   {DEVICE_NVIDIA_NV43_GEFORCE_GO5,NV_ARCH_40},
 273   {DEVICE_NVIDIA_NV43_GEFORCE_GO6,NV_ARCH_40},
 274   {DEVICE_NVIDIA_NV43_GEFORCE_6610,NV_ARCH_40},
 275   {DEVICE_NVIDIA_NV43GL_QUADRO_FX,NV_ARCH_40},
 276   {DEVICE_NVIDIA_GEFORCE_6100_NFORCE,NV_ARCH_40},
 277   {DEVICE_NVIDIA_GEFORCE_6100_NFORCE2,NV_ARCH_40},
 278   {DEVICE_NVIDIA_GEFORCE_6100_NFORCE3,NV_ARCH_40},
 279   {DEVICE_NVIDIA_GEFORCE_6100_NFORCE4,NV_ARCH_40},
 280   {DEVICE_NVIDIA_C51G_GEFORCE_6100,NV_ARCH_40},
 281   {DEVICE_NVIDIA_C51PV_GEFORCE_6150,NV_ARCH_40},
 282   {DEVICE_NVIDIA_NV44_GEFORCE_6200,NV_ARCH_40},
 283   {DEVICE_NVIDIA_NV44_GEFORCE_62002,NV_ARCH_40},
 284   {DEVICE_NVIDIA_NV44_GEFORCE_62003,NV_ARCH_40},
 285   {DEVICE_NVIDIA_NV44_GEFORCE_GO,NV_ARCH_40},
 286   {DEVICE_NVIDIA_NV44_QUADRO_NVS,NV_ARCH_40},
 287   {DEVICE_NVIDIA_GEFORCE_GO_6200,NV_ARCH_40},
 288   {DEVICE_NVIDIA_NV44A_GEFORCE_6200,NV_ARCH_40},
 289   {DEVICE_NVIDIA_NV45GL_QUADRO_FX,NV_ARCH_40},
 290   {DEVICE_NVIDIA_GEFORCE_GO_7200,NV_ARCH_40},
 291   {DEVICE_NVIDIA_QUADRO_NVS_110M,NV_ARCH_40},
 292   {DEVICE_NVIDIA_GEFORCE_GO_7400,NV_ARCH_40},
 293   {DEVICE_NVIDIA_QUADRO_NVS_110M2,NV_ARCH_40},
 294   {DEVICE_NVIDIA_QUADRO_FX_350,NV_ARCH_40},
 295   {DEVICE_NVIDIA_G70_GEFORCE_7300,NV_ARCH_40},
 296   {DEVICE_NVIDIA_GEFORCE_7300_GS,NV_ARCH_40},
 297   {DEVICE_NVIDIA_G70_GEFORCE_7600,NV_ARCH_40},
 298   {DEVICE_NVIDIA_G70_GEFORCE_76002,NV_ARCH_40},
 299   {DEVICE_NVIDIA_GEFORCE_7600_GS,NV_ARCH_40},
 300   {DEVICE_NVIDIA_G70_GEFORCE_GO,NV_ARCH_40},
 301   {DEVICE_NVIDIA_QUADRO_FX_560,NV_ARCH_40},
 302   {DEVICE_NVIDIA_G70_GEFORCE_7800,NV_ARCH_40},
 303   {DEVICE_NVIDIA_G70_GEFORCE_78002,NV_ARCH_40},
 304   {DEVICE_NVIDIA_G70_GEFORCE_78003,NV_ARCH_40},
 305   {DEVICE_NVIDIA_G70_GEFORCE_78004,NV_ARCH_40},
 306   {DEVICE_NVIDIA_G70_GEFORCE_78005,NV_ARCH_40},
 307   {DEVICE_NVIDIA_GEFORCE_GO_7800,NV_ARCH_40},
 308   {DEVICE_NVIDIA_GEFORCE_7900_GTX,NV_ARCH_40},
 309   {DEVICE_NVIDIA_GEFORCE_7900_GT,NV_ARCH_40},
 310   {DEVICE_NVIDIA_GEFORCE_7900_GS,NV_ARCH_40},
 311   {DEVICE_NVIDIA_GEFORCE_GO_7900,NV_ARCH_40},
 312   {DEVICE_NVIDIA_GEFORCE_GO_79002,NV_ARCH_40},
 313   {DEVICE_NVIDIA_GE_FORCE_GO,NV_ARCH_40},
 314   {DEVICE_NVIDIA_G70GL_QUADRO_FX4500,NV_ARCH_40},
 315   {DEVICE_NVIDIA_G71_QUADRO_FX,NV_ARCH_40},
 316   {DEVICE_NVIDIA_G71_QUADRO_FX2,NV_ARCH_40}
 317 };
 318
 319
 320 static int find_chip(unsigned chip_id){
 321   unsigned i;
 322   for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++)
 323   {
 324     if(chip_id == nvidia_card_ids[i].chip_id)return i;
 325   }
 326   return -1;
 327 }
 328
 329 static int nv_probe(int verbose, int force){
 330     pciinfo_t lst[MAX_PCI_DEVICES];
 331     unsigned i,num_pci;
 332     int err;
 333
 334     if (force)
 335             printf("[nvidia_vid]: warning: forcing not supported yet!\n");
 336     err = pci_scan(lst,&num_pci);
 337     if(err){
 338         printf("[nvidia_vid] Error occurred during pci scan: %s\n",strerror(err));
 339         return err;
 340     }
 341     else {
 342         err = ENXIO;
 343         for(i=0; i < num_pci; i++){
 344             if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){
 345                 int idx;
 346                 const char *dname;
 347                 idx = find_chip(lst[i].device);
 348                 if(idx == -1)
 349                     continue;
 350                 dname = pci_device_name(lst[i].vendor, lst[i].device);
 351                 dname = dname ? dname : "Unknown chip";
 352                 printf("[nvidia_vid] Found chip: %s\n", dname);
 353                 if ((lst[i].command & PCI_COMMAND_IO) == 0){
 354                         printf("[nvidia_vid] Device is disabled, ignoring\n");
 355                         continue;
 356                 }
 357                 nvidia_cap.device_id = lst[i].device;
 358                 err = 0;
 359                 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
 360                 break;
 361             }
 362         }
 363     }
 364     if(err && verbose) printf("[nvidia_vid] Can't find chip\n");
 365     return err;
 366 }
 367
 368
 369
 370
 371 /*
 372  * PCI-Memory IO access macros.
 373  */
 374
 375 #define MEM_BARRIER() __asm__ volatile ("" : : : "memory")
 376
 377 #undef  VID_WR08
 378 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); })
 379 #undef  VID_RD08
 380 #define VID_RD08(p,i)     ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; })
 381
 382 #undef  VID_WR32
 383 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=val; })
 384 #undef  VID_RD32
 385 #define VID_RD32(p,i)     ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; })
 386
 387 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val))
 388 #define VID_OR32(p,i,val)  VID_WR32(p,i,VID_RD32(p,i)|(val))
 389 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val))
 390
 391
 392
 393
 394
 395
 396 struct rivatv_chip {
 397         volatile uint32_t *PMC;    /* general control                   */
 398         volatile uint32_t *PME;    /* multimedia port                   */
 399         volatile uint32_t *PFB;    /* framebuffer control               */
 400         volatile uint32_t *PVIDEO; /* overlay control                   */
 401         volatile uint8_t *PCIO;    /* SVGA (CRTC, ATTR) registers       */
 402         volatile uint8_t *PVIO;    /* SVGA (MISC, GRAPH, SEQ) registers */
 403         volatile uint32_t *PRAMIN; /* instance memory                   */
 404         volatile uint32_t *PRAMHT; /* hash table                        */
 405         volatile uint32_t *PRAMFC; /* fifo context table                */
 406         volatile uint32_t *PRAMRO; /* fifo runout table                 */
 407         volatile uint32_t *PFIFO;  /* fifo control region               */
 408         volatile uint32_t *FIFO;   /* fifo channels (USER)              */
 409         volatile uint32_t *PGRAPH; /* graphics engine                   */
 410
 411         unsigned long fbsize;              /* framebuffer size             */
 412         int arch;                  /* compatible NV_ARCH_XX define */
 413         int realarch;              /* real architecture            */
 414         void (* lock) (struct rivatv_chip *, int);
 415 };
 416 typedef struct rivatv_chip rivatv_chip;
 417
 418
 419 struct rivatv_info {
 420     unsigned int use_colorkey;
 421     unsigned int colorkey; /* saved xv colorkey*/
 422     unsigned int vidixcolorkey; /*currently used colorkey*/
 423     unsigned int depth;
 424     unsigned int format;
 425     unsigned int pitch;
 426     unsigned int width,height;
 427     unsigned int d_width,d_height;  /*scaled width && height*/
 428     unsigned int wx,wy;                /*window x && y*/
 429     unsigned int screen_x;            /*screen width*/
 430     unsigned int screen_y;            /*screen height*/
 431         unsigned long buffer_size;               /* size of the image buffer           */
 432         struct rivatv_chip chip;         /* NV architecture structure                  */
 433         void* video_base;                /* virtual address of control region          */
 434         void* control_base;              /* virtual address of fb region               */
 435         void* picture_base;              /* direct pointer to video picture            */
 436         unsigned long picture_offset;    /* offset of video picture in frame buffer    */
 437 //      struct rivatv_dma dma;           /* DMA structure                              */
 438     unsigned int cur_frame;
 439         unsigned int num_frames;             /* number of buffers                          */
 440         int bps;                        /* bytes per line */
 441 };
 442 typedef struct rivatv_info rivatv_info;
 443
 444 uint8_t nvReadVGA (struct rivatv_chip *chip, int index) {
 445         VID_WR08 (chip->PCIO, 0x3D4, index);
 446         return VID_RD08 (chip->PCIO, 0x3D5);
 447 }
 448
 449 void nvWriteVGA (struct rivatv_chip *chip, int index, int data) {
 450         VID_WR08 (chip->PCIO, 0x3D4, index);
 451         VID_WR08 (chip->PCIO, 0x3D5, data);
 452 }
 453
 454 //framebuffer size funcs
 455 static unsigned long rivatv_fbsize_nv03 (struct rivatv_chip *chip){
 456         if (VID_RD32 (chip->PFB, 0) & 0x00000020) {
 457                 if (((VID_RD32 (chip->PMC, 0) & 0xF0) == 0x20)
 458                     && ((VID_RD32 (chip->PMC, 0) & 0x0F) >= 0x02)) {
 459                         /* SDRAM 128 ZX. */
 460                         return (1 << (VID_RD32 (chip->PFB, 0) & 0x03)) * 1024 * 1024;
 461                 }
 462                 else {
 463                         return 1024 * 1024 * 8;
 464                 }
 465         }
 466         else {
 467                 /* SGRAM 128. */
 468                 switch (VID_RD32(chip->PFB, 0) & 0x00000003) {
 469                 case 0:
 470                         return 1024 * 1024 * 8;
 471                         break;
 472                 case 2:
 473                         return 1024 * 1024 * 4;
 474                         break;
 475                 default:
 476                         return 1024 * 1024 * 2;
 477                         break;
 478                 }
 479         }
 480 }
 481 static unsigned long rivatv_fbsize_nv04 (struct rivatv_chip *chip){
 482         if (VID_RD32 (chip->PFB, 0) & 0x00000100) {
 483                 return ((VID_RD32 (chip->PFB, 0) >> 12) & 0x0F) * 1024 * 1024 * 2
 484                         + 1024 * 1024 * 2;
 485         } else {
 486                 switch (VID_RD32 (chip->PFB, 0) & 0x00000003) {
 487                 case 0:
 488                         return 1024 * 1024 * 32;
 489                         break;
 490                 case 1:
 491                         return 1024 * 1024 * 4;
 492                         break;
 493                 case 2:
 494                         return 1024 * 1024 * 8;
 495                         break;
 496                 case 3:
 497                 default:
 498                         return 1024 * 1024 * 16;
 499                         break;
 500                 }
 501         }
 502 }
 503
 504 static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){
 505         return VID_RD32 (chip->PFB, 0x20C) & 0xFFF00000;
 506 }
 507
 508 //lock funcs
 509 static void rivatv_lock_nv03 (struct rivatv_chip *chip, int LockUnlock){
 510         VID_WR08 (chip->PVIO, 0x3C4, 0x06);
 511         VID_WR08 (chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57);
 512 }
 513
 514 static void rivatv_lock_nv04 (struct rivatv_chip *chip, int LockUnlock){
 515         rivatv_lock_nv03 (chip, LockUnlock);
 516         nvWriteVGA (chip, 0x1F, LockUnlock ? 0x99 : 0x57);
 517 }
 518
 519
 520
 521
 522 /* Enable PFB (Framebuffer), PVIDEO (Overlay unit) and PME (Mediaport) if neccessary. */
 523 static void  rivatv_enable_PMEDIA (struct rivatv_info *info){
 524         uint32_t reg;
 525
 526         /* switch off interrupts once for a while */
 527 //      VID_WR32 (info->chip.PME, 0x200140, 0x00);
 528 //      VID_WR32 (info->chip.PMC, 0x000140, 0x00);
 529
 530         reg = VID_RD32 (info->chip.PMC, 0x000200);
 531
 532         /* NV3 (0x10100010): NV03_PMC_ENABLE_PMEDIA, NV03_PMC_ENABLE_PFB, NV03_PMC_ENABLE_PVIDEO */
 533
 534         if ((reg & 0x10100010) != 0x10100010) {
 535                 printf("PVIDEO and PFB disabled, enabling...\n");
 536                 VID_OR32 (info->chip.PMC, 0x000200, 0x10100010);
 537         }
 538
 539         /* save the current colorkey */
 540     switch (info->chip.arch ) {
 541           case NV_ARCH_10:
 542           case NV_ARCH_20:
 543       case NV_ARCH_30:
 544       case NV_ARCH_40:
 545         /* NV_PVIDEO_COLOR_KEY */
 546             info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00);
 547         break;
 548       case NV_ARCH_03:
 549           case NV_ARCH_04:
 550         /* NV_PVIDEO_KEY */
 551             info->colorkey = VID_RD32 (info->chip.PVIDEO, 0x240);
 552         break;
 553     }
 554
 555
 556         /* re-enable interrupts again */
 557 //      VID_WR32 (info->chip.PMC, 0x000140, 0x01);
 558 //      VID_WR32 (info->chip.PME, 0x200140, 0x01);
 559 }
 560
 561 /* Stop overlay video. */
 562 static void rivatv_overlay_stop (struct rivatv_info *info) {
 563         switch (info->chip.arch ) {
 564         case NV_ARCH_10:
 565         case NV_ARCH_20:
 566         case NV_ARCH_30:
 567         case NV_ARCH_40:
 568                 /* NV_PVIDEO_COLOR_KEY */
 569                 /* Xv-Extension-Hack: Restore previously saved value. */
 570                 VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey);
 571                 /* NV_PVIDEO_STOP */
 572                 VID_OR32 (info->chip.PVIDEO, 0x704, 0x11);
 573                 /* NV_PVIDEO_BUFFER */
 574                 VID_AND32 (info->chip.PVIDEO, 0x700, ~0x11);
 575                 /* NV_PVIDEO_INTR_EN_BUFFER */
 576 //              VID_AND32 (info->chip.PVIDEO, 0x140, ~0x11);
 577                 break;
 578         case NV_ARCH_03:
 579         case NV_ARCH_04:
 580                 /* NV_PVIDEO_KEY */
 581                 VID_WR32 (info->chip.PVIDEO, 0x240, info->colorkey);
 582                 /* NV_PVIDEO_OVERLAY_VIDEO_OFF */
 583                 VID_AND32 (info->chip.PVIDEO, 0x244, ~0x01);
 584                 /* NV_PVIDEO_INTR_EN_0_NOTIFY */
 585 //              VID_AND32 (info->chip.PVIDEO, 0x140, ~0x01);
 586                 /* NV_PVIDEO_OE_STATE */
 587                 VID_WR32 (info->chip.PVIDEO, 0x224, 0);
 588                 /* NV_PVIDEO_SU_STATE */
 589                 VID_WR32 (info->chip.PVIDEO, 0x228, 0);
 590                 /* NV_PVIDEO_RM_STATE */
 591                 VID_WR32 (info->chip.PVIDEO, 0x22C, 0);
 592                 break;
 593         }
 594 }
 595
 596 /* Get pan offset of the physical screen. */
 597 static uint32_t rivatv_overlay_pan (struct rivatv_info *info){
 598         uint32_t pan;
 599         info->chip.lock (&info->chip, 0);
 600         pan  =  nvReadVGA (&info->chip, 0x0D);
 601         pan |=  nvReadVGA (&info->chip, 0x0C) << 8;
 602         pan |= (nvReadVGA (&info->chip, 0x19) & 0x1F) << 16;
 603         pan |= (nvReadVGA (&info->chip, 0x2D) & 0x60) << 16;
 604         return pan << 2;
 605 }
 606
 607 /* Compute and set colorkey depending on the colour depth. */
 608 static void rivatv_overlay_colorkey (rivatv_info* info, unsigned int chromakey){
 609         uint32_t r, g, b, key = 0;
 610
 611         r = (chromakey & 0x00FF0000) >> 16;
 612         g = (chromakey & 0x0000FF00) >> 8;
 613         b = chromakey & 0x000000FF;
 614         switch (info->depth) {
 615         case 15:
 616                 key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3));
 617
 618 #if !defined(__MINGW32__) && !defined(__CYGWIN__)
 619         key = key | 0x00008000;
 620 #endif
 621                 break;
 622         case 16: // XXX unchecked
 623                 key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3));
 624 #if !defined(__MINGW32__) && !defined(__CYGWIN__)
 625         key = key | 0x00008000;
 626 #endif
 627                 break;
 628         case 24: // XXX unchecked, maybe swap order of masking - FIXME Can the card be in 24 bit mode anyway?
 629                 key = (chromakey & 0x00FFFFFF) | 0x00800000;
 630                 break;
 631         case 32:
 632                 key = chromakey;
 633 #if !defined(__MINGW32__) && !defined(__CYGWIN__)
 634         key = key | 0x80000000;
 635 #endif
 636                 break;
 637         }
 638         //printf("[nvidia_vid] depth=%d %08X \n", info->depth, chromakey);
 639     switch (info->chip.arch) {
 640           case NV_ARCH_10:
 641           case NV_ARCH_20:
 642       case NV_ARCH_30:
 643       case NV_ARCH_40:
 644         VID_WR32 (info->chip.PVIDEO, 0xB00, key);
 645         break;
 646           case NV_ARCH_03:
 647           case NV_ARCH_04:
 648         VID_WR32 (info->chip.PVIDEO, 0x240, key);
 649         break;
 650     }
 651 }
 652
 653 static void nv_getscreenproperties(struct rivatv_info *info){
 654   uint32_t bpp=0,x;
 655   info->chip.lock(&info->chip, 0);
 656   /*get screen depth*/
 657   bpp = nvReadVGA (&info->chip, 0x28) & 0x3;
 658   if((bpp == 2) && (VID_RD32(info->chip.PVIDEO,0x600) & 0x00001000) == 0x0)info->depth=15;
 659   else info->depth = 0x04 << bpp;
 660   /*get screen width*/
 661   info->screen_x = nvReadVGA (&info->chip, 0x1);
 662   /* NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 */
 663   info->screen_x |= (nvReadVGA (&info->chip, 0x2D) & 0x02) << 7;
 664   info->screen_x = (info->screen_x + 1) << 3;
 665   /*get screen height*/
 666   /* get first 8 bits in VT_DISPLAY_END*/
 667   info->screen_y = nvReadVGA (&info->chip, 0x12);
 668   /* get 9th bit in CRTC_OVERFLOW*/
 669   info->screen_y |= (nvReadVGA (&info->chip, 0x07) & 0x02) << 7;
 670   /* and the 10th in CRTC_OVERFLOW*/
 671   info->screen_y |= (nvReadVGA (&info->chip, 0x07) & 0x40) << 3;
 672   ++info->screen_y;
 673
 674   if(info->chip.arch >= NV_ARCH_10){
 675     /* NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 */
 676     info->screen_y |= (nvReadVGA (&info->chip, 0x25) & 0x02) << 9;
 677     /* NV_PCRTC_???_VERT_DISPLAY_END_11 */
 678     info->screen_y |= (nvReadVGA (&info->chip, 0x41) & 0x04) << 9;
 679   }
 680
 681   /* NV_PCRTC_OFFSET */
 682   x  =  nvReadVGA (&info->chip, 0x13);
 683   /* NV_PCRTC_REPAINT0_OFFSET_10_8 */
 684   x |= (nvReadVGA (&info->chip, 0x19) & 0xE0) << 3;
 685   /* NV_PCRTC_EXTRA_OFFSET_11 */
 686   x |= (nvReadVGA (&info->chip, 0x25) & 0x20) << 6; x <<= 3;
 687   info->bps = x * bpp;
 688 }
 689
 690
 691
 692
 693 /* Start overlay video. */
 694 static void rivatv_overlay_start (struct rivatv_info *info,int bufno){
 695     uint32_t base, size, offset, xscale, yscale, pan;
 696     uint32_t value;
 697         int x=info->wx, y=info->wy;
 698         int lwidth=info->d_width, lheight=info->d_height;
 699
 700     size = info->buffer_size;
 701         base = info->picture_offset;
 702         offset = bufno*size;
 703     /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/
 704     nv_getscreenproperties(info);
 705
 706     if(info->depth){
 707         /* get pan offset of the physical screen */
 708         pan = rivatv_overlay_pan (info);
 709         /* adjust window position depending on the pan offset */
 710         if (info->bps != 0)
 711         {
 712           x = info->wx - (pan % info->bps) * 8 / info->depth;
 713           y = info->wy - (pan / info->bps);
 714         }
 715     } else {
 716             // we can't adjust the window position correctly in textmode
 717             // setting y to 8 seems to work ok, though
 718             if(info->chip.arch < NV_ARCH_10 && y < 8) y = 8;
 719     }
 720
 721             /* adjust negative output window variables */
 722             if (x < 0) {
 723                   lwidth = info->d_width + x;
 724                   offset += (-x * info->width / info->d_width) << 1;
 725 //              offset += (-window->x * port->vld_width / window->width) << 1;
 726                   x = 0;
 727             }
 728             if (y < 0) {
 729                   lheight = info->d_height + y;
 730                   offset += (-y * info->height / info->d_height * info->width) << 1;
 731 //              offset += (-window->y * port->vld_height / window->height * port->org_width) << 1;
 732               y = 0;
 733             }
 734
 735         switch (info->chip.arch) {
 736         case NV_ARCH_10:
 737         case NV_ARCH_20:
 738         case NV_ARCH_30:
 739         case NV_ARCH_40:
 740
 741                 /* NV_PVIDEO_BASE */
 742                 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base + offset);
 743                 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base);
 744                 /* NV_PVIDEO_LIMIT */
 745                 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + offset + size - 1);
 746                 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1);
 747
 748                 /* extra code for NV20 && NV30 architectures */
 749                 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30 || info->chip.arch == NV_ARCH_40) {
 750                         VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base + offset);
 751                         //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base);
 752                         VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + offset + size - 1);
 753                         //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1);
 754                 }
 755
 756                 /* NV_PVIDEO_LUMINANCE */
 757                 VID_WR32 (info->chip.PVIDEO, 0x910 + 0, eq.lum);
 758                 //VID_WR32 (info->chip.PVIDEO, 0x910 + 4, 0x00001000);
 759                 /* NV_PVIDEO_CHROMINANCE */
 760                 VID_WR32 (info->chip.PVIDEO, 0x918 + 0, eq.chrom);
 761                 //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000);
 762
 763                 /* NV_PVIDEO_OFFSET */
 764                 VID_WR32 (info->chip.PVIDEO, 0x920 + 0, 0x0);
 765                 //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch);
 766                 /* NV_PVIDEO_SIZE_IN */
 767                 VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width);
 768                 //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width);
 769                 /* NV_PVIDEO_POINT_IN */
 770                 VID_WR32 (info->chip.PVIDEO, 0x930 + 0, 0x00000000);
 771                 //VID_WR32 (info->chip.PVIDEO, 0x930 + 4, 0x00000000);
 772                 /* NV_PVIDEO_DS_DX_RATIO */
 773                 VID_WR32 (info->chip.PVIDEO, 0x938 + 0, (info->width << 20) / info->d_width);
 774                 //VID_WR32 (info->chip.PVIDEO, 0x938 + 4, (port->org_width << 20) / window->width);
 775                 /* NV_PVIDEO_DT_DY_RATIO */
 776                 VID_WR32 (info->chip.PVIDEO, 0x940 + 0, ((info->height) << 20) / info->d_height);
 777                 //VID_WR32 (info->chip.PVIDEO, 0x940 + 4, ((port->org_height/2) << 20) / window->height);
 778
 779                 /* NV_PVIDEO_POINT_OUT */
 780                 VID_WR32 (info->chip.PVIDEO, 0x948 + 0, ((y + 0) << 16) | x);
 781                 //VID_WR32 (info->chip.PVIDEO, 0x948 + 4, ((y + 0) << 16) | x);
 782                 /* NV_PVIDEO_SIZE_OUT */
 783                 VID_WR32 (info->chip.PVIDEO, 0x950 + 0, (lheight << 16) | lwidth);
 784                 //VID_WR32 (info->chip.PVIDEO, 0x950 + 4, (height << 16) | width);
 785
 786                 /* NV_PVIDEO_FORMAT */
 787         value = info->pitch;
 788             if(info->use_colorkey)value |= 1 << 20;
 789         if(info->format == IMGFMT_YUY2)value |= 1 << 16;
 790         VID_WR32 (info->chip.PVIDEO, 0x958 + 0, value);
 791             //VID_WR32 (info->chip.PVIDEO, 0x958 + 4, (pitch << 1) | 0x00100000);
 792
 793                 /* NV_PVIDEO_INTR_EN_BUFFER */
 794 //              VID_OR32 (info->chip.PVIDEO, 0x140, 0x01/*0x11*/);
 795                 /* NV_PVIDEO_STOP */
 796                 VID_WR32 (info->chip.PVIDEO, 0x704,0x0);
 797                 /* NV_PVIDEO_BUFFER */
 798                 VID_WR32 (info->chip.PVIDEO, 0x700, 0x01/*0x11*/);
 799                 break;
 800
 801         case NV_ARCH_03:
 802         case NV_ARCH_04:
 803
 804
 805                 /* NV_PVIDEO_OE_STATE */
 806                 VID_WR32 (info->chip.PVIDEO, 0x224, 0);
 807                 /* NV_PVIDEO_SU_STATE */
 808                 VID_WR32 (info->chip.PVIDEO, 0x228, 0);
 809                 /* NV_PVIDEO_RM_STATE */
 810                 VID_WR32 (info->chip.PVIDEO, 0x22C, 0);
 811
 812                 /* NV_PVIDEO_BUFF0_START_ADDRESS */
 813                 VID_WR32 (info->chip.PVIDEO, 0x20C + 0, base + offset + 0);
 814                 VID_WR32 (info->chip.PVIDEO, 0x20C + 4, base + offset + 0);
 815                 /* NV_PVIDEO_BUFF0_PITCH_LENGTH */
 816                 VID_WR32 (info->chip.PVIDEO, 0x214 + 0, info->pitch);
 817                 VID_WR32 (info->chip.PVIDEO, 0x214 + 4, info->pitch);
 818
 819                 /* NV_PVIDEO_WINDOW_START */
 820                 VID_WR32 (info->chip.PVIDEO, 0x230, (y << 16) | x);
 821                 /* NV_PVIDEO_WINDOW_SIZE */
 822                 VID_WR32 (info->chip.PVIDEO, 0x234, (lheight << 16) | lwidth);
 823                 /* NV_PVIDEO_STEP_SIZE */
 824                 yscale = ((info->height - 1) << 11) / (info->d_height - 1);
 825                 xscale = ((info->width - 1) << 11) / (info->d_width - 1);
 826                 VID_WR32 (info->chip.PVIDEO, 0x200, (yscale << 16) | xscale);
 827
 828                 /* NV_PVIDEO_RED_CSC_OFFSET */
 829                 VID_WR32 (info->chip.PVIDEO, 0x280, eq.red_off);
 830                 /* NV_PVIDEO_GREEN_CSC_OFFSET */
 831                 VID_WR32 (info->chip.PVIDEO, 0x284, eq.green_off);
 832                 /* NV_PVIDEO_BLUE_CSC_OFFSET */
 833                 VID_WR32 (info->chip.PVIDEO, 0x288, eq.blue_off);
 834                 /* NV_PVIDEO_CSC_ADJUST */
 835                 VID_WR32 (info->chip.PVIDEO, 0x28C, 0x00000); /* No colour correction! */
 836
 837                 /* NV_PVIDEO_CONTROL_Y (BLUR_ON, LINE_HALF) */
 838                 VID_WR32 (info->chip.PVIDEO, 0x204, 0x001);
 839                 /* NV_PVIDEO_CONTROL_X (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */
 840                 VID_WR32 (info->chip.PVIDEO, 0x208, 0x111);     /*directx overlay 0x110 */
 841
 842                 /* NV_PVIDEO_FIFO_BURST_LENGTH */
 843                 VID_WR32 (info->chip.PVIDEO, 0x23C, 0x03);
 844                 /* NV_PVIDEO_FIFO_THRES_SIZE */
 845                 VID_WR32 (info->chip.PVIDEO, 0x238, 0x38);   /*windows uses 0x40*/
 846
 847                 /* NV_PVIDEO_BUFF0_OFFSET */
 848                 VID_WR32 (info->chip.PVIDEO, 0x21C + 0, 0);
 849                 VID_WR32 (info->chip.PVIDEO, 0x21C + 4, 0);
 850
 851                 /* NV_PVIDEO_INTR_EN_0_NOTIFY_ENABLED */
 852 //              VID_OR32 (info->chip.PVIDEO, 0x140, 0x01);
 853
 854                 /* NV_PVIDEO_OVERLAY (KEY_ON, VIDEO_ON, FORMAT_CCIR) */
 855         value = 0x1; /*video on*/
 856         if(info->format==IMGFMT_YUY2)value |= 0x100;
 857         if(info->use_colorkey)value |=0x10;
 858         VID_WR32 (info->chip.PVIDEO, 0x244, value);
 859
 860                 /* NV_PVIDEO_SU_STATE */
 861                 VID_XOR32 (info->chip.PVIDEO, 0x228, 1 << 16);
 862                 break;
 863         }
 864     /*set colorkey*/
 865     rivatv_overlay_colorkey(info,info->vidixcolorkey);
 866
 867 }
 868
 869
 870
 871
 872
 873
 874
 875 static rivatv_info* info;
 876
 877
 878
 879
 880 static int nv_init(void){
 881         int mtrr;
 882   info = calloc(1,sizeof(rivatv_info));
 883   info->control_base = map_phys_mem(pci_info.base0, 0x00C00000 + 0x00008000);
 884   info->chip.arch =  nvidia_card_ids[find_chip(pci_info.device)].arch;
 885   printf("[nvidia_vid] arch %x register base %p\n",info->chip.arch,info->control_base);
 886   info->chip.PFIFO  = (uint32_t *) (info->control_base + 0x00002000);
 887   info->chip.FIFO   = (uint32_t *) (info->control_base + 0x00800000);
 888   info->chip.PMC    = (uint32_t *) (info->control_base + 0x00000000);
 889   info->chip.PFB    = (uint32_t *) (info->control_base + 0x00100000);
 890   info->chip.PME    = (uint32_t *) (info->control_base + 0x00000000);
 891   info->chip.PCIO   = (uint8_t *)  (info->control_base + 0x00601000);
 892   info->chip.PVIO   = (uint8_t *)  (info->control_base + 0x000C0000);
 893   info->chip.PGRAPH = (uint32_t *) (info->control_base + 0x00400000);
 894   /* setup chip specific functions */
 895   switch (info->chip.arch) {
 896         case NV_ARCH_03:
 897                 info->chip.lock = rivatv_lock_nv03;
 898                 info->chip.fbsize = rivatv_fbsize_nv03 (&info->chip);
 899                 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000);
 900                 break;
 901         case NV_ARCH_04:
 902                 info->chip.lock = rivatv_lock_nv04;
 903                 info->chip.fbsize = rivatv_fbsize_nv04 (&info->chip);
 904                 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000);
 905                 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000);
 906                 break;
 907         case NV_ARCH_10:
 908         case NV_ARCH_20:
 909         case NV_ARCH_30:
 910         case NV_ARCH_40:
 911                 info->chip.lock = rivatv_lock_nv04;
 912                 info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip);
 913                 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000);
 914                 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000);
 915                 break;
 916   }
 917   switch (info->chip.arch) {
 918         case NV_ARCH_03:
 919     {
 920         /* This maps framebuffer @6MB, thus 2MB are left for video. */
 921             info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize);
 922         /* This may trash your screen for resolutions greater than 1024x768, sorry. */
 923         info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1);
 924         info->picture_base = info->video_base + info->picture_offset;
 925         info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000);
 926         break;
 927         }
 928     case NV_ARCH_04:
 929         case NV_ARCH_10:
 930         case NV_ARCH_20:
 931     case NV_ARCH_30:
 932     case NV_ARCH_40:
 933         {
 934                 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize);
 935                 info->picture_offset = info->chip.fbsize - NV04_BES_SIZE;
 936                 if(info->chip.fbsize > 16*1024*1024)
 937                         info->picture_offset -= NV04_BES_SIZE;
 938 //              info->picture_base = (unsigned long)map_phys_mem(pci_info.base1+info->picture_offset,NV04_BES_SIZE);
 939                 info->picture_base = info->video_base + info->picture_offset;
 940                 break;
 941         }
 942   }
 943
 944   printf("[nvidia_vid] detected memory size %u MB\n",(uint32_t)(info->chip.fbsize /1024/1024));
 945
 946   if ((mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB))!= 0)
 947           printf("[nvidia_vid] unable to setup MTRR: %s\n", strerror(mtrr));
 948   else
 949           printf("[nvidia_vid] MTRR set up\n");
 950
 951   nv_getscreenproperties(info);
 952   if(!info->depth)printf("[nvidia_vid] text mode: %ux%u\n",info->screen_x,info->screen_y);
 953   else printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x,info->screen_y, info->depth);
 954
 955
 956   rivatv_enable_PMEDIA(info);
 957   info->cur_frame = 0;
 958   info->use_colorkey = 0;
 959
 960   eq.lum = 0x00001000;
 961   eq.chrom = 0x00001000;
 962   memset(&eq.vals, 0, sizeof(vidix_video_eq_t));
 963   eq.vals.cap = VEQ_CAP_BRIGHTNESS;
 964   if (info->chip.arch > NV_ARCH_04)
 965     eq.vals.cap |= VEQ_CAP_CONTRAST | VEQ_CAP_SATURATION | VEQ_CAP_HUE;
 966   eq.red_off = 0x69;
 967   eq.green_off = 0x3e;
 968   eq.blue_off = 0x89;
 969   return 0;
 970 }
 971
 972 static void nv_destroy(void){
 973   unmap_phys_mem(info->control_base ,0x00C00000 + 0x00008000);
 974   unmap_phys_mem(info->video_base, info->chip.fbsize);
 975   free(info);
 976 }
 977
 978 static int nv_get_caps(vidix_capability_t *to){
 979     memcpy(to, &nvidia_cap, sizeof(vidix_capability_t));
 980     return 0;
 981 }
 982
 983 inline static int is_supported_fourcc(uint32_t fourcc)
 984 {
 985         if      (fourcc == IMGFMT_UYVY || fourcc == IMGFMT_YUY2)
 986                 return 1;
 987         else
 988                 return 0;
 989 }
 990
 991 static int nv_query_fourcc(vidix_fourcc_t *to){
 992     if(is_supported_fourcc(to->fourcc)){
 993         to->depth = VID_DEPTH_ALL;
 994         to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
 995         return 0;
 996     }
 997     else  to->depth = to->flags = 0;
 998     return ENOSYS;
 999 }
1000
1001 static int nv_config_playback(vidix_playback_t *vinfo){
1002     uint32_t i;
1003 //    printf("called %s\n", __FUNCTION__);
1004     if (! is_supported_fourcc(vinfo->fourcc))
1005             return ENOSYS;
1006
1007     info->width = vinfo->src.w;
1008     info->height = vinfo->src.h;
1009
1010     info->d_width = vinfo->dest.w;
1011     info->d_height = vinfo->dest.h;
1012     info->wx = vinfo->dest.x;
1013     info->wy = vinfo->dest.y;
1014     info->format = vinfo->fourcc;
1015
1016     printf("[nvidia_vid] setting up a %dx%d-%dx%d video window (src %dx%d), format 0x%X\n",
1017                     info->d_width, info->d_height, info->wx, info->wy, info->width, info->height, vinfo->fourcc);
1018
1019
1020     vinfo->dga_addr=info->picture_base;
1021
1022     switch (vinfo->fourcc)
1023     {
1024             case IMGFMT_YUY2:
1025             case IMGFMT_UYVY:
1026
1027                     vinfo->dest.pitch.y = 64;
1028                     vinfo->dest.pitch.u = 0;
1029                     vinfo->dest.pitch.v = 0;
1030
1031                     vinfo->offset.y = 0;
1032                     vinfo->offset.v = 0;
1033                     vinfo->offset.u = 0;
1034                     info->pitch = ((info->width << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1);
1035                     vinfo->frame_size = info->pitch * info->height;
1036                     break;
1037     }
1038     info->buffer_size = vinfo->frame_size;
1039     info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size;
1040     if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES;
1041 //    vinfo->num_frames = 1;
1042 //    printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames);
1043     for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i;
1044     return 0;
1045 }
1046
1047 static int nv_playback_on(void){
1048     rivatv_overlay_start(info,info->cur_frame);
1049     return 0;
1050 }
1051
1052 static int nv_playback_off(void){
1053     rivatv_overlay_stop(info);
1054     return 0;
1055 }
1056
1057 static int nv_set_gkeys( const vidix_grkey_t * grkey){
1058   if (grkey->ckey.op == CKEY_FALSE)
1059   {
1060     info->use_colorkey = 0;
1061     printf("[nvidia_vid] colorkeying disabled\n");
1062   }
1063   else {
1064   info->use_colorkey = 1;
1065   info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue);
1066   printf("[nvidia_vid] set colorkey 0x%x\n",info->vidixcolorkey);
1067   }
1068   if(info->d_width && info->d_height)rivatv_overlay_start(info,0);
1069   return 0;
1070 }
1071
1072 static int nv_frame_sel(unsigned int frame){
1073 //  printf("selecting buffer %d\n", frame);
1074   rivatv_overlay_start(info, frame);
1075   if (info->num_frames >= 1)
1076           info->cur_frame = frame/*(frame+1)%info->num_frames*/;
1077   return 0;
1078 }
1079
1080 static int nv_set_eq(const vidix_video_eq_t *eq_parm) {
1081   double angle;
1082   int16_t chrom_cos, chrom_sin;
1083   if (eq_parm->cap & VEQ_CAP_BRIGHTNESS)
1084     eq.vals.brightness = eq_parm->brightness;
1085   if (eq_parm->cap & VEQ_CAP_CONTRAST)
1086     eq.vals.contrast = eq_parm->contrast;
1087   if (eq_parm->cap & VEQ_CAP_SATURATION)
1088     eq.vals.saturation = eq_parm->saturation;
1089   if (eq_parm->cap & VEQ_CAP_HUE)
1090     eq.vals.hue = eq_parm->hue;
1091   eq.lum = (((eq.vals.brightness * 512 + 500) / 1000) << 16) |
1092            ((((eq.vals.contrast + 1000) * 8191 + 1000) / 2000) & 0xffff);
1093   angle = (double)eq.vals.hue / 1000.0 * 3.1415927;
1094   chrom_cos = ((eq.vals.saturation + 1000) * 8191 * cos(angle) + 1000) / 2000;
1095   chrom_sin = ((eq.vals.saturation + 1000) * 8191 * sin(angle) + 1000) / 2000;
1096   eq.chrom = chrom_sin << 16 | chrom_cos;
1097   eq.red_off = 0x69 - eq.vals.brightness * 62 / 1000;
1098   eq.green_off = 0x3e + eq.vals.brightness * 62 / 1000;
1099   eq.blue_off = 0x89 - eq.vals.brightness * 62 / 1000;
1100   return 0;
1101 }
1102
1103 static int nv_get_eq(vidix_video_eq_t *eq_parm) {
1104   memcpy(eq_parm, &eq.vals, sizeof(vidix_video_eq_t));
1105   return 0;
1106 }
1107
1108 VDXDriver nvidia_drv = {
1109   "nvidia",
1110   NULL,
1111   .probe = nv_probe,
1112   .get_caps = nv_get_caps,
1113   .query_fourcc = nv_query_fourcc,
1114   .init = nv_init,
1115   .destroy = nv_destroy,
1116   .config_playback = nv_config_playback,
1117   .playback_on = nv_playback_on,
1118   .playback_off = nv_playback_off,
1119   .frame_sel = nv_frame_sel,
1120   .get_eq = nv_get_eq,
1121   .set_eq = nv_set_eq,
1122   .set_gkey = nv_set_gkeys,
1123 };
1124
1125
1126 #if 0
1127 //gcc -o nvidia_vid nvidia_vid.c -I ../ -lm ../vidix/libvidix.a
1128
1129 int main(int argc,char* argv[]){
1130   if(nv_probe(0,0)){
1131         printf("no supported chip found\n");
1132         return 1;
1133   }
1134   if(nv_init()){
1135         printf("could not init\n");
1136         return 1;
1137   }
1138   if(info->chip.arch >= NV_ARCH_10){
1139     printf("NV_PVIDEO_BASE (0x900) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x900));
1140     printf("NV_PVIDEO_LIMIT (0x908) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x908));
1141     printf("NV_PVIDEO_OFFSET (0x920) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x920));
1142     printf("NV_PVIDEO_FORMAT (0x958) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x958));
1143     printf("NV_PVIDEO_STOP (0x704) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x704));
1144     printf("NV_PVIDEO_BUFFER (0x700) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x700));
1145   }
1146
1147   nv_destroy();
1148   return 0;
1149 }
1150
1151 #endif
1152