16 #include "osdep/timer.h"
19 #include <sys/param.h>
20 #include <sys/sysctl.h>
21 #include <machine/cpu.h>
25 #include <sys/types.h>
26 #include <sys/sysctl.h>
37 //#define X86_FXSR_MAGIC
38 /* Thanks to the FreeBSD project for some of this cpuid code, and
39 * help understanding how to use it. Thanks to the Mesa
40 * team for SSE support detection and more cpu detect code.
43 /* I believe this code works. However, it has only been used on a PII and PIII */
45 static void check_os_katmai_support( void );
48 // return TRUE if cpuid supported
49 static int has_cpuid()
53 // code from libavcodec:
54 __asm__
__volatile__ (
55 /* See if CPUID instruction is supported ... */
56 /* ... Get copies of EFLAGS into eax and ecx */
61 /* ... Toggle the ID bit in one copy and store */
62 /* to the EFLAGS reg */
63 "xorl $0x200000, %0\n\t"
67 /* ... Get the (hopefully modified) EFLAGS */
80 do_cpuid(unsigned int ax
, unsigned int *p
)
85 : "=a" (p
[0]), "=b" (p
[1]), "=c" (p
[2]), "=d" (p
[3])
89 // code from libavcodec:
91 ("movl %%ebx, %%esi\n\t"
94 : "=a" (p
[0]), "=S" (p
[1]),
95 "=c" (p
[2]), "=d" (p
[3])
101 void GetCpuCaps( CpuCaps
*caps
)
103 unsigned int regs
[4];
104 unsigned int regs2
[4];
106 memset(caps
, 0, sizeof(*caps
));
108 caps
->cl_size
=32; /* default */
110 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"CPUID not supported!??? (maybe an old 486?)\n");
113 do_cpuid(0x00000000, regs
); // get _max_ cpuid level and vendor name
114 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n",
115 (char*) (regs
+1),(char*) (regs
+3),(char*) (regs
+2), regs
[0]);
116 if (regs
[0]>=0x00000001)
121 do_cpuid(0x00000001, regs2
);
123 caps
->cpuType
=(regs2
[0] >> 8)&0xf;
124 if(caps
->cpuType
==0xf){
125 // use extended family (P4, IA64)
126 caps
->cpuType
=8+((regs2
[0]>>20)&255);
128 caps
->cpuStepping
=regs2
[0] & 0xf;
130 // general feature flags:
131 caps
->hasTSC
= (regs2
[3] & (1 << 8 )) >> 8; // 0x0000010
132 caps
->hasMMX
= (regs2
[3] & (1 << 23 )) >> 23; // 0x0800000
133 caps
->hasSSE
= (regs2
[3] & (1 << 25 )) >> 25; // 0x2000000
134 caps
->hasSSE2
= (regs2
[3] & (1 << 26 )) >> 26; // 0x4000000
135 caps
->hasMMX2
= caps
->hasSSE
; // SSE cpus supports mmxext too
136 cl_size
= ((regs2
[1] >> 8) & 0xFF)*8;
137 if(cl_size
) caps
->cl_size
= cl_size
;
139 tmpstr
=GetCpuFriendlyName(regs
, regs2
);
140 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: %s ",tmpstr
);
142 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"(Family: %d, Stepping: %d)\n",
143 caps
->cpuType
, caps
->cpuStepping
);
146 do_cpuid(0x80000000, regs
);
147 if (regs
[0]>=0x80000001) {
148 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"extended cpuid-level: %d\n",regs
[0]&0x7FFFFFFF);
149 do_cpuid(0x80000001, regs2
);
150 caps
->hasMMX
|= (regs2
[3] & (1 << 23 )) >> 23; // 0x0800000
151 caps
->hasMMX2
|= (regs2
[3] & (1 << 22 )) >> 22; // 0x400000
152 caps
->has3DNow
= (regs2
[3] & (1 << 31 )) >> 31; //0x80000000
153 caps
->has3DNowExt
= (regs2
[3] & (1 << 30 )) >> 30;
155 if(regs
[0]>=0x80000006)
157 do_cpuid(0x80000006, regs2
);
158 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"extended cache-info: %d\n",regs2
[2]&0x7FFFFFFF);
159 caps
->cl_size
= regs2
[2] & 0xFF;
161 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"Detected cache-line size is %u bytes\n",caps
->cl_size
);
163 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
169 gCpuCaps
.has3DNowExt
);
172 /* FIXME: Does SSE2 need more OS support, too? */
173 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__CYGWIN__)
175 check_os_katmai_support();
183 // caps->hasMMX2 = 0;
187 if(caps
->hasMMX
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"MMX supported but disabled\n");
191 if(caps
->hasMMX2
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"MMX2 supported but disabled\n");
195 if(caps
->hasSSE
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"SSE supported but disabled\n");
199 if(caps
->hasSSE2
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"SSE2 supported but disabled\n");
203 if(caps
->has3DNow
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"3DNow supported but disabled\n");
207 if(caps
->has3DNowExt
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"3DNowExt supported but disabled\n");
213 static inline unsigned long long int rdtsc( void )
215 unsigned long long int retval
;
216 __asm
__volatile ("rdtsc":"=A"(retval
)::"memory");
220 /* Returns CPU clock in khz */
221 static unsigned int GetCpuSpeed(void)
223 unsigned long long int tscstart
, tscstop
;
224 unsigned int start
, stop
;
232 return((tscstop
-tscstart
)/((stop
-start
)/1000.0));
236 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
237 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */
238 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */
239 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */
240 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */
241 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */
243 char *GetCpuFriendlyName(unsigned int regs
[], unsigned int regs2
[]){
244 #include "cputable.h" /* get cpuname and cpuvendors */
245 char vendor
[17], cpuspeed
[16];
249 if (NULL
==(retname
=(char*)malloc(256))) {
250 mp_msg(MSGT_CPUDETECT
,MSGL_FATAL
,"Error: GetCpuFriendlyName() not enough memory\n");
254 /* Measure CPU speed */
255 if (gCpuCaps
.hasTSC
&& (i
= GetCpuSpeed()) > 0) {
257 i
+= 50; /* for rounding */
258 snprintf(cpuspeed
,15, " %d.%d MHz", i
/1000, (i
/100)%10);
260 //i += 500; /* for rounding */
261 snprintf(cpuspeed
,15, " %d MHz", i
/1000);
263 } else { /* No TSC Support */
268 sprintf(vendor
,"%.4s%.4s%.4s",(char*)(regs
+1),(char*)(regs
+3),(char*)(regs
+2));
270 for(i
=0; i
<MAX_VENDORS
; i
++){
271 if(!strcmp(cpuvendors
[i
].string
,vendor
)){
272 if(cpuname
[i
][CPUID_FAMILY
][CPUID_MODEL
]){
273 snprintf(retname
,255,"%s %s%s",cpuvendors
[i
].name
,cpuname
[i
][CPUID_FAMILY
][CPUID_MODEL
],cpuspeed
);
275 snprintf(retname
,255,"unknown %s %d. Generation CPU%s",cpuvendors
[i
].name
,CPUID_FAMILY
,cpuspeed
);
276 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"unknown %s CPU:\n",cpuvendors
[i
].name
);
277 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Vendor: %s\n",cpuvendors
[i
].string
);
278 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Type: %d\n",CPUID_TYPE
);
279 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Family: %d (ext: %d)\n",CPUID_FAMILY
,CPUID_EXTFAMILY
);
280 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Model: %d (ext: %d)\n",CPUID_MODEL
,CPUID_EXTMODEL
);
281 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Stepping: %d\n",CPUID_STEPPING
);
282 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Please send the above info along with the exact CPU name"
283 "to the MPlayer-Developers, so we can add it to the list!\n");
288 //printf("Detected CPU: %s\n", retname);
292 #undef CPUID_EXTFAMILY
293 #undef CPUID_EXTMODEL
297 #undef CPUID_STEPPING
300 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
301 static void sigill_handler_sse( int signal
, struct sigcontext sc
)
303 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "SIGILL, " );
305 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
306 * instructions are 3 bytes long. We must increment the instruction
307 * pointer manually to avoid repeated execution of the offending
310 * If the SIGILL is caused by a divide-by-zero when unmasked
311 * exceptions aren't supported, the SIMD FPU status and control
312 * word will be restored at the end of the test, so we don't need
313 * to worry about doing it here. Besides, we may not be able to...
320 static void sigfpe_handler_sse( int signal
, struct sigcontext sc
)
322 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "SIGFPE, " );
324 if ( sc
.fpstate
->magic
!= 0xffff ) {
325 /* Our signal context has the extended FPU state, so reset the
326 * divide-by-zero exception mask and clear the divide-by-zero
329 sc
.fpstate
->mxcsr
|= 0x00000200;
330 sc
.fpstate
->mxcsr
&= 0xfffffffb;
332 /* If we ever get here, we're completely hosed.
334 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "\n\n" );
335 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "SSE enabling test failed badly!" );
338 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
341 LONG CALLBACK
win32_sig_handler_sse(EXCEPTION_POINTERS
* ep
)
343 if(ep
->ExceptionRecord
->ExceptionCode
==EXCEPTION_ILLEGAL_INSTRUCTION
){
344 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "SIGILL, " );
345 ep
->ContextRecord
->Eip
+=3;
347 return EXCEPTION_CONTINUE_EXECUTION
;
349 return EXCEPTION_CONTINUE_SEARCH
;
353 /* If we're running on a processor that can do SSE, let's see if we
354 * are allowed to or not. This will catch 2.4.0 or later kernels that
355 * haven't been configured for a Pentium III but are running on one,
356 * and RedHat patched 2.2 kernels that have broken exception handling
357 * support for user space apps that do SSE.
359 static void check_os_katmai_support( void )
361 #if defined(__FreeBSD__)
363 size_t len
=sizeof(has_sse
);
365 ret
= sysctlbyname("hw.instruction_sse", &has_sse
, &len
, NULL
, 0);
369 #elif defined(__NetBSD__)
370 #if __NetBSD_Version__ >= 105250000
371 int has_sse
, has_sse2
, ret
, mib
[2];
374 mib
[0] = CTL_MACHDEP
;
376 varlen
= sizeof(has_sse
);
378 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE... " );
379 ret
= sysctl(mib
, 2, &has_sse
, &varlen
, NULL
, 0);
380 if (ret
< 0 || !has_sse
) {
382 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "no!\n" );
385 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "yes!\n" );
389 varlen
= sizeof(has_sse2
);
390 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE2... " );
391 ret
= sysctl(mib
, 2, &has_sse2
, &varlen
, NULL
, 0);
392 if (ret
< 0 || !has_sse2
) {
394 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "no!\n" );
397 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "yes!\n" );
401 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
, "No OS support for SSE, disabling to be safe.\n" );
404 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil
;
405 if ( gCpuCaps
.hasSSE
) {
406 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE... " );
407 exc_fil
= SetUnhandledExceptionFilter(win32_sig_handler_sse
);
408 __asm
__volatile ("xorps %xmm0, %xmm0");
409 SetUnhandledExceptionFilter(exc_fil
);
410 if ( gCpuCaps
.hasSSE
) mp_msg(MSGT_CPUDETECT
,MSGL_V
, "yes.\n" );
411 else mp_msg(MSGT_CPUDETECT
,MSGL_V
, "no!\n" );
413 #elif defined(__linux__)
414 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
415 struct sigaction saved_sigill
;
416 struct sigaction saved_sigfpe
;
418 /* Save the original signal handlers.
420 sigaction( SIGILL
, NULL
, &saved_sigill
);
421 sigaction( SIGFPE
, NULL
, &saved_sigfpe
);
423 signal( SIGILL
, (void (*)(int))sigill_handler_sse
);
424 signal( SIGFPE
, (void (*)(int))sigfpe_handler_sse
);
426 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it
427 * supports the extended FPU save and restore required for SSE. If
428 * we execute an SSE instruction on a PIII and get a SIGILL, the OS
429 * doesn't support Streaming SIMD Exceptions, even if the processor
432 if ( gCpuCaps
.hasSSE
) {
433 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE... " );
435 // __asm __volatile ("xorps %%xmm0, %%xmm0");
436 __asm
__volatile ("xorps %xmm0, %xmm0");
438 if ( gCpuCaps
.hasSSE
) {
439 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "yes.\n" );
441 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "no!\n" );
445 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if
446 * it supports unmasked SIMD FPU exceptions. If we unmask the
447 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
448 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE
449 * as expected, we're okay but we need to clean up after it.
451 * Are we being too stringent in our requirement that the OS support
452 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by
453 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98
454 * doesn't even support them. We at least know the user-space SSE
455 * support is good in kernels that do support unmasked exceptions,
456 * and therefore to be safe I'm going to leave this test in here.
458 if ( gCpuCaps
.hasSSE
) {
459 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE unmasked exceptions... " );
461 // test_os_katmai_exception_support();
463 if ( gCpuCaps
.hasSSE
) {
464 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "yes.\n" );
466 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "no!\n" );
470 /* Restore the original signal handlers.
472 sigaction( SIGILL
, &saved_sigill
, NULL
);
473 sigaction( SIGFPE
, &saved_sigfpe
, NULL
);
475 /* If we've gotten to here and the XMM CPUID bit is still set, we're
476 * safe to go ahead and hook out the SSE code throughout Mesa.
478 if ( gCpuCaps
.hasSSE
) {
479 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Tests of OS support for SSE passed.\n" );
481 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Tests of OS support for SSE failed!\n" );
484 /* We can't use POSIX signal handling to test the availability of
485 * SSE, so we disable it by default.
487 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
, "Cannot test OS support for SSE, disabling to be safe.\n" );
489 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
491 /* Do nothing on other platforms for now.
493 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
, "Cannot test OS support for SSE, leaving disabled.\n" );
495 #endif /* __linux__ */
500 #include <sys/sysctl.h>
505 static sigjmp_buf jmpbuf
;
506 static volatile sig_atomic_t canjump
= 0;
508 static void sigill_handler (int sig
)
511 signal (sig
, SIG_DFL
);
516 siglongjmp (jmpbuf
, 1);
520 void GetCpuCaps( CpuCaps
*caps
)
531 caps
->hasAltiVec
= 0;
535 rip-off from ffmpeg altivec detection code.
536 this code also appears on Apple's AltiVec pages.
539 int sels
[2] = {CTL_HW
, HW_VECTORUNIT
};
541 size_t len
= sizeof(has_vu
);
544 err
= sysctl(sels
, 2, &has_vu
, &len
, NULL
, 0);
548 caps
->hasAltiVec
= 1;
550 #else /* SYS_DARWIN */
551 /* no Darwin, do it the brute-force way */
552 /* this is borrowed from the libmpeg2 library */
554 signal (SIGILL
, sigill_handler
);
555 if (sigsetjmp (jmpbuf
, 1)) {
556 signal (SIGILL
, SIG_DFL
);
560 asm volatile ("mtspr 256, %0\n\t"
561 "vand %%v0, %%v0, %%v0"
565 signal (SIGILL
, SIG_DFL
);
566 caps
->hasAltiVec
= 1;
569 #endif /* SYS_DARWIN */
570 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"AltiVec %sfound\n", (caps
->hasAltiVec
? "" : "not "));
571 #endif /* HAVE_ALTIVEC */
573 #endif /* !ARCH_X86 */