vo_gl: Make it possible to select GL_NEAREST scaling
[mplayer/glamo.git] / cpudetect.c
blob1edf4a08be7b94525d49de9254864989219384bf
1 /*
2 * This file is part of MPlayer.
4 * MPlayer is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * MPlayer is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with MPlayer; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 #include "config.h"
20 #include "cpudetect.h"
21 #include "mp_msg.h"
23 CpuCaps gCpuCaps;
25 #include <stdlib.h>
27 #if ARCH_X86
29 #include <stdio.h>
30 #include <string.h>
32 #if defined (__NetBSD__) || defined(__OpenBSD__)
33 #include <sys/param.h>
34 #include <sys/sysctl.h>
35 #include <machine/cpu.h>
36 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
37 #include <sys/types.h>
38 #include <sys/sysctl.h>
39 #elif defined(__linux__)
40 #include <signal.h>
41 #elif defined(__MINGW32__) || defined(__CYGWIN__)
42 #include <windows.h>
43 #elif defined(__OS2__)
44 #define INCL_DOS
45 #include <os2.h>
46 #elif defined(__AMIGAOS4__)
47 #include <proto/exec.h>
48 #endif
50 /* Thanks to the FreeBSD project for some of this cpuid code, and
51 * help understanding how to use it. Thanks to the Mesa
52 * team for SSE support detection and more cpu detect code.
55 /* I believe this code works. However, it has only been used on a PII and PIII */
57 static void check_os_katmai_support( void );
59 // return TRUE if cpuid supported
60 static int has_cpuid(void)
62 // code from libavcodec:
63 #if ARCH_X86_64
64 return 1;
65 #else
66 long a, c;
67 __asm__ volatile (
68 /* See if CPUID instruction is supported ... */
69 /* ... Get copies of EFLAGS into eax and ecx */
70 "pushfl\n\t"
71 "pop %0\n\t"
72 "mov %0, %1\n\t"
74 /* ... Toggle the ID bit in one copy and store */
75 /* to the EFLAGS reg */
76 "xor $0x200000, %0\n\t"
77 "push %0\n\t"
78 "popfl\n\t"
80 /* ... Get the (hopefully modified) EFLAGS */
81 "pushfl\n\t"
82 "pop %0\n\t"
83 : "=a" (a), "=c" (c)
85 : "cc"
88 return a != c;
89 #endif
92 static void
93 do_cpuid(unsigned int ax, unsigned int *p)
95 #if 0
96 __asm__ volatile(
97 "cpuid;"
98 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
99 : "0" (ax)
101 #else
102 // code from libavcodec:
103 __asm__ volatile
104 ("mov %%"REG_b", %%"REG_S"\n\t"
105 "cpuid\n\t"
106 "xchg %%"REG_b", %%"REG_S
107 : "=a" (p[0]), "=S" (p[1]),
108 "=c" (p[2]), "=d" (p[3])
109 : "0" (ax));
110 #endif
113 void GetCpuCaps( CpuCaps *caps)
115 unsigned int regs[4];
116 unsigned int regs2[4];
118 memset(caps, 0, sizeof(*caps));
119 caps->isX86=1;
120 caps->cl_size=32; /* default */
121 if (!has_cpuid()) {
122 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
123 return;
125 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
126 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n",
127 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
128 if (regs[0]>=0x00000001)
130 char *tmpstr, *ptmpstr;
131 unsigned cl_size;
133 do_cpuid(0x00000001, regs2);
135 caps->cpuType=(regs2[0] >> 8)&0xf;
136 caps->cpuModel=(regs2[0] >> 4)&0xf;
138 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
139 // System Instructions, Table 3-2: Effective family computation, page 120.
140 if(caps->cpuType==0xf){
141 // use extended family (P4, IA64, K8)
142 caps->cpuType=0xf+((regs2[0]>>20)&255);
144 if(caps->cpuType==0xf || caps->cpuType==6)
145 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
147 caps->cpuStepping=regs2[0] & 0xf;
149 // general feature flags:
150 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010
151 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
152 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
153 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
154 caps->hasSSE3 = (regs2[2] & 1); // 0x0000001
155 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >> 9; // 0x0000200
156 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
157 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
158 if(cl_size) caps->cl_size = cl_size;
160 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
161 while(*ptmpstr == ' ') // strip leading spaces
162 ptmpstr++;
163 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr);
164 free(tmpstr);
165 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n",
166 caps->cpuType, caps->cpuModel, caps->cpuStepping);
169 do_cpuid(0x80000000, regs);
170 if (regs[0]>=0x80000001) {
171 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
172 do_cpuid(0x80000001, regs2);
173 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
174 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
175 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
176 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
177 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >> 6; // 0x0000040
179 if(regs[0]>=0x80000006)
181 do_cpuid(0x80000006, regs2);
182 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
183 caps->cl_size = regs2[2] & 0xFF;
185 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
186 #if 0
187 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
188 gCpuCaps.hasMMX,
189 gCpuCaps.hasMMX2,
190 gCpuCaps.hasSSE,
191 gCpuCaps.hasSSE2,
192 gCpuCaps.has3DNow,
193 gCpuCaps.has3DNowExt);
194 #endif
196 /* FIXME: Does SSE2 need more OS support, too? */
197 if (caps->hasSSE)
198 check_os_katmai_support();
199 if (!caps->hasSSE)
200 caps->hasSSE2 = 0;
201 // caps->has3DNow=1;
202 // caps->hasMMX2 = 0;
203 // caps->hasMMX = 0;
205 #if !CONFIG_RUNTIME_CPUDETECT
206 #if !HAVE_MMX
207 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
208 caps->hasMMX=0;
209 #endif
210 #if !HAVE_MMX2
211 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
212 caps->hasMMX2=0;
213 #endif
214 #if !HAVE_SSE
215 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
216 caps->hasSSE=0;
217 #endif
218 #if !HAVE_SSE2
219 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
220 caps->hasSSE2=0;
221 #endif
222 #if !HAVE_AMD3DNOW
223 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
224 caps->has3DNow=0;
225 #endif
226 #if !HAVE_AMD3DNOWEXT
227 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
228 caps->has3DNowExt=0;
229 #endif
230 #endif // CONFIG_RUNTIME_CPUDETECT
233 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
234 char vendor[13];
235 char *retname;
236 int i;
238 if (NULL==(retname=malloc(256))) {
239 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
240 exit(1);
242 retname[0] = '\0';
244 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
246 do_cpuid(0x80000000,regs);
247 if (regs[0] >= 0x80000004)
249 // CPU has built-in namestring
250 for (i = 0x80000002; i <= 0x80000004; i++)
252 do_cpuid(i, regs);
253 strncat(retname, (char*)regs, 16);
256 return retname;
259 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64
260 static void sigill_handler_sse( int signal, struct sigcontext sc )
262 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
264 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
265 * instructions are 3 bytes long. We must increment the instruction
266 * pointer manually to avoid repeated execution of the offending
267 * instruction.
269 * If the SIGILL is caused by a divide-by-zero when unmasked
270 * exceptions aren't supported, the SIMD FPU status and control
271 * word will be restored at the end of the test, so we don't need
272 * to worry about doing it here. Besides, we may not be able to...
274 sc.eip += 3;
276 gCpuCaps.hasSSE=0;
278 #endif /* __linux__ && _POSIX_SOURCE */
280 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64
281 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
283 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
284 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
285 ep->ContextRecord->Eip +=3;
286 gCpuCaps.hasSSE=0;
287 return EXCEPTION_CONTINUE_EXECUTION;
289 return EXCEPTION_CONTINUE_SEARCH;
291 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
293 #ifdef __OS2__
294 ULONG _System os2_sig_handler_sse(PEXCEPTIONREPORTRECORD p1,
295 PEXCEPTIONREGISTRATIONRECORD p2,
296 PCONTEXTRECORD p3,
297 PVOID p4)
299 if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
300 mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
302 p3->ctx_RegEip += 3;
303 gCpuCaps.hasSSE = 0;
305 return XCPT_CONTINUE_EXECUTION;
307 return XCPT_CONTINUE_SEARCH;
309 #endif
311 /* If we're running on a processor that can do SSE, let's see if we
312 * are allowed to or not. This will catch 2.4.0 or later kernels that
313 * haven't been configured for a Pentium III but are running on one,
314 * and RedHat patched 2.2 kernels that have broken exception handling
315 * support for user space apps that do SSE.
318 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
319 #define SSE_SYSCTL_NAME "hw.instruction_sse"
320 #elif defined(__APPLE__)
321 #define SSE_SYSCTL_NAME "hw.optional.sse"
322 #endif
324 static void check_os_katmai_support( void )
326 #if ARCH_X86_64
327 gCpuCaps.hasSSE=1;
328 gCpuCaps.hasSSE2=1;
329 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
330 int has_sse=0, ret;
331 size_t len=sizeof(has_sse);
333 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
334 if (ret || !has_sse)
335 gCpuCaps.hasSSE=0;
337 #elif defined(__NetBSD__) || defined (__OpenBSD__)
338 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
339 int has_sse, has_sse2, ret, mib[2];
340 size_t varlen;
342 mib[0] = CTL_MACHDEP;
343 mib[1] = CPU_SSE;
344 varlen = sizeof(has_sse);
346 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
347 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
348 gCpuCaps.hasSSE = ret >= 0 && has_sse;
349 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
351 mib[1] = CPU_SSE2;
352 varlen = sizeof(has_sse2);
353 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
354 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
355 gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
356 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
357 #else
358 gCpuCaps.hasSSE = 0;
359 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
360 #endif
361 #elif defined(__MINGW32__) || defined(__CYGWIN__)
362 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
363 if ( gCpuCaps.hasSSE ) {
364 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
365 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
366 __asm__ volatile ("xorps %xmm0, %xmm0");
367 SetUnhandledExceptionFilter(exc_fil);
368 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
370 #elif defined(__OS2__)
371 EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
372 if ( gCpuCaps.hasSSE ) {
373 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
374 DosSetExceptionHandler( &RegRec );
375 __asm__ volatile ("xorps %xmm0, %xmm0");
376 DosUnsetExceptionHandler( &RegRec );
377 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
379 #elif defined(__linux__)
380 #if defined(_POSIX_SOURCE)
381 struct sigaction saved_sigill;
383 /* Save the original signal handlers.
385 sigaction( SIGILL, NULL, &saved_sigill );
387 signal( SIGILL, (void (*)(int))sigill_handler_sse );
389 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it
390 * supports the extended FPU save and restore required for SSE. If
391 * we execute an SSE instruction on a PIII and get a SIGILL, the OS
392 * doesn't support Streaming SIMD Exceptions, even if the processor
393 * does.
395 if ( gCpuCaps.hasSSE ) {
396 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
398 // __asm__ volatile ("xorps %%xmm0, %%xmm0");
399 __asm__ volatile ("xorps %xmm0, %xmm0");
401 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
404 /* Restore the original signal handlers.
406 sigaction( SIGILL, &saved_sigill, NULL );
408 /* If we've gotten to here and the XMM CPUID bit is still set, we're
409 * safe to go ahead and hook out the SSE code throughout Mesa.
411 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
412 #else
413 /* We can't use POSIX signal handling to test the availability of
414 * SSE, so we disable it by default.
416 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
417 gCpuCaps.hasSSE=0;
418 #endif /* _POSIX_SOURCE */
419 #else
420 /* Do nothing on other platforms for now.
422 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
423 gCpuCaps.hasSSE=0;
424 #endif /* __linux__ */
426 #else /* ARCH_X86 */
428 #ifdef __APPLE__
429 #include <sys/sysctl.h>
430 #elif defined(__AMIGAOS4__)
431 /* nothing */
432 #else
433 #include <signal.h>
434 #include <setjmp.h>
436 static sigjmp_buf jmpbuf;
437 static volatile sig_atomic_t canjump = 0;
439 static void sigill_handler (int sig)
441 if (!canjump) {
442 signal (sig, SIG_DFL);
443 raise (sig);
446 canjump = 0;
447 siglongjmp (jmpbuf, 1);
449 #endif /* __APPLE__ */
451 void GetCpuCaps( CpuCaps *caps)
453 caps->cpuType=0;
454 caps->cpuModel=0;
455 caps->cpuStepping=0;
456 caps->hasMMX=0;
457 caps->hasMMX2=0;
458 caps->has3DNow=0;
459 caps->has3DNowExt=0;
460 caps->hasSSE=0;
461 caps->hasSSE2=0;
462 caps->hasSSE3=0;
463 caps->hasSSSE3=0;
464 caps->hasSSE4a=0;
465 caps->isX86=0;
466 caps->hasAltiVec = 0;
467 #if HAVE_ALTIVEC
468 #ifdef __APPLE__
470 rip-off from ffmpeg altivec detection code.
471 this code also appears on Apple's AltiVec pages.
474 int sels[2] = {CTL_HW, HW_VECTORUNIT};
475 int has_vu = 0;
476 size_t len = sizeof(has_vu);
477 int err;
479 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
481 if (err == 0)
482 if (has_vu != 0)
483 caps->hasAltiVec = 1;
485 #elif defined(__AMIGAOS4__)
486 ULONG result = 0;
488 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
489 if (result == VECTORTYPE_ALTIVEC)
490 caps->hasAltiVec = 1;
491 #else
492 /* no Darwin, do it the brute-force way */
493 /* this is borrowed from the libmpeg2 library */
495 signal (SIGILL, sigill_handler);
496 if (sigsetjmp (jmpbuf, 1)) {
497 signal (SIGILL, SIG_DFL);
498 } else {
499 canjump = 1;
501 __asm__ volatile ("mtspr 256, %0\n\t"
502 "vand %%v0, %%v0, %%v0"
504 : "r" (-1));
506 signal (SIGILL, SIG_DFL);
507 caps->hasAltiVec = 1;
510 #endif /* __APPLE__ */
511 mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
512 #endif /* HAVE_ALTIVEC */
514 if (ARCH_IA64)
515 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n");
517 if (ARCH_SPARC)
518 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n");
520 if (ARCH_ARM)
521 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n");
523 if (ARCH_PPC)
524 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n");
526 if (ARCH_ALPHA)
527 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n");
529 if (ARCH_MIPS)
530 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: MIPS\n");
532 if (ARCH_PA_RISC)
533 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n");
535 if (ARCH_S390)
536 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n");
538 if (ARCH_S390X)
539 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n");
541 if (ARCH_VAX)
542 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" );
544 if (ARCH_XTENSA)
545 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" );
547 #endif /* !ARCH_X86 */