cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #ifdef HAVE_MALLOC_H
   8 #include <malloc.h>
   9 #endif
  10 #include <stdlib.h>
  11
  12 #ifdef ARCH_X86
  13
  14 #include <stdio.h>
  15 #include <string.h>
  16
  17 #if defined (__NetBSD__) || defined(__OpenBSD__)
  18 #include <sys/param.h>
  19 #include <sys/sysctl.h>
  20 #include <machine/cpu.h>
  21 #endif
  22
  23 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
  24 #include <sys/types.h>
  25 #include <sys/sysctl.h>
  26 #endif
  27
  28 #ifdef __linux__
  29 #include <signal.h>
  30 #endif
  31
  32 #if defined(__MINGW32__) || defined(__CYGWIN__)
  33 #include <windows.h>
  34 #endif
  35
  36 #ifdef __OS2__
  37 #define INCL_DOS
  38 #include <os2.h>
  39 #endif
  40
  41 #ifdef __AMIGAOS4__
  42 #include <proto/exec.h>
  43 #endif
  44
  45 /* Thanks to the FreeBSD project for some of this cpuid code, and
  46  * help understanding how to use it.  Thanks to the Mesa
  47  * team for SSE support detection and more cpu detect code.
  48  */
  49
  50 /* I believe this code works.  However, it has only been used on a PII and PIII */
  51
  52 static void check_os_katmai_support( void );
  53
  54 // return TRUE if cpuid supported
  55 static int has_cpuid(void)
  56 {
  57         long a, c;
  58
  59 // code from libavcodec:
  60     __asm__ volatile (
  61                           /* See if CPUID instruction is supported ... */
  62                           /* ... Get copies of EFLAGS into eax and ecx */
  63                           "pushf\n\t"
  64                           "pop %0\n\t"
  65                           "mov %0, %1\n\t"
  66
  67                           /* ... Toggle the ID bit in one copy and store */
  68                           /*     to the EFLAGS reg */
  69                           "xor $0x200000, %0\n\t"
  70                           "push %0\n\t"
  71                           "popf\n\t"
  72
  73                           /* ... Get the (hopefully modified) EFLAGS */
  74                           "pushf\n\t"
  75                           "pop %0\n\t"
  76                           : "=a" (a), "=c" (c)
  77                           :
  78                           : "cc"
  79                           );
  80
  81         return a != c;
  82 }
  83
  84 static void
  85 do_cpuid(unsigned int ax, unsigned int *p)
  86 {
  87 #if 0
  88         __asm__ volatile(
  89         "cpuid;"
  90         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  91         :  "0" (ax)
  92         );
  93 #else
  94 // code from libavcodec:
  95     __asm__ volatile
  96         ("mov %%"REG_b", %%"REG_S"\n\t"
  97          "cpuid\n\t"
  98          "xchg %%"REG_b", %%"REG_S
  99          : "=a" (p[0]), "=S" (p[1]),
 100            "=c" (p[2]), "=d" (p[3])
 101          : "0" (ax));
 102 #endif
 103
 104 }
 105
 106 void GetCpuCaps( CpuCaps *caps)
 107 {
 108         unsigned int regs[4];
 109         unsigned int regs2[4];
 110
 111         memset(caps, 0, sizeof(*caps));
 112         caps->isX86=1;
 113         caps->cl_size=32; /* default */
 114         if (!has_cpuid()) {
 115             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 116             return;
 117         }
 118         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 119         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 120                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 121         if (regs[0]>=0x00000001)
 122         {
 123                 char *tmpstr, *ptmpstr;
 124                 unsigned cl_size;
 125
 126                 do_cpuid(0x00000001, regs2);
 127
 128                 caps->cpuType=(regs2[0] >> 8)&0xf;
 129                 caps->cpuModel=(regs2[0] >> 4)&0xf;
 130
 131 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 132 // System Instructions, Table 3-2: Effective family computation, page 120.
 133                 if(caps->cpuType==0xf){
 134                     // use extended family (P4, IA64, K8)
 135                     caps->cpuType=0xf+((regs2[0]>>20)&255);
 136                 }
 137                 if(caps->cpuType==0xf || caps->cpuType==6)
 138                     caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 139
 140                 caps->cpuStepping=regs2[0] & 0xf;
 141
 142                 // general feature flags:
 143                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 144                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 145                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 146                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 147                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 148                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 149                 if(cl_size) caps->cl_size = cl_size;
 150
 151                 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 152                 while(*ptmpstr == ' ')        // strip leading spaces
 153                     ptmpstr++;
 154                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ", ptmpstr);
 155                 free(tmpstr);
 156                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Model: %d, Stepping: %d)\n",
 157                     caps->cpuType, caps->cpuModel, caps->cpuStepping);
 158
 159         }
 160         do_cpuid(0x80000000, regs);
 161         if (regs[0]>=0x80000001) {
 162                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 163                 do_cpuid(0x80000001, regs2);
 164                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 165                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 166                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 167                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 168         }
 169         if(regs[0]>=0x80000006)
 170         {
 171                 do_cpuid(0x80000006, regs2);
 172                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 173                 caps->cl_size  = regs2[2] & 0xFF;
 174         }
 175         mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 176 #if 0
 177         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 178                 gCpuCaps.hasMMX,
 179                 gCpuCaps.hasMMX2,
 180                 gCpuCaps.hasSSE,
 181                 gCpuCaps.hasSSE2,
 182                 gCpuCaps.has3DNow,
 183                 gCpuCaps.has3DNowExt );
 184 #endif
 185
 186                 /* FIXME: Does SSE2 need more OS support, too? */
 187 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \
 188   || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \
 189   || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \
 190   || defined(__OS2__)
 191                 if (caps->hasSSE)
 192                         check_os_katmai_support();
 193                 if (!caps->hasSSE)
 194                         caps->hasSSE2 = 0;
 195 #else
 196                 caps->hasSSE=0;
 197                 caps->hasSSE2 = 0;
 198 #endif
 199 //              caps->has3DNow=1;
 200 //              caps->hasMMX2 = 0;
 201 //              caps->hasMMX = 0;
 202
 203 #ifndef RUNTIME_CPUDETECT
 204 #ifndef HAVE_MMX
 205         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 206         caps->hasMMX=0;
 207 #endif
 208 #ifndef HAVE_MMX2
 209         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 210         caps->hasMMX2=0;
 211 #endif
 212 #ifndef HAVE_SSE
 213         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 214         caps->hasSSE=0;
 215 #endif
 216 #ifndef HAVE_SSE2
 217         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 218         caps->hasSSE2=0;
 219 #endif
 220 #ifndef HAVE_3DNOW
 221         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 222         caps->has3DNow=0;
 223 #endif
 224 #ifndef HAVE_3DNOWEX
 225         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 226         caps->has3DNowExt=0;
 227 #endif
 228 #endif  // RUNTIME_CPUDETECT
 229 }
 230
 231
 232 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
 233 #define CPUID_EXTMODEL  ((regs2[0] >> 16)&0x0F) /* 19..16 */
 234 #define CPUID_TYPE              ((regs2[0] >> 12)&0x04) /* 13..12 */
 235 #define CPUID_FAMILY    ((regs2[0] >>  8)&0x0F) /* 11..08 */
 236 #define CPUID_MODEL             ((regs2[0] >>  4)&0x0F) /* 07..04 */
 237 #define CPUID_STEPPING  ((regs2[0] >>  0)&0x0F) /* 03..00 */
 238
 239 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 240 #include "cputable.h" /* get cpuname and cpuvendors */
 241         char vendor[13];
 242         char *retname;
 243         int i;
 244
 245         if (NULL==(retname=malloc(256))) {
 246                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 247                 exit(1);
 248         }
 249
 250         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 251
 252         do_cpuid(0x80000000,regs);
 253         if (regs[0] >= 0x80000004)
 254         {
 255                 // CPU has built-in namestring
 256                 retname[0] = '\0';
 257                 for (i = 0x80000002; i <= 0x80000004; i++)
 258                 {
 259                         do_cpuid(i, regs);
 260                         strncat(retname, (char*)regs, 16);
 261                 }
 262                 return retname;
 263         }
 264
 265         for(i=0; i<MAX_VENDORS; i++){
 266                 if(!strcmp(cpuvendors[i].string,vendor)){
 267                         if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
 268                                 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
 269                         } else {
 270                                 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
 271                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name);
 272                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor:   %s\n",cpuvendors[i].string);
 273                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type:     %d\n",CPUID_TYPE);
 274                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family:   %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
 275                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model:    %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
 276                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING);
 277                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name"
 278                                        "to the MPlayer-Developers, so we can add it to the list!\n");
 279                         }
 280                 }
 281         }
 282         retname[255] = 0;
 283
 284         //printf("Detected CPU: %s\n", retname);
 285         return retname;
 286 }
 287
 288 #undef CPUID_EXTFAMILY
 289 #undef CPUID_EXTMODEL
 290 #undef CPUID_TYPE
 291 #undef CPUID_FAMILY
 292 #undef CPUID_MODEL
 293 #undef CPUID_STEPPING
 294
 295
 296 #if defined(__linux__) && defined(_POSIX_SOURCE) && !defined(ARCH_X86_64)
 297 static void sigill_handler_sse( int signal, struct sigcontext sc )
 298 {
 299    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 300
 301    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 302     * instructions are 3 bytes long.  We must increment the instruction
 303     * pointer manually to avoid repeated execution of the offending
 304     * instruction.
 305     *
 306     * If the SIGILL is caused by a divide-by-zero when unmasked
 307     * exceptions aren't supported, the SIMD FPU status and control
 308     * word will be restored at the end of the test, so we don't need
 309     * to worry about doing it here.  Besides, we may not be able to...
 310     */
 311    sc.eip += 3;
 312
 313    gCpuCaps.hasSSE=0;
 314 }
 315 #endif /* __linux__ && _POSIX_SOURCE */
 316
 317 #if defined(__MINGW32__) || defined(__CYGWIN__)
 318 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 319 {
 320    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 321       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 322       ep->ContextRecord->Eip +=3;
 323       gCpuCaps.hasSSE=0;
 324           return EXCEPTION_CONTINUE_EXECUTION;
 325    }
 326    return EXCEPTION_CONTINUE_SEARCH;
 327 }
 328 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
 329
 330 #ifdef __OS2__
 331 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD       p1,
 332                                    PEXCEPTIONREGISTRATIONRECORD p2,
 333                                    PCONTEXTRECORD               p3,
 334                                    PVOID                        p4 )
 335 {
 336    if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
 337       mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
 338
 339       p3->ctx_RegEip += 3;
 340       gCpuCaps.hasSSE = 0;
 341
 342       return XCPT_CONTINUE_EXECUTION;
 343    }
 344    return XCPT_CONTINUE_SEARCH;
 345 }
 346 #endif
 347
 348 /* If we're running on a processor that can do SSE, let's see if we
 349  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 350  * haven't been configured for a Pentium III but are running on one,
 351  * and RedHat patched 2.2 kernels that have broken exception handling
 352  * support for user space apps that do SSE.
 353  */
 354
 355 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
 356 #define SSE_SYSCTL_NAME "hw.instruction_sse"
 357 #elif defined(__APPLE__)
 358 #define SSE_SYSCTL_NAME "hw.optional.sse"
 359 #endif
 360
 361 static void check_os_katmai_support( void )
 362 {
 363 #ifdef ARCH_X86_64
 364    gCpuCaps.hasSSE=1;
 365    gCpuCaps.hasSSE2=1;
 366 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 367    int has_sse=0, ret;
 368    size_t len=sizeof(has_sse);
 369
 370    ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 371    if (ret || !has_sse)
 372       gCpuCaps.hasSSE=0;
 373
 374 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 375 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 376    int has_sse, has_sse2, ret, mib[2];
 377    size_t varlen;
 378
 379    mib[0] = CTL_MACHDEP;
 380    mib[1] = CPU_SSE;
 381    varlen = sizeof(has_sse);
 382
 383    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 384    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 385    gCpuCaps.hasSSE = ret >= 0 && has_sse;
 386    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 387
 388    mib[1] = CPU_SSE2;
 389    varlen = sizeof(has_sse2);
 390    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 391    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 392    gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
 393    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
 394 #else
 395    gCpuCaps.hasSSE = 0;
 396    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 397 #endif
 398 #elif defined(__MINGW32__) || defined(__CYGWIN__)
 399    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 400    if ( gCpuCaps.hasSSE ) {
 401       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 402       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 403       __asm__ volatile ("xorps %xmm0, %xmm0");
 404       SetUnhandledExceptionFilter(exc_fil);
 405       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 406    }
 407 #elif defined(__OS2__)
 408    EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
 409    if ( gCpuCaps.hasSSE ) {
 410       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 411       DosSetExceptionHandler( &RegRec );
 412       __asm__ volatile ("xorps %xmm0, %xmm0");
 413       DosUnsetExceptionHandler( &RegRec );
 414       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 415    }
 416 #elif defined(__linux__)
 417 #if defined(_POSIX_SOURCE)
 418    struct sigaction saved_sigill;
 419
 420    /* Save the original signal handlers.
 421     */
 422    sigaction( SIGILL, NULL, &saved_sigill );
 423
 424    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 425
 426    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 427     * supports the extended FPU save and restore required for SSE.  If
 428     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 429     * doesn't support Streaming SIMD Exceptions, even if the processor
 430     * does.
 431     */
 432    if ( gCpuCaps.hasSSE ) {
 433       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 434
 435 //      __asm__ volatile ("xorps %%xmm0, %%xmm0");
 436       __asm__ volatile ("xorps %xmm0, %xmm0");
 437
 438       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 439    }
 440
 441    /* Restore the original signal handlers.
 442     */
 443    sigaction( SIGILL, &saved_sigill, NULL );
 444
 445    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 446     * safe to go ahead and hook out the SSE code throughout Mesa.
 447     */
 448    mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
 449 #else
 450    /* We can't use POSIX signal handling to test the availability of
 451     * SSE, so we disable it by default.
 452     */
 453    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 454    gCpuCaps.hasSSE=0;
 455 #endif /* _POSIX_SOURCE */
 456 #else
 457    /* Do nothing on other platforms for now.
 458     */
 459    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 460    gCpuCaps.hasSSE=0;
 461 #endif /* __linux__ */
 462 }
 463 #else /* ARCH_X86 */
 464
 465 #ifdef __APPLE__
 466 #include <sys/sysctl.h>
 467 #elif __AMIGAOS4__
 468 /* nothing */
 469 #else
 470 #include <signal.h>
 471 #include <setjmp.h>
 472
 473 static sigjmp_buf jmpbuf;
 474 static volatile sig_atomic_t canjump = 0;
 475
 476 static void sigill_handler (int sig)
 477 {
 478     if (!canjump) {
 479         signal (sig, SIG_DFL);
 480         raise (sig);
 481     }
 482
 483     canjump = 0;
 484     siglongjmp (jmpbuf, 1);
 485 }
 486 #endif /* __APPLE__ */
 487
 488 void GetCpuCaps( CpuCaps *caps)
 489 {
 490         caps->cpuType=0;
 491         caps->cpuModel=0;
 492         caps->cpuStepping=0;
 493         caps->hasMMX=0;
 494         caps->hasMMX2=0;
 495         caps->has3DNow=0;
 496         caps->has3DNowExt=0;
 497         caps->hasSSE=0;
 498         caps->hasSSE2=0;
 499         caps->isX86=0;
 500         caps->hasAltiVec = 0;
 501 #ifdef HAVE_ALTIVEC
 502 #ifdef __APPLE__
 503 /*
 504   rip-off from ffmpeg altivec detection code.
 505   this code also appears on Apple's AltiVec pages.
 506  */
 507         {
 508                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 509                 int has_vu = 0;
 510                 size_t len = sizeof(has_vu);
 511                 int err;
 512
 513                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 514
 515                 if (err == 0)
 516                         if (has_vu != 0)
 517                                 caps->hasAltiVec = 1;
 518         }
 519 #elif __AMIGAOS4__
 520         ULONG result = 0;
 521
 522         GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 523         if (result == VECTORTYPE_ALTIVEC)
 524                 caps->hasAltiVec = 1;
 525 #else
 526 /* no Darwin, do it the brute-force way */
 527 /* this is borrowed from the libmpeg2 library */
 528         {
 529           signal (SIGILL, sigill_handler);
 530           if (sigsetjmp (jmpbuf, 1)) {
 531             signal (SIGILL, SIG_DFL);
 532           } else {
 533             canjump = 1;
 534
 535             __asm__ volatile ("mtspr 256, %0\n\t"
 536                           "vand %%v0, %%v0, %%v0"
 537                           :
 538                           : "r" (-1));
 539
 540             signal (SIGILL, SIG_DFL);
 541             caps->hasAltiVec = 1;
 542           }
 543         }
 544 #endif /* __APPLE__ */
 545         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 546 #endif /* HAVE_ALTIVEC */
 547
 548 #ifdef ARCH_IA64
 549         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n");
 550 #endif
 551
 552 #ifdef ARCH_SPARC
 553         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n");
 554 #endif
 555
 556 #ifdef ARCH_ARMV4L
 557         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n");
 558 #endif
 559
 560 #ifdef ARCH_POWERPC
 561         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n");
 562 #endif
 563
 564 #ifdef ARCH_ALPHA
 565         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n");
 566 #endif
 567
 568 #ifdef ARCH_SGI_MIPS
 569         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n");
 570 #endif
 571
 572 #ifdef ARCH_PA_RISC
 573         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n");
 574 #endif
 575
 576 #ifdef ARCH_S390
 577         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n");
 578 #endif
 579
 580 #ifdef ARCH_S390X
 581         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n");
 582 #endif
 583
 584 #ifdef ARCH_VAX
 585         mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" );
 586 #endif
 587
 588 #ifdef ARCH_XTENSA
 589         mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Tensilica Xtensa\n" );
 590 #endif
 591 }
 592 #endif /* !ARCH_X86 */