cpudetect.c

   1 /*
   2  * This file is part of MPlayer.
   3  *
   4  * MPlayer is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * MPlayer is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with MPlayer; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include "config.h"
  20 #include "cpudetect.h"
  21 #include "mp_msg.h"
  22
  23 CpuCaps gCpuCaps;
  24
  25 #include <stdlib.h>
  26
  27 #if ARCH_X86
  28
  29 #include <stdio.h>
  30 #include <string.h>
  31
  32 #if defined (__NetBSD__) || defined(__OpenBSD__)
  33 #include <sys/param.h>
  34 #include <sys/sysctl.h>
  35 #include <machine/cpu.h>
  36 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
  37 #include <sys/types.h>
  38 #include <sys/sysctl.h>
  39 #elif defined(__linux__)
  40 #include <signal.h>
  41 #elif defined(__MINGW32__) || defined(__CYGWIN__)
  42 #include <windows.h>
  43 #elif defined(__OS2__)
  44 #define INCL_DOS
  45 #include <os2.h>
  46 #elif defined(__AMIGAOS4__)
  47 #include <proto/exec.h>
  48 #endif
  49
  50 /* Thanks to the FreeBSD project for some of this cpuid code, and
  51  * help understanding how to use it.  Thanks to the Mesa
  52  * team for SSE support detection and more cpu detect code.
  53  */
  54
  55 /* I believe this code works.  However, it has only been used on a PII and PIII */
  56
  57 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64
  58 static void sigill_handler_sse( int signal, struct sigcontext sc )
  59 {
  60    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
  61
  62    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
  63     * instructions are 3 bytes long.  We must increment the instruction
  64     * pointer manually to avoid repeated execution of the offending
  65     * instruction.
  66     *
  67     * If the SIGILL is caused by a divide-by-zero when unmasked
  68     * exceptions aren't supported, the SIMD FPU status and control
  69     * word will be restored at the end of the test, so we don't need
  70     * to worry about doing it here.  Besides, we may not be able to...
  71     */
  72    sc.eip += 3;
  73
  74    gCpuCaps.hasSSE=0;
  75 }
  76 #endif /* __linux__ && _POSIX_SOURCE */
  77
  78 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64
  79 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
  80 {
  81     if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
  82         mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
  83         ep->ContextRecord->Eip +=3;
  84         gCpuCaps.hasSSE=0;
  85         return EXCEPTION_CONTINUE_EXECUTION;
  86     }
  87     return EXCEPTION_CONTINUE_SEARCH;
  88 }
  89 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
  90
  91 #ifdef __OS2__
  92 ULONG _System os2_sig_handler_sse(PEXCEPTIONREPORTRECORD       p1,
  93                                   PEXCEPTIONREGISTRATIONRECORD p2,
  94                                   PCONTEXTRECORD               p3,
  95                                   PVOID                        p4)
  96 {
  97     if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
  98         mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
  99
 100         p3->ctx_RegEip += 3;
 101         gCpuCaps.hasSSE = 0;
 102
 103         return XCPT_CONTINUE_EXECUTION;
 104     }
 105     return XCPT_CONTINUE_SEARCH;
 106 }
 107 #endif
 108
 109 /* If we're running on a processor that can do SSE, let's see if we
 110  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 111  * haven't been configured for a Pentium III but are running on one,
 112  * and RedHat patched 2.2 kernels that have broken exception handling
 113  * support for user space apps that do SSE.
 114  */
 115
 116 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
 117 #define SSE_SYSCTL_NAME "hw.instruction_sse"
 118 #elif defined(__APPLE__)
 119 #define SSE_SYSCTL_NAME "hw.optional.sse"
 120 #endif
 121
 122 static void check_os_katmai_support( void )
 123 {
 124 #if ARCH_X86_64
 125     gCpuCaps.hasSSE=1;
 126     gCpuCaps.hasSSE2=1;
 127 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 128     int has_sse=0, ret;
 129     size_t len=sizeof(has_sse);
 130
 131     ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 132     if (ret || !has_sse)
 133         gCpuCaps.hasSSE=0;
 134
 135 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 136 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 137     int has_sse, has_sse2, ret, mib[2];
 138     size_t varlen;
 139
 140     mib[0] = CTL_MACHDEP;
 141     mib[1] = CPU_SSE;
 142     varlen = sizeof(has_sse);
 143
 144     mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 145     ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 146     gCpuCaps.hasSSE = ret >= 0 && has_sse;
 147     mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 148
 149     mib[1] = CPU_SSE2;
 150     varlen = sizeof(has_sse2);
 151     mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 152     ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 153     gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
 154     mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
 155 #else
 156     gCpuCaps.hasSSE = 0;
 157     mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 158 #endif
 159 #elif defined(__MINGW32__) || defined(__CYGWIN__)
 160     LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 161     if ( gCpuCaps.hasSSE ) {
 162         mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 163         exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 164         __asm__ volatile ("xorps %xmm0, %xmm0");
 165         SetUnhandledExceptionFilter(exc_fil);
 166         mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 167     }
 168 #elif defined(__OS2__)
 169     EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
 170     if ( gCpuCaps.hasSSE ) {
 171         mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 172         DosSetExceptionHandler( &RegRec );
 173         __asm__ volatile ("xorps %xmm0, %xmm0");
 174         DosUnsetExceptionHandler( &RegRec );
 175         mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 176     }
 177 #elif defined(__linux__)
 178 #if defined(_POSIX_SOURCE)
 179     struct sigaction saved_sigill;
 180
 181     /* Save the original signal handlers.
 182      */
 183     sigaction( SIGILL, NULL, &saved_sigill );
 184
 185     signal( SIGILL, (void (*)(int))sigill_handler_sse );
 186
 187     /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 188      * supports the extended FPU save and restore required for SSE.  If
 189      * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 190      * doesn't support Streaming SIMD Exceptions, even if the processor
 191      * does.
 192      */
 193     if ( gCpuCaps.hasSSE ) {
 194         mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 195
 196 //      __asm__ volatile ("xorps %%xmm0, %%xmm0");
 197         __asm__ volatile ("xorps %xmm0, %xmm0");
 198
 199         mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 200     }
 201
 202     /* Restore the original signal handlers.
 203      */
 204     sigaction( SIGILL, &saved_sigill, NULL );
 205
 206     /* If we've gotten to here and the XMM CPUID bit is still set, we're
 207      * safe to go ahead and hook out the SSE code throughout Mesa.
 208      */
 209     mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
 210 #else
 211     /* We can't use POSIX signal handling to test the availability of
 212      * SSE, so we disable it by default.
 213      */
 214     mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 215     gCpuCaps.hasSSE=0;
 216 #endif /* _POSIX_SOURCE */
 217 #else
 218     /* Do nothing on other platforms for now.
 219      */
 220     mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 221     gCpuCaps.hasSSE=0;
 222 #endif /* __linux__ */
 223 }
 224
 225
 226 // return TRUE if cpuid supported
 227 static int has_cpuid(void)
 228 {
 229 // code from libavcodec:
 230 #if ARCH_X86_64
 231    return 1;
 232 #else
 233    long a, c;
 234    __asm__ volatile (
 235        /* See if CPUID instruction is supported ... */
 236        /* ... Get copies of EFLAGS into eax and ecx */
 237        "pushfl\n\t"
 238        "pop %0\n\t"
 239        "mov %0, %1\n\t"
 240
 241        /* ... Toggle the ID bit in one copy and store */
 242        /*     to the EFLAGS reg */
 243        "xor $0x200000, %0\n\t"
 244        "push %0\n\t"
 245        "popfl\n\t"
 246
 247        /* ... Get the (hopefully modified) EFLAGS */
 248        "pushfl\n\t"
 249        "pop %0\n\t"
 250        : "=a" (a), "=c" (c)
 251        :
 252        : "cc"
 253        );
 254
 255    return a != c;
 256 #endif
 257 }
 258
 259 void
 260 do_cpuid(unsigned int ax, unsigned int *p)
 261 {
 262 // code from libavcodec:
 263     __asm__ volatile
 264         ("mov %%"REG_b", %%"REG_S"\n\t"
 265          "cpuid\n\t"
 266          "xchg %%"REG_b", %%"REG_S
 267          : "=a" (p[0]), "=S" (p[1]),
 268            "=c" (p[2]), "=d" (p[3])
 269          : "0" (ax));
 270 }
 271
 272 void GetCpuCaps( CpuCaps *caps)
 273 {
 274     unsigned int regs[4];
 275     unsigned int regs2[4];
 276
 277     memset(caps, 0, sizeof(*caps));
 278     caps->isX86=1;
 279     caps->cl_size=32; /* default */
 280     if (!has_cpuid()) {
 281         mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 282         return;
 283     }
 284     do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 285     mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 286             (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 287     if (regs[0]>=0x00000001)
 288     {
 289         char *tmpstr, *ptmpstr;
 290         unsigned cl_size;
 291
 292         do_cpuid(0x00000001, regs2);
 293
 294         caps->cpuType=(regs2[0] >> 8)&0xf;
 295         caps->cpuModel=(regs2[0] >> 4)&0xf;
 296
 297 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 298 // System Instructions, Table 3-2: Effective family computation, page 120.
 299         if(caps->cpuType==0xf){
 300             // use extended family (P4, IA64, K8)
 301             caps->cpuType=0xf+((regs2[0]>>20)&255);
 302         }
 303         if(caps->cpuType==0xf || caps->cpuType==6)
 304             caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 305
 306         caps->cpuStepping=regs2[0] & 0xf;
 307
 308         // general feature flags:
 309         caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 310         caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 311         caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 312         caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 313         caps->hasSSE3 = (regs2[2] & 1);        // 0x0000001
 314         caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >>  9; // 0x0000200
 315         caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 316         cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 317         if(cl_size) caps->cl_size = cl_size;
 318
 319         ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 320         while(*ptmpstr == ' ')    // strip leading spaces
 321             ptmpstr++;
 322         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr);
 323         free(tmpstr);
 324         mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n",
 325                caps->cpuType, caps->cpuModel, caps->cpuStepping);
 326
 327     }
 328     do_cpuid(0x80000000, regs);
 329     if (regs[0]>=0x80000001) {
 330         mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 331         do_cpuid(0x80000001, regs2);
 332         caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 333         caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 334         caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 335         caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 336         caps->hasSSE4a = (regs2[2] & (1 << 6 )) >>  6; // 0x0000040
 337     }
 338     if(regs[0]>=0x80000006)
 339     {
 340         do_cpuid(0x80000006, regs2);
 341         mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 342         caps->cl_size  = regs2[2] & 0xFF;
 343     }
 344     mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 345 #if 0
 346     mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 347            gCpuCaps.hasMMX,
 348            gCpuCaps.hasMMX2,
 349            gCpuCaps.hasSSE,
 350            gCpuCaps.hasSSE2,
 351            gCpuCaps.has3DNow,
 352            gCpuCaps.has3DNowExt);
 353 #endif
 354
 355         /* FIXME: Does SSE2 need more OS support, too? */
 356         if (caps->hasSSE)
 357             check_os_katmai_support();
 358         if (!caps->hasSSE)
 359             caps->hasSSE2 = 0;
 360 //          caps->has3DNow=1;
 361 //          caps->hasMMX2 = 0;
 362 //          caps->hasMMX = 0;
 363
 364 #if !CONFIG_RUNTIME_CPUDETECT
 365 #if !HAVE_MMX
 366         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 367         caps->hasMMX=0;
 368 #endif
 369 #if !HAVE_MMX2
 370         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 371         caps->hasMMX2=0;
 372 #endif
 373 #if !HAVE_SSE
 374         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 375         caps->hasSSE=0;
 376 #endif
 377 #if !HAVE_SSE2
 378         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 379         caps->hasSSE2=0;
 380 #endif
 381 #if !HAVE_AMD3DNOW
 382         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 383         caps->has3DNow=0;
 384 #endif
 385 #if !HAVE_AMD3DNOWEXT
 386         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 387         caps->has3DNowExt=0;
 388 #endif
 389 #endif  // CONFIG_RUNTIME_CPUDETECT
 390 }
 391
 392 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 393     char vendor[13];
 394     char *retname;
 395     int i;
 396
 397     if (NULL==(retname=malloc(256))) {
 398         mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 399         exit(1);
 400     }
 401     retname[0] = '\0';
 402
 403     sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 404
 405     do_cpuid(0x80000000,regs);
 406     if (regs[0] >= 0x80000004)
 407     {
 408         // CPU has built-in namestring
 409         for (i = 0x80000002; i <= 0x80000004; i++)
 410         {
 411             do_cpuid(i, regs);
 412             strncat(retname, (char*)regs, 16);
 413         }
 414     }
 415     return retname;
 416 }
 417
 418 #else /* ARCH_X86 */
 419
 420 #ifdef __APPLE__
 421 #include <sys/sysctl.h>
 422 #elif defined(__AMIGAOS4__)
 423 /* nothing */
 424 #else
 425 #include <signal.h>
 426 #include <setjmp.h>
 427
 428 static sigjmp_buf jmpbuf;
 429 static volatile sig_atomic_t canjump = 0;
 430
 431 static void sigill_handler (int sig)
 432 {
 433     if (!canjump) {
 434         signal (sig, SIG_DFL);
 435         raise (sig);
 436     }
 437
 438     canjump = 0;
 439     siglongjmp (jmpbuf, 1);
 440 }
 441 #endif /* __APPLE__ */
 442
 443 void GetCpuCaps( CpuCaps *caps)
 444 {
 445     caps->cpuType=0;
 446     caps->cpuModel=0;
 447     caps->cpuStepping=0;
 448     caps->hasMMX=0;
 449     caps->hasMMX2=0;
 450     caps->has3DNow=0;
 451     caps->has3DNowExt=0;
 452     caps->hasSSE=0;
 453     caps->hasSSE2=0;
 454     caps->hasSSE3=0;
 455     caps->hasSSSE3=0;
 456     caps->hasSSE4a=0;
 457     caps->isX86=0;
 458     caps->hasAltiVec = 0;
 459 #if HAVE_ALTIVEC
 460 #ifdef __APPLE__
 461 /*
 462   rip-off from ffmpeg altivec detection code.
 463   this code also appears on Apple's AltiVec pages.
 464  */
 465     {
 466         int sels[2] = {CTL_HW, HW_VECTORUNIT};
 467         int has_vu = 0;
 468         size_t len = sizeof(has_vu);
 469         int err;
 470
 471         err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 472
 473         if (err == 0)
 474             if (has_vu != 0)
 475                 caps->hasAltiVec = 1;
 476     }
 477 #elif defined(__AMIGAOS4__)
 478     ULONG result = 0;
 479
 480     GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 481     if (result == VECTORTYPE_ALTIVEC)
 482         caps->hasAltiVec = 1;
 483 #else
 484 /* no Darwin, do it the brute-force way */
 485 /* this is borrowed from the libmpeg2 library */
 486     {
 487         signal (SIGILL, sigill_handler);
 488         if (sigsetjmp (jmpbuf, 1)) {
 489             signal (SIGILL, SIG_DFL);
 490         } else {
 491             canjump = 1;
 492
 493         __asm__ volatile ("mtspr 256, %0\n\t"
 494                           "vand %%v0, %%v0, %%v0"
 495                           :
 496                           : "r" (-1));
 497
 498         signal (SIGILL, SIG_DFL);
 499         caps->hasAltiVec = 1;
 500         }
 501     }
 502 #endif /* __APPLE__ */
 503     mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 504 #endif /* HAVE_ALTIVEC */
 505
 506     if (ARCH_IA64)
 507         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n");
 508
 509     if (ARCH_SPARC)
 510         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n");
 511
 512     if (ARCH_ARM)
 513         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n");
 514
 515     if (ARCH_PPC)
 516         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n");
 517
 518     if (ARCH_ALPHA)
 519         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n");
 520
 521     if (ARCH_MIPS)
 522         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: MIPS\n");
 523
 524     if (ARCH_PA_RISC)
 525         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n");
 526
 527     if (ARCH_S390)
 528         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n");
 529
 530     if (ARCH_S390X)
 531         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n");
 532
 533     if (ARCH_VAX)
 534         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" );
 535
 536     if (ARCH_XTENSA)
 537         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" );
 538 }
 539 #endif /* !ARCH_X86 */