cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #include <stdlib.h>
   8
   9 #if ARCH_X86
  10
  11 #include <stdio.h>
  12 #include <string.h>
  13
  14 #if defined (__NetBSD__) || defined(__OpenBSD__)
  15 #include <sys/param.h>
  16 #include <sys/sysctl.h>
  17 #include <machine/cpu.h>
  18 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
  19 #include <sys/types.h>
  20 #include <sys/sysctl.h>
  21 #elif defined(__linux__)
  22 #include <signal.h>
  23 #elif defined(__MINGW32__) || defined(__CYGWIN__)
  24 #include <windows.h>
  25 #elif defined(__OS2__)
  26 #define INCL_DOS
  27 #include <os2.h>
  28 #elif defined(__AMIGAOS4__)
  29 #include <proto/exec.h>
  30 #endif
  31
  32 /* Thanks to the FreeBSD project for some of this cpuid code, and
  33  * help understanding how to use it.  Thanks to the Mesa
  34  * team for SSE support detection and more cpu detect code.
  35  */
  36
  37 /* I believe this code works.  However, it has only been used on a PII and PIII */
  38
  39 static void check_os_katmai_support( void );
  40
  41 // return TRUE if cpuid supported
  42 static int has_cpuid(void)
  43 {
  44 // code from libavcodec:
  45 #if ARCH_X86_64
  46    return 1;
  47 #else
  48         long a, c;
  49     __asm__ volatile (
  50                           /* See if CPUID instruction is supported ... */
  51                           /* ... Get copies of EFLAGS into eax and ecx */
  52                           "pushfl\n\t"
  53                           "pop %0\n\t"
  54                           "mov %0, %1\n\t"
  55
  56                           /* ... Toggle the ID bit in one copy and store */
  57                           /*     to the EFLAGS reg */
  58                           "xor $0x200000, %0\n\t"
  59                           "push %0\n\t"
  60                           "popfl\n\t"
  61
  62                           /* ... Get the (hopefully modified) EFLAGS */
  63                           "pushfl\n\t"
  64                           "pop %0\n\t"
  65                           : "=a" (a), "=c" (c)
  66                           :
  67                           : "cc"
  68                           );
  69
  70         return a != c;
  71 #endif
  72 }
  73
  74 static void
  75 do_cpuid(unsigned int ax, unsigned int *p)
  76 {
  77 #if 0
  78         __asm__ volatile(
  79         "cpuid;"
  80         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  81         :  "0" (ax)
  82         );
  83 #else
  84 // code from libavcodec:
  85     __asm__ volatile
  86         ("mov %%"REG_b", %%"REG_S"\n\t"
  87          "cpuid\n\t"
  88          "xchg %%"REG_b", %%"REG_S
  89          : "=a" (p[0]), "=S" (p[1]),
  90            "=c" (p[2]), "=d" (p[3])
  91          : "0" (ax));
  92 #endif
  93
  94 }
  95
  96 void GetCpuCaps( CpuCaps *caps)
  97 {
  98         unsigned int regs[4];
  99         unsigned int regs2[4];
 100
 101         memset(caps, 0, sizeof(*caps));
 102         caps->isX86=1;
 103         caps->cl_size=32; /* default */
 104         if (!has_cpuid()) {
 105             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 106             return;
 107         }
 108         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 109         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 110                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 111         if (regs[0]>=0x00000001)
 112         {
 113                 char *tmpstr, *ptmpstr;
 114                 unsigned cl_size;
 115
 116                 do_cpuid(0x00000001, regs2);
 117
 118                 caps->cpuType=(regs2[0] >> 8)&0xf;
 119                 caps->cpuModel=(regs2[0] >> 4)&0xf;
 120
 121 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 122 // System Instructions, Table 3-2: Effective family computation, page 120.
 123                 if(caps->cpuType==0xf){
 124                     // use extended family (P4, IA64, K8)
 125                     caps->cpuType=0xf+((regs2[0]>>20)&255);
 126                 }
 127                 if(caps->cpuType==0xf || caps->cpuType==6)
 128                     caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 129
 130                 caps->cpuStepping=regs2[0] & 0xf;
 131
 132                 // general feature flags:
 133                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 134                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 135                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 136                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 137                 caps->hasSSE3 = (regs2[2] & 1);                // 0x0000001
 138                 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >>  9; // 0x0000200
 139                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 140                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 141                 if(cl_size) caps->cl_size = cl_size;
 142
 143                 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 144                 while(*ptmpstr == ' ')        // strip leading spaces
 145                     ptmpstr++;
 146                 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr);
 147                 free(tmpstr);
 148                 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n",
 149                     caps->cpuType, caps->cpuModel, caps->cpuStepping);
 150
 151         }
 152         do_cpuid(0x80000000, regs);
 153         if (regs[0]>=0x80000001) {
 154                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 155                 do_cpuid(0x80000001, regs2);
 156                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 157                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 158                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 159                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 160                 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >>  6; // 0x0000040
 161         }
 162         if(regs[0]>=0x80000006)
 163         {
 164                 do_cpuid(0x80000006, regs2);
 165                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 166                 caps->cl_size  = regs2[2] & 0xFF;
 167         }
 168         mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 169 #if 0
 170         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 171                 gCpuCaps.hasMMX,
 172                 gCpuCaps.hasMMX2,
 173                 gCpuCaps.hasSSE,
 174                 gCpuCaps.hasSSE2,
 175                 gCpuCaps.has3DNow,
 176                 gCpuCaps.has3DNowExt );
 177 #endif
 178
 179                 /* FIXME: Does SSE2 need more OS support, too? */
 180 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \
 181   || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \
 182   || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \
 183   || defined(__OS2__)
 184                 if (caps->hasSSE)
 185                         check_os_katmai_support();
 186                 if (!caps->hasSSE)
 187                         caps->hasSSE2 = 0;
 188 #else
 189                 caps->hasSSE=0;
 190                 caps->hasSSE2 = 0;
 191 #endif
 192 //              caps->has3DNow=1;
 193 //              caps->hasMMX2 = 0;
 194 //              caps->hasMMX = 0;
 195
 196 #if !CONFIG_RUNTIME_CPUDETECT
 197 #if !HAVE_MMX
 198         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 199         caps->hasMMX=0;
 200 #endif
 201 #if !HAVE_MMX2
 202         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 203         caps->hasMMX2=0;
 204 #endif
 205 #if !HAVE_SSE
 206         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 207         caps->hasSSE=0;
 208 #endif
 209 #if !HAVE_SSE2
 210         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 211         caps->hasSSE2=0;
 212 #endif
 213 #if !HAVE_AMD3DNOW
 214         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 215         caps->has3DNow=0;
 216 #endif
 217 #if !HAVE_AMD3DNOWEXT
 218         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 219         caps->has3DNowExt=0;
 220 #endif
 221 #endif  // CONFIG_RUNTIME_CPUDETECT
 222 }
 223
 224 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 225         char vendor[13];
 226         char *retname;
 227         int i;
 228
 229         if (NULL==(retname=malloc(256))) {
 230                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 231                 exit(1);
 232         }
 233         retname[0] = '\0';
 234
 235         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 236
 237         do_cpuid(0x80000000,regs);
 238         if (regs[0] >= 0x80000004)
 239         {
 240                 // CPU has built-in namestring
 241                 for (i = 0x80000002; i <= 0x80000004; i++)
 242                 {
 243                         do_cpuid(i, regs);
 244                         strncat(retname, (char*)regs, 16);
 245                 }
 246         }
 247         return retname;
 248 }
 249
 250 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64
 251 static void sigill_handler_sse( int signal, struct sigcontext sc )
 252 {
 253    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 254
 255    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 256     * instructions are 3 bytes long.  We must increment the instruction
 257     * pointer manually to avoid repeated execution of the offending
 258     * instruction.
 259     *
 260     * If the SIGILL is caused by a divide-by-zero when unmasked
 261     * exceptions aren't supported, the SIMD FPU status and control
 262     * word will be restored at the end of the test, so we don't need
 263     * to worry about doing it here.  Besides, we may not be able to...
 264     */
 265    sc.eip += 3;
 266
 267    gCpuCaps.hasSSE=0;
 268 }
 269 #endif /* __linux__ && _POSIX_SOURCE */
 270
 271 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64
 272 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 273 {
 274    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 275       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 276       ep->ContextRecord->Eip +=3;
 277       gCpuCaps.hasSSE=0;
 278           return EXCEPTION_CONTINUE_EXECUTION;
 279    }
 280    return EXCEPTION_CONTINUE_SEARCH;
 281 }
 282 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
 283
 284 #ifdef __OS2__
 285 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD       p1,
 286                                    PEXCEPTIONREGISTRATIONRECORD p2,
 287                                    PCONTEXTRECORD               p3,
 288                                    PVOID                        p4 )
 289 {
 290    if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
 291       mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
 292
 293       p3->ctx_RegEip += 3;
 294       gCpuCaps.hasSSE = 0;
 295
 296       return XCPT_CONTINUE_EXECUTION;
 297    }
 298    return XCPT_CONTINUE_SEARCH;
 299 }
 300 #endif
 301
 302 /* If we're running on a processor that can do SSE, let's see if we
 303  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 304  * haven't been configured for a Pentium III but are running on one,
 305  * and RedHat patched 2.2 kernels that have broken exception handling
 306  * support for user space apps that do SSE.
 307  */
 308
 309 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
 310 #define SSE_SYSCTL_NAME "hw.instruction_sse"
 311 #elif defined(__APPLE__)
 312 #define SSE_SYSCTL_NAME "hw.optional.sse"
 313 #endif
 314
 315 static void check_os_katmai_support( void )
 316 {
 317 #if ARCH_X86_64
 318    gCpuCaps.hasSSE=1;
 319    gCpuCaps.hasSSE2=1;
 320 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 321    int has_sse=0, ret;
 322    size_t len=sizeof(has_sse);
 323
 324    ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 325    if (ret || !has_sse)
 326       gCpuCaps.hasSSE=0;
 327
 328 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 329 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 330    int has_sse, has_sse2, ret, mib[2];
 331    size_t varlen;
 332
 333    mib[0] = CTL_MACHDEP;
 334    mib[1] = CPU_SSE;
 335    varlen = sizeof(has_sse);
 336
 337    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 338    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 339    gCpuCaps.hasSSE = ret >= 0 && has_sse;
 340    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 341
 342    mib[1] = CPU_SSE2;
 343    varlen = sizeof(has_sse2);
 344    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 345    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 346    gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
 347    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
 348 #else
 349    gCpuCaps.hasSSE = 0;
 350    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 351 #endif
 352 #elif defined(__MINGW32__) || defined(__CYGWIN__)
 353    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 354    if ( gCpuCaps.hasSSE ) {
 355       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 356       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 357       __asm__ volatile ("xorps %xmm0, %xmm0");
 358       SetUnhandledExceptionFilter(exc_fil);
 359       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 360    }
 361 #elif defined(__OS2__)
 362    EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
 363    if ( gCpuCaps.hasSSE ) {
 364       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 365       DosSetExceptionHandler( &RegRec );
 366       __asm__ volatile ("xorps %xmm0, %xmm0");
 367       DosUnsetExceptionHandler( &RegRec );
 368       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 369    }
 370 #elif defined(__linux__)
 371 #if defined(_POSIX_SOURCE)
 372    struct sigaction saved_sigill;
 373
 374    /* Save the original signal handlers.
 375     */
 376    sigaction( SIGILL, NULL, &saved_sigill );
 377
 378    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 379
 380    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 381     * supports the extended FPU save and restore required for SSE.  If
 382     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 383     * doesn't support Streaming SIMD Exceptions, even if the processor
 384     * does.
 385     */
 386    if ( gCpuCaps.hasSSE ) {
 387       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 388
 389 //      __asm__ volatile ("xorps %%xmm0, %%xmm0");
 390       __asm__ volatile ("xorps %xmm0, %xmm0");
 391
 392       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 393    }
 394
 395    /* Restore the original signal handlers.
 396     */
 397    sigaction( SIGILL, &saved_sigill, NULL );
 398
 399    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 400     * safe to go ahead and hook out the SSE code throughout Mesa.
 401     */
 402    mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
 403 #else
 404    /* We can't use POSIX signal handling to test the availability of
 405     * SSE, so we disable it by default.
 406     */
 407    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 408    gCpuCaps.hasSSE=0;
 409 #endif /* _POSIX_SOURCE */
 410 #else
 411    /* Do nothing on other platforms for now.
 412     */
 413    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 414    gCpuCaps.hasSSE=0;
 415 #endif /* __linux__ */
 416 }
 417 #else /* ARCH_X86 */
 418
 419 #ifdef __APPLE__
 420 #include <sys/sysctl.h>
 421 #elif defined(__AMIGAOS4__)
 422 /* nothing */
 423 #else
 424 #include <signal.h>
 425 #include <setjmp.h>
 426
 427 static sigjmp_buf jmpbuf;
 428 static volatile sig_atomic_t canjump = 0;
 429
 430 static void sigill_handler (int sig)
 431 {
 432     if (!canjump) {
 433         signal (sig, SIG_DFL);
 434         raise (sig);
 435     }
 436
 437     canjump = 0;
 438     siglongjmp (jmpbuf, 1);
 439 }
 440 #endif /* __APPLE__ */
 441
 442 void GetCpuCaps( CpuCaps *caps)
 443 {
 444         caps->cpuType=0;
 445         caps->cpuModel=0;
 446         caps->cpuStepping=0;
 447         caps->hasMMX=0;
 448         caps->hasMMX2=0;
 449         caps->has3DNow=0;
 450         caps->has3DNowExt=0;
 451         caps->hasSSE=0;
 452         caps->hasSSE2=0;
 453         caps->hasSSE3=0;
 454         caps->hasSSSE3=0;
 455         caps->hasSSE4a=0;
 456         caps->isX86=0;
 457         caps->hasAltiVec = 0;
 458 #if HAVE_ALTIVEC
 459 #ifdef __APPLE__
 460 /*
 461   rip-off from ffmpeg altivec detection code.
 462   this code also appears on Apple's AltiVec pages.
 463  */
 464         {
 465                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 466                 int has_vu = 0;
 467                 size_t len = sizeof(has_vu);
 468                 int err;
 469
 470                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 471
 472                 if (err == 0)
 473                         if (has_vu != 0)
 474                                 caps->hasAltiVec = 1;
 475         }
 476 #elif defined(__AMIGAOS4__)
 477         ULONG result = 0;
 478
 479         GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 480         if (result == VECTORTYPE_ALTIVEC)
 481                 caps->hasAltiVec = 1;
 482 #else
 483 /* no Darwin, do it the brute-force way */
 484 /* this is borrowed from the libmpeg2 library */
 485         {
 486           signal (SIGILL, sigill_handler);
 487           if (sigsetjmp (jmpbuf, 1)) {
 488             signal (SIGILL, SIG_DFL);
 489           } else {
 490             canjump = 1;
 491
 492             __asm__ volatile ("mtspr 256, %0\n\t"
 493                           "vand %%v0, %%v0, %%v0"
 494                           :
 495                           : "r" (-1));
 496
 497             signal (SIGILL, SIG_DFL);
 498             caps->hasAltiVec = 1;
 499           }
 500         }
 501 #endif /* __APPLE__ */
 502         mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 503 #endif /* HAVE_ALTIVEC */
 504
 505 if (ARCH_IA64)
 506         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n");
 507
 508 if (ARCH_SPARC)
 509         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n");
 510
 511 if (ARCH_ARM)
 512         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n");
 513
 514 if (ARCH_PPC)
 515         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n");
 516
 517 if (ARCH_ALPHA)
 518         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n");
 519
 520 if (ARCH_SGI_MIPS)
 521         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: SGI MIPS\n");
 522
 523 if (ARCH_PA_RISC)
 524         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n");
 525
 526 if (ARCH_S390)
 527         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n");
 528
 529 if (ARCH_S390X)
 530         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n");
 531
 532 if (ARCH_VAX)
 533         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" );
 534
 535 if (ARCH_XTENSA)
 536         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" );
 537 }
 538 #endif /* !ARCH_X86 */