cpudetect.c

   1 /*
   2  * This file is part of MPlayer.
   3  *
   4  * MPlayer is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * MPlayer is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with MPlayer; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include "config.h"
  20 #include "cpudetect.h"
  21 #include "mp_msg.h"
  22
  23 CpuCaps gCpuCaps;
  24
  25 #include <stdlib.h>
  26
  27 #if ARCH_X86
  28
  29 #include <stdio.h>
  30 #include <string.h>
  31
  32 #if defined (__NetBSD__) || defined(__OpenBSD__)
  33 #include <sys/param.h>
  34 #include <sys/sysctl.h>
  35 #include <machine/cpu.h>
  36 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
  37 #include <sys/types.h>
  38 #include <sys/sysctl.h>
  39 #elif defined(__linux__)
  40 #include <signal.h>
  41 #elif defined(__MINGW32__) || defined(__CYGWIN__)
  42 #include <windows.h>
  43 #elif defined(__OS2__)
  44 #define INCL_DOS
  45 #include <os2.h>
  46 #elif defined(__AMIGAOS4__)
  47 #include <proto/exec.h>
  48 #endif
  49
  50 /* Thanks to the FreeBSD project for some of this cpuid code, and
  51  * help understanding how to use it.  Thanks to the Mesa
  52  * team for SSE support detection and more cpu detect code.
  53  */
  54
  55 /* I believe this code works.  However, it has only been used on a PII and PIII */
  56
  57 static void check_os_katmai_support( void );
  58
  59 // return TRUE if cpuid supported
  60 static int has_cpuid(void)
  61 {
  62 // code from libavcodec:
  63 #if ARCH_X86_64
  64    return 1;
  65 #else
  66         long a, c;
  67     __asm__ volatile (
  68                           /* See if CPUID instruction is supported ... */
  69                           /* ... Get copies of EFLAGS into eax and ecx */
  70                           "pushfl\n\t"
  71                           "pop %0\n\t"
  72                           "mov %0, %1\n\t"
  73
  74                           /* ... Toggle the ID bit in one copy and store */
  75                           /*     to the EFLAGS reg */
  76                           "xor $0x200000, %0\n\t"
  77                           "push %0\n\t"
  78                           "popfl\n\t"
  79
  80                           /* ... Get the (hopefully modified) EFLAGS */
  81                           "pushfl\n\t"
  82                           "pop %0\n\t"
  83                           : "=a" (a), "=c" (c)
  84                           :
  85                           : "cc"
  86                           );
  87
  88         return a != c;
  89 #endif
  90 }
  91
  92 static void
  93 do_cpuid(unsigned int ax, unsigned int *p)
  94 {
  95 #if 0
  96         __asm__ volatile(
  97         "cpuid;"
  98         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  99         :  "0" (ax)
 100         );
 101 #else
 102 // code from libavcodec:
 103     __asm__ volatile
 104         ("mov %%"REG_b", %%"REG_S"\n\t"
 105          "cpuid\n\t"
 106          "xchg %%"REG_b", %%"REG_S
 107          : "=a" (p[0]), "=S" (p[1]),
 108            "=c" (p[2]), "=d" (p[3])
 109          : "0" (ax));
 110 #endif
 111
 112 }
 113
 114 void GetCpuCaps( CpuCaps *caps)
 115 {
 116         unsigned int regs[4];
 117         unsigned int regs2[4];
 118
 119         memset(caps, 0, sizeof(*caps));
 120         caps->isX86=1;
 121         caps->cl_size=32; /* default */
 122         if (!has_cpuid()) {
 123             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 124             return;
 125         }
 126         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 127         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 128                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 129         if (regs[0]>=0x00000001)
 130         {
 131                 char *tmpstr, *ptmpstr;
 132                 unsigned cl_size;
 133
 134                 do_cpuid(0x00000001, regs2);
 135
 136                 caps->cpuType=(regs2[0] >> 8)&0xf;
 137                 caps->cpuModel=(regs2[0] >> 4)&0xf;
 138
 139 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 140 // System Instructions, Table 3-2: Effective family computation, page 120.
 141                 if(caps->cpuType==0xf){
 142                     // use extended family (P4, IA64, K8)
 143                     caps->cpuType=0xf+((regs2[0]>>20)&255);
 144                 }
 145                 if(caps->cpuType==0xf || caps->cpuType==6)
 146                     caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 147
 148                 caps->cpuStepping=regs2[0] & 0xf;
 149
 150                 // general feature flags:
 151                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 152                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 153                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 154                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 155                 caps->hasSSE3 = (regs2[2] & 1);                // 0x0000001
 156                 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >>  9; // 0x0000200
 157                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 158                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 159                 if(cl_size) caps->cl_size = cl_size;
 160
 161                 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 162                 while(*ptmpstr == ' ')        // strip leading spaces
 163                     ptmpstr++;
 164                 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr);
 165                 free(tmpstr);
 166                 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n",
 167                     caps->cpuType, caps->cpuModel, caps->cpuStepping);
 168
 169         }
 170         do_cpuid(0x80000000, regs);
 171         if (regs[0]>=0x80000001) {
 172                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 173                 do_cpuid(0x80000001, regs2);
 174                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 175                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 176                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 177                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 178                 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >>  6; // 0x0000040
 179         }
 180         if(regs[0]>=0x80000006)
 181         {
 182                 do_cpuid(0x80000006, regs2);
 183                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 184                 caps->cl_size  = regs2[2] & 0xFF;
 185         }
 186         mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 187 #if 0
 188         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 189                 gCpuCaps.hasMMX,
 190                 gCpuCaps.hasMMX2,
 191                 gCpuCaps.hasSSE,
 192                 gCpuCaps.hasSSE2,
 193                 gCpuCaps.has3DNow,
 194                 gCpuCaps.has3DNowExt );
 195 #endif
 196
 197                 /* FIXME: Does SSE2 need more OS support, too? */
 198                 if (caps->hasSSE)
 199                         check_os_katmai_support();
 200                 if (!caps->hasSSE)
 201                         caps->hasSSE2 = 0;
 202 //              caps->has3DNow=1;
 203 //              caps->hasMMX2 = 0;
 204 //              caps->hasMMX = 0;
 205
 206 #if !CONFIG_RUNTIME_CPUDETECT
 207 #if !HAVE_MMX
 208         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 209         caps->hasMMX=0;
 210 #endif
 211 #if !HAVE_MMX2
 212         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 213         caps->hasMMX2=0;
 214 #endif
 215 #if !HAVE_SSE
 216         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 217         caps->hasSSE=0;
 218 #endif
 219 #if !HAVE_SSE2
 220         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 221         caps->hasSSE2=0;
 222 #endif
 223 #if !HAVE_AMD3DNOW
 224         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 225         caps->has3DNow=0;
 226 #endif
 227 #if !HAVE_AMD3DNOWEXT
 228         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 229         caps->has3DNowExt=0;
 230 #endif
 231 #endif  // CONFIG_RUNTIME_CPUDETECT
 232 }
 233
 234 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 235         char vendor[13];
 236         char *retname;
 237         int i;
 238
 239         if (NULL==(retname=malloc(256))) {
 240                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 241                 exit(1);
 242         }
 243         retname[0] = '\0';
 244
 245         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 246
 247         do_cpuid(0x80000000,regs);
 248         if (regs[0] >= 0x80000004)
 249         {
 250                 // CPU has built-in namestring
 251                 for (i = 0x80000002; i <= 0x80000004; i++)
 252                 {
 253                         do_cpuid(i, regs);
 254                         strncat(retname, (char*)regs, 16);
 255                 }
 256         }
 257         return retname;
 258 }
 259
 260 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64
 261 static void sigill_handler_sse( int signal, struct sigcontext sc )
 262 {
 263    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 264
 265    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 266     * instructions are 3 bytes long.  We must increment the instruction
 267     * pointer manually to avoid repeated execution of the offending
 268     * instruction.
 269     *
 270     * If the SIGILL is caused by a divide-by-zero when unmasked
 271     * exceptions aren't supported, the SIMD FPU status and control
 272     * word will be restored at the end of the test, so we don't need
 273     * to worry about doing it here.  Besides, we may not be able to...
 274     */
 275    sc.eip += 3;
 276
 277    gCpuCaps.hasSSE=0;
 278 }
 279 #endif /* __linux__ && _POSIX_SOURCE */
 280
 281 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64
 282 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 283 {
 284    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 285       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 286       ep->ContextRecord->Eip +=3;
 287       gCpuCaps.hasSSE=0;
 288           return EXCEPTION_CONTINUE_EXECUTION;
 289    }
 290    return EXCEPTION_CONTINUE_SEARCH;
 291 }
 292 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
 293
 294 #ifdef __OS2__
 295 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD       p1,
 296                                    PEXCEPTIONREGISTRATIONRECORD p2,
 297                                    PCONTEXTRECORD               p3,
 298                                    PVOID                        p4 )
 299 {
 300    if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
 301       mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
 302
 303       p3->ctx_RegEip += 3;
 304       gCpuCaps.hasSSE = 0;
 305
 306       return XCPT_CONTINUE_EXECUTION;
 307    }
 308    return XCPT_CONTINUE_SEARCH;
 309 }
 310 #endif
 311
 312 /* If we're running on a processor that can do SSE, let's see if we
 313  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 314  * haven't been configured for a Pentium III but are running on one,
 315  * and RedHat patched 2.2 kernels that have broken exception handling
 316  * support for user space apps that do SSE.
 317  */
 318
 319 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
 320 #define SSE_SYSCTL_NAME "hw.instruction_sse"
 321 #elif defined(__APPLE__)
 322 #define SSE_SYSCTL_NAME "hw.optional.sse"
 323 #endif
 324
 325 static void check_os_katmai_support( void )
 326 {
 327 #if ARCH_X86_64
 328    gCpuCaps.hasSSE=1;
 329    gCpuCaps.hasSSE2=1;
 330 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 331    int has_sse=0, ret;
 332    size_t len=sizeof(has_sse);
 333
 334    ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 335    if (ret || !has_sse)
 336       gCpuCaps.hasSSE=0;
 337
 338 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 339 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 340    int has_sse, has_sse2, ret, mib[2];
 341    size_t varlen;
 342
 343    mib[0] = CTL_MACHDEP;
 344    mib[1] = CPU_SSE;
 345    varlen = sizeof(has_sse);
 346
 347    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 348    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 349    gCpuCaps.hasSSE = ret >= 0 && has_sse;
 350    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 351
 352    mib[1] = CPU_SSE2;
 353    varlen = sizeof(has_sse2);
 354    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 355    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 356    gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
 357    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
 358 #else
 359    gCpuCaps.hasSSE = 0;
 360    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 361 #endif
 362 #elif defined(__MINGW32__) || defined(__CYGWIN__)
 363    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 364    if ( gCpuCaps.hasSSE ) {
 365       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 366       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 367       __asm__ volatile ("xorps %xmm0, %xmm0");
 368       SetUnhandledExceptionFilter(exc_fil);
 369       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 370    }
 371 #elif defined(__OS2__)
 372    EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
 373    if ( gCpuCaps.hasSSE ) {
 374       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 375       DosSetExceptionHandler( &RegRec );
 376       __asm__ volatile ("xorps %xmm0, %xmm0");
 377       DosUnsetExceptionHandler( &RegRec );
 378       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 379    }
 380 #elif defined(__linux__)
 381 #if defined(_POSIX_SOURCE)
 382    struct sigaction saved_sigill;
 383
 384    /* Save the original signal handlers.
 385     */
 386    sigaction( SIGILL, NULL, &saved_sigill );
 387
 388    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 389
 390    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 391     * supports the extended FPU save and restore required for SSE.  If
 392     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 393     * doesn't support Streaming SIMD Exceptions, even if the processor
 394     * does.
 395     */
 396    if ( gCpuCaps.hasSSE ) {
 397       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 398
 399 //      __asm__ volatile ("xorps %%xmm0, %%xmm0");
 400       __asm__ volatile ("xorps %xmm0, %xmm0");
 401
 402       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 403    }
 404
 405    /* Restore the original signal handlers.
 406     */
 407    sigaction( SIGILL, &saved_sigill, NULL );
 408
 409    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 410     * safe to go ahead and hook out the SSE code throughout Mesa.
 411     */
 412    mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
 413 #else
 414    /* We can't use POSIX signal handling to test the availability of
 415     * SSE, so we disable it by default.
 416     */
 417    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 418    gCpuCaps.hasSSE=0;
 419 #endif /* _POSIX_SOURCE */
 420 #else
 421    /* Do nothing on other platforms for now.
 422     */
 423    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 424    gCpuCaps.hasSSE=0;
 425 #endif /* __linux__ */
 426 }
 427 #else /* ARCH_X86 */
 428
 429 #ifdef __APPLE__
 430 #include <sys/sysctl.h>
 431 #elif defined(__AMIGAOS4__)
 432 /* nothing */
 433 #else
 434 #include <signal.h>
 435 #include <setjmp.h>
 436
 437 static sigjmp_buf jmpbuf;
 438 static volatile sig_atomic_t canjump = 0;
 439
 440 static void sigill_handler (int sig)
 441 {
 442     if (!canjump) {
 443         signal (sig, SIG_DFL);
 444         raise (sig);
 445     }
 446
 447     canjump = 0;
 448     siglongjmp (jmpbuf, 1);
 449 }
 450 #endif /* __APPLE__ */
 451
 452 void GetCpuCaps( CpuCaps *caps)
 453 {
 454         caps->cpuType=0;
 455         caps->cpuModel=0;
 456         caps->cpuStepping=0;
 457         caps->hasMMX=0;
 458         caps->hasMMX2=0;
 459         caps->has3DNow=0;
 460         caps->has3DNowExt=0;
 461         caps->hasSSE=0;
 462         caps->hasSSE2=0;
 463         caps->hasSSE3=0;
 464         caps->hasSSSE3=0;
 465         caps->hasSSE4a=0;
 466         caps->isX86=0;
 467         caps->hasAltiVec = 0;
 468 #if HAVE_ALTIVEC
 469 #ifdef __APPLE__
 470 /*
 471   rip-off from ffmpeg altivec detection code.
 472   this code also appears on Apple's AltiVec pages.
 473  */
 474         {
 475                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 476                 int has_vu = 0;
 477                 size_t len = sizeof(has_vu);
 478                 int err;
 479
 480                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 481
 482                 if (err == 0)
 483                         if (has_vu != 0)
 484                                 caps->hasAltiVec = 1;
 485         }
 486 #elif defined(__AMIGAOS4__)
 487         ULONG result = 0;
 488
 489         GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 490         if (result == VECTORTYPE_ALTIVEC)
 491                 caps->hasAltiVec = 1;
 492 #else
 493 /* no Darwin, do it the brute-force way */
 494 /* this is borrowed from the libmpeg2 library */
 495         {
 496           signal (SIGILL, sigill_handler);
 497           if (sigsetjmp (jmpbuf, 1)) {
 498             signal (SIGILL, SIG_DFL);
 499           } else {
 500             canjump = 1;
 501
 502             __asm__ volatile ("mtspr 256, %0\n\t"
 503                           "vand %%v0, %%v0, %%v0"
 504                           :
 505                           : "r" (-1));
 506
 507             signal (SIGILL, SIG_DFL);
 508             caps->hasAltiVec = 1;
 509           }
 510         }
 511 #endif /* __APPLE__ */
 512         mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 513 #endif /* HAVE_ALTIVEC */
 514
 515 if (ARCH_IA64)
 516         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n");
 517
 518 if (ARCH_SPARC)
 519         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n");
 520
 521 if (ARCH_ARM)
 522         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n");
 523
 524 if (ARCH_PPC)
 525         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n");
 526
 527 if (ARCH_ALPHA)
 528         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n");
 529
 530 if (ARCH_MIPS)
 531         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: MIPS\n");
 532
 533 if (ARCH_PA_RISC)
 534         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n");
 535
 536 if (ARCH_S390)
 537         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n");
 538
 539 if (ARCH_S390X)
 540         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n");
 541
 542 if (ARCH_VAX)
 543         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" );
 544
 545 if (ARCH_XTENSA)
 546         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" );
 547 }
 548 #endif /* !ARCH_X86 */