cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #ifdef HAVE_MALLOC_H
   8 #include <malloc.h>
   9 #endif
  10 #include <stdlib.h>
  11
  12 #if defined(ARCH_X86) || defined(ARCH_X86_64)
  13
  14 #include <stdio.h>
  15 #include <string.h>
  16
  17 #if defined (__NetBSD__) || defined(__OpenBSD__)
  18 #include <sys/param.h>
  19 #include <sys/sysctl.h>
  20 #include <machine/cpu.h>
  21 #endif
  22
  23 #if defined(__FreeBSD__) || defined(__DragonFly__)
  24 #include <sys/types.h>
  25 #include <sys/sysctl.h>
  26 #endif
  27
  28 #ifdef __linux__
  29 #include <signal.h>
  30 #endif
  31
  32 #ifdef WIN32
  33 #include <windows.h>
  34 #endif
  35
  36 //#define X86_FXSR_MAGIC
  37 /* Thanks to the FreeBSD project for some of this cpuid code, and
  38  * help understanding how to use it.  Thanks to the Mesa
  39  * team for SSE support detection and more cpu detect code.
  40  */
  41
  42 /* I believe this code works.  However, it has only been used on a PII and PIII */
  43
  44 static void check_os_katmai_support( void );
  45
  46 #if 1
  47 // return TRUE if cpuid supported
  48 static int has_cpuid()
  49 {
  50         long a, c;
  51
  52 // code from libavcodec:
  53     __asm__ __volatile__ (
  54                           /* See if CPUID instruction is supported ... */
  55                           /* ... Get copies of EFLAGS into eax and ecx */
  56                           "pushf\n\t"
  57                           "pop %0\n\t"
  58                           "mov %0, %1\n\t"
  59
  60                           /* ... Toggle the ID bit in one copy and store */
  61                           /*     to the EFLAGS reg */
  62                           "xor $0x200000, %0\n\t"
  63                           "push %0\n\t"
  64                           "popf\n\t"
  65
  66                           /* ... Get the (hopefully modified) EFLAGS */
  67                           "pushf\n\t"
  68                           "pop %0\n\t"
  69                           : "=a" (a), "=c" (c)
  70                           :
  71                           : "cc"
  72                           );
  73
  74         return (a!=c);
  75 }
  76 #endif
  77
  78 static void
  79 do_cpuid(unsigned int ax, unsigned int *p)
  80 {
  81 #if 0
  82         __asm __volatile(
  83         "cpuid;"
  84         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  85         :  "0" (ax)
  86         );
  87 #else
  88 // code from libavcodec:
  89     __asm __volatile
  90         ("mov %%"REG_b", %%"REG_S"\n\t"
  91          "cpuid\n\t"
  92          "xchg %%"REG_b", %%"REG_S
  93          : "=a" (p[0]), "=S" (p[1]),
  94            "=c" (p[2]), "=d" (p[3])
  95          : "0" (ax));
  96 #endif
  97
  98 }
  99
 100 void GetCpuCaps( CpuCaps *caps)
 101 {
 102         unsigned int regs[4];
 103         unsigned int regs2[4];
 104
 105         memset(caps, 0, sizeof(*caps));
 106         caps->isX86=1;
 107         caps->cl_size=32; /* default */
 108         if (!has_cpuid()) {
 109             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 110             return;
 111         }
 112         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 113         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 114                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 115         if (regs[0]>=0x00000001)
 116         {
 117                 char *tmpstr;
 118                 unsigned cl_size;
 119
 120                 do_cpuid(0x00000001, regs2);
 121
 122                 caps->cpuType=(regs2[0] >> 8)&0xf;
 123                 if(caps->cpuType==0xf){
 124                     // use extended family (P4, IA64)
 125                     caps->cpuType=8+((regs2[0]>>20)&255);
 126                 }
 127                 caps->cpuStepping=regs2[0] & 0xf;
 128
 129                 // general feature flags:
 130                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 131                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 132                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 133                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 134                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 135                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 136                 if(cl_size) caps->cl_size = cl_size;
 137
 138                 tmpstr=GetCpuFriendlyName(regs, regs2);
 139                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ",tmpstr);
 140                 free(tmpstr);
 141                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Stepping: %d)\n",
 142                     caps->cpuType, caps->cpuStepping);
 143
 144         }
 145         do_cpuid(0x80000000, regs);
 146         if (regs[0]>=0x80000001) {
 147                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 148                 do_cpuid(0x80000001, regs2);
 149                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 150                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 151                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 152                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 153         }
 154         if(regs[0]>=0x80000006)
 155         {
 156                 do_cpuid(0x80000006, regs2);
 157                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 158                 caps->cl_size  = regs2[2] & 0xFF;
 159         }
 160         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"Detected cache-line size is %u bytes\n",caps->cl_size);
 161 #if 0
 162         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 163                 gCpuCaps.hasMMX,
 164                 gCpuCaps.hasMMX2,
 165                 gCpuCaps.hasSSE,
 166                 gCpuCaps.hasSSE2,
 167                 gCpuCaps.has3DNow,
 168                 gCpuCaps.has3DNowExt );
 169 #endif
 170
 171                 /* FIXME: Does SSE2 need more OS support, too? */
 172 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__CYGWIN__) || defined(__OpenBSD__) || defined(__DragonFly__)
 173                 if (caps->hasSSE)
 174                         check_os_katmai_support();
 175                 if (!caps->hasSSE)
 176                         caps->hasSSE2 = 0;
 177 #else
 178                 caps->hasSSE=0;
 179                 caps->hasSSE2 = 0;
 180 #endif
 181 //              caps->has3DNow=1;
 182 //              caps->hasMMX2 = 0;
 183 //              caps->hasMMX = 0;
 184
 185 #ifndef HAVE_MMX
 186         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 187         caps->hasMMX=0;
 188 #endif
 189 #ifndef HAVE_MMX2
 190         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 191         caps->hasMMX2=0;
 192 #endif
 193 #ifndef HAVE_SSE
 194         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 195         caps->hasSSE=0;
 196 #endif
 197 #ifndef HAVE_SSE2
 198         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 199         caps->hasSSE2=0;
 200 #endif
 201 #ifndef HAVE_3DNOW
 202         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 203         caps->has3DNow=0;
 204 #endif
 205 #ifndef HAVE_3DNOWEX
 206         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 207         caps->has3DNowExt=0;
 208 #endif
 209 }
 210
 211
 212 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
 213 #define CPUID_EXTMODEL  ((regs2[0] >> 16)&0x0F) /* 19..16 */
 214 #define CPUID_TYPE              ((regs2[0] >> 12)&0x04) /* 13..12 */
 215 #define CPUID_FAMILY    ((regs2[0] >>  8)&0x0F) /* 11..08 */
 216 #define CPUID_MODEL             ((regs2[0] >>  4)&0x0F) /* 07..04 */
 217 #define CPUID_STEPPING  ((regs2[0] >>  0)&0x0F) /* 03..00 */
 218
 219 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 220 #include "cputable.h" /* get cpuname and cpuvendors */
 221         char vendor[17];
 222         char *retname;
 223         int i;
 224
 225         if (NULL==(retname=(char*)malloc(256))) {
 226                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 227                 exit(1);
 228         }
 229
 230         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 231
 232         for(i=0; i<MAX_VENDORS; i++){
 233                 if(!strcmp(cpuvendors[i].string,vendor)){
 234                         if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
 235                                 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
 236                         } else {
 237                                 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
 238                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name);
 239                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor:   %s\n",cpuvendors[i].string);
 240                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type:     %d\n",CPUID_TYPE);
 241                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family:   %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
 242                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model:    %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
 243                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING);
 244                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name"
 245                                        "to the MPlayer-Developers, so we can add it to the list!\n");
 246                         }
 247                 }
 248         }
 249         retname[255] = 0;
 250
 251         //printf("Detected CPU: %s\n", retname);
 252         return retname;
 253 }
 254
 255 #undef CPUID_EXTFAMILY
 256 #undef CPUID_EXTMODEL
 257 #undef CPUID_TYPE
 258 #undef CPUID_FAMILY
 259 #undef CPUID_MODEL
 260 #undef CPUID_STEPPING
 261
 262
 263 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 264 static void sigill_handler_sse( int signal, struct sigcontext sc )
 265 {
 266    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 267
 268    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 269     * instructions are 3 bytes long.  We must increment the instruction
 270     * pointer manually to avoid repeated execution of the offending
 271     * instruction.
 272     *
 273     * If the SIGILL is caused by a divide-by-zero when unmasked
 274     * exceptions aren't supported, the SIMD FPU status and control
 275     * word will be restored at the end of the test, so we don't need
 276     * to worry about doing it here.  Besides, we may not be able to...
 277     */
 278    sc.eip += 3;
 279
 280    gCpuCaps.hasSSE=0;
 281 }
 282
 283 static void sigfpe_handler_sse( int signal, struct sigcontext sc )
 284 {
 285    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " );
 286
 287    if ( sc.fpstate->magic != 0xffff ) {
 288       /* Our signal context has the extended FPU state, so reset the
 289        * divide-by-zero exception mask and clear the divide-by-zero
 290        * exception bit.
 291        */
 292       sc.fpstate->mxcsr |= 0x00000200;
 293       sc.fpstate->mxcsr &= 0xfffffffb;
 294    } else {
 295       /* If we ever get here, we're completely hosed.
 296        */
 297       mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" );
 298       mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" );
 299    }
 300 }
 301 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
 302
 303 #ifdef WIN32
 304 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 305 {
 306    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 307       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 308       ep->ContextRecord->Eip +=3;
 309       gCpuCaps.hasSSE=0;
 310           return EXCEPTION_CONTINUE_EXECUTION;
 311    }
 312    return EXCEPTION_CONTINUE_SEARCH;
 313 }
 314 #endif /* WIN32 */
 315
 316 /* If we're running on a processor that can do SSE, let's see if we
 317  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 318  * haven't been configured for a Pentium III but are running on one,
 319  * and RedHat patched 2.2 kernels that have broken exception handling
 320  * support for user space apps that do SSE.
 321  */
 322 static void check_os_katmai_support( void )
 323 {
 324 #ifdef ARCH_X86_64
 325    gCpuCaps.hasSSE=1;
 326    gCpuCaps.hasSSE2=1;
 327 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 328    int has_sse=0, ret;
 329    size_t len=sizeof(has_sse);
 330
 331    ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0);
 332    if (ret || !has_sse)
 333       gCpuCaps.hasSSE=0;
 334
 335 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 336 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 337    int has_sse, has_sse2, ret, mib[2];
 338    size_t varlen;
 339
 340    mib[0] = CTL_MACHDEP;
 341    mib[1] = CPU_SSE;
 342    varlen = sizeof(has_sse);
 343
 344    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 345    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 346    if (ret < 0 || !has_sse) {
 347       gCpuCaps.hasSSE=0;
 348       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 349    } else {
 350       gCpuCaps.hasSSE=1;
 351       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 352    }
 353
 354    mib[1] = CPU_SSE2;
 355    varlen = sizeof(has_sse2);
 356    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 357    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 358    if (ret < 0 || !has_sse2) {
 359       gCpuCaps.hasSSE2=0;
 360       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 361    } else {
 362       gCpuCaps.hasSSE2=1;
 363       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 364    }
 365 #else
 366    gCpuCaps.hasSSE = 0;
 367    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 368 #endif
 369 #elif defined(WIN32)
 370    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 371    if ( gCpuCaps.hasSSE ) {
 372       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 373       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 374       __asm __volatile ("xorps %xmm0, %xmm0");
 375       SetUnhandledExceptionFilter(exc_fil);
 376       if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 377       else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 378    }
 379 #elif defined(__linux__)
 380 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 381    struct sigaction saved_sigill;
 382    struct sigaction saved_sigfpe;
 383
 384    /* Save the original signal handlers.
 385     */
 386    sigaction( SIGILL, NULL, &saved_sigill );
 387    sigaction( SIGFPE, NULL, &saved_sigfpe );
 388
 389    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 390    signal( SIGFPE, (void (*)(int))sigfpe_handler_sse );
 391
 392    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 393     * supports the extended FPU save and restore required for SSE.  If
 394     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 395     * doesn't support Streaming SIMD Exceptions, even if the processor
 396     * does.
 397     */
 398    if ( gCpuCaps.hasSSE ) {
 399       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 400
 401 //      __asm __volatile ("xorps %%xmm0, %%xmm0");
 402       __asm __volatile ("xorps %xmm0, %xmm0");
 403
 404       if ( gCpuCaps.hasSSE ) {
 405          mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 406       } else {
 407          mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 408       }
 409    }
 410
 411    /* Emulate test for OSXMMEXCPT in CR4.  The OS will set this bit if
 412     * it supports unmasked SIMD FPU exceptions.  If we unmask the
 413     * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
 414     * doesn't support unmasked SIMD FPU exceptions.  If we get a SIGFPE
 415     * as expected, we're okay but we need to clean up after it.
 416     *
 417     * Are we being too stringent in our requirement that the OS support
 418     * unmasked exceptions?  Certain RedHat 2.2 kernels enable SSE by
 419     * setting CR4.OSFXSR but don't support unmasked exceptions.  Win98
 420     * doesn't even support them.  We at least know the user-space SSE
 421     * support is good in kernels that do support unmasked exceptions,
 422     * and therefore to be safe I'm going to leave this test in here.
 423     */
 424    if ( gCpuCaps.hasSSE ) {
 425       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " );
 426
 427 //      test_os_katmai_exception_support();
 428
 429       if ( gCpuCaps.hasSSE ) {
 430          mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 431       } else {
 432          mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 433       }
 434    }
 435
 436    /* Restore the original signal handlers.
 437     */
 438    sigaction( SIGILL, &saved_sigill, NULL );
 439    sigaction( SIGFPE, &saved_sigfpe, NULL );
 440
 441    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 442     * safe to go ahead and hook out the SSE code throughout Mesa.
 443     */
 444    if ( gCpuCaps.hasSSE ) {
 445       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" );
 446    } else {
 447       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" );
 448    }
 449 #else
 450    /* We can't use POSIX signal handling to test the availability of
 451     * SSE, so we disable it by default.
 452     */
 453    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 454    gCpuCaps.hasSSE=0;
 455 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
 456 #else
 457    /* Do nothing on other platforms for now.
 458     */
 459    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 460    gCpuCaps.hasSSE=0;
 461 #endif /* __linux__ */
 462 }
 463 #else /* ARCH_X86 || ARCH_X86_64 */
 464
 465 #ifdef SYS_DARWIN
 466 #include <sys/sysctl.h>
 467 #else
 468 #include <signal.h>
 469 #include <setjmp.h>
 470
 471 static sigjmp_buf jmpbuf;
 472 static volatile sig_atomic_t canjump = 0;
 473
 474 static void sigill_handler (int sig)
 475 {
 476     if (!canjump) {
 477         signal (sig, SIG_DFL);
 478         raise (sig);
 479     }
 480
 481     canjump = 0;
 482     siglongjmp (jmpbuf, 1);
 483 }
 484 #endif
 485
 486 void GetCpuCaps( CpuCaps *caps)
 487 {
 488         caps->cpuType=0;
 489         caps->cpuStepping=0;
 490         caps->hasMMX=0;
 491         caps->hasMMX2=0;
 492         caps->has3DNow=0;
 493         caps->has3DNowExt=0;
 494         caps->hasSSE=0;
 495         caps->hasSSE2=0;
 496         caps->isX86=0;
 497         caps->hasAltiVec = 0;
 498 #ifdef HAVE_ALTIVEC
 499 #ifdef SYS_DARWIN
 500 /*
 501   rip-off from ffmpeg altivec detection code.
 502   this code also appears on Apple's AltiVec pages.
 503  */
 504         {
 505                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 506                 int has_vu = 0;
 507                 size_t len = sizeof(has_vu);
 508                 int err;
 509
 510                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 511
 512                 if (err == 0)
 513                         if (has_vu != 0)
 514                                 caps->hasAltiVec = 1;
 515         }
 516 #else /* SYS_DARWIN */
 517 /* no Darwin, do it the brute-force way */
 518 /* this is borrowed from the libmpeg2 library */
 519         {
 520           signal (SIGILL, sigill_handler);
 521           if (sigsetjmp (jmpbuf, 1)) {
 522             signal (SIGILL, SIG_DFL);
 523           } else {
 524             canjump = 1;
 525
 526             asm volatile ("mtspr 256, %0\n\t"
 527                           "vand %%v0, %%v0, %%v0"
 528                           :
 529                           : "r" (-1));
 530
 531             signal (SIGILL, SIG_DFL);
 532             caps->hasAltiVec = 1;
 533           }
 534         }
 535 #endif /* SYS_DARWIN */
 536         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 537 #endif /* HAVE_ALTIVEC */
 538
 539 #ifdef ARCH_IA64
 540         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n");
 541 #endif
 542
 543 #ifdef ARCH_SPARC
 544         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n");
 545 #endif
 546
 547 #ifdef ARCH_ARMV4L
 548         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n");
 549 #endif
 550
 551 #ifdef ARCH_POWERPC
 552         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n");
 553 #endif
 554
 555 #ifdef ARCH_ALPHA
 556         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n");
 557 #endif
 558
 559 #ifdef ARCH_SGI_MIPS
 560         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n");
 561 #endif
 562
 563 #ifdef ARCH_PA_RISC
 564         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n");
 565 #endif
 566
 567 #ifdef ARCH_S390
 568         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n");
 569 #endif
 570
 571 #ifdef ARCH_S390X
 572         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n");
 573 #endif
 574
 575 #ifdef ARCH_VAX
 576         mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" );
 577 #endif
 578 }
 579 #endif /* !ARCH_X86 */