vidix/mach64.h

   1 /*
   2  * VIDIX driver for ATI Mach64 and 3DRage chipsets.
   3  *
   4  * Copyright (C) 2002 Nick Kurshev
   5  * This file is based on sources from
   6  *  radeonfb, GATOS (gatos.sf.net) and X11 (www.xfree86.org)
   7  *
   8  * This file is part of MPlayer.
   9  *
  10  * MPlayer is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * MPlayer is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with MPlayer; if not, write to the Free Software Foundation, Inc.,
  22  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  23  */
  24
  25 #ifndef MPLAYER_MACH64_H
  26 #define MPLAYER_MACH64_H
  27
  28 /* Note: this model of accessing to IO space is based on MMIO technology.
  29 This means that this sources don't support ISA and VLB cards */
  30 #define BlockIOTag(val) (val)
  31 #define IOPortTag(sparce,val) (val)
  32
  33 /* MDA/[M]CGA/EGA/VGA I/O ports */
  34 #define GENVS                   0x0102u         /* Write (and Read on uC only) */
  35
  36 #define R_GENLPS                0x03b9u         /* Read */
  37
  38 #define GENHP                   0x03bfu
  39
  40 #define ATTRX                   0x03c0u
  41 #define ATTRD                   0x03c1u
  42 #define GENS0                   0x03c2u         /* Read */
  43 #define GENMO                   0x03c2u         /* Write */
  44 #define GENENB                  0x03c3u         /* Read */
  45 #define SEQX                    0x03c4u
  46 #define SEQD                    0x03c5u
  47 #define VGA_DAC_MASK            0x03c6u
  48 #define VGA_DAC_READ            0x03c7u
  49 #define VGA_DAC_WRITE           0x03c8u
  50 #define VGA_DAC_DATA            0x03c9u
  51 #define R_GENFC                 0x03cau         /* Read */
  52 /*      ?                       0x03cbu */
  53 #define R_GENMO                 0x03ccu         /* Read */
  54 /*      ?                       0x03cdu */
  55 #define GRAX                    0x03ceu
  56 #define GRAD                    0x03cfu
  57
  58 #define GENB                    0x03d9u
  59
  60 #define GENLPS                  0x03dcu         /* Write */
  61 #define KCX                     0x03ddu
  62 #define KCD                     0x03deu
  63
  64 #define GENENA                  0x46e8u         /* Write */
  65
  66 /* I/O port base numbers */
  67 #define MonochromeIOBase        0x03b0u
  68 #define ColourIOBase            0x03d0u
  69
  70 /* Other MDA/[M]CGA/EGA/VGA I/O ports */
  71 /*      ?(_IOBase)              ((_IOBase) + 0x00u) */  /* CRTX synonym */
  72 /*      ?(_IOBase)              ((_IOBase) + 0x01u) */  /* CRTD synonym */
  73 /*      ?(_IOBase)              ((_IOBase) + 0x02u) */  /* CRTX synonym */
  74 /*      ?(_IOBase)              ((_IOBase) + 0x03u) */  /* CRTD synonym */
  75 #define CRTX(_IOBase)           ((_IOBase) + 0x04u)
  76 #define CRTD(_IOBase)           ((_IOBase) + 0x05u)
  77 /*      ?(_IOBase)              ((_IOBase) + 0x06u) */
  78 /*      ?(_IOBase)              ((_IOBase) + 0x07u) */
  79 #define GENMC(_IOBase)          ((_IOBase) + 0x08u)
  80 /*      ?(_IOBase)              ((_IOBase) + 0x09u) */  /* R_GENLPS/GENB */
  81 #define GENS1(_IOBase)          ((_IOBase) + 0x0au)     /* Read */
  82 #define GENFC(_IOBase)          ((_IOBase) + 0x0au)     /* Write */
  83 #define GENLPC(_IOBase)         ((_IOBase) + 0x0bu)
  84 /*      ?(_IOBase)              ((_IOBase) + 0x0cu) */  /* /GENLPS */
  85 /*      ?(_IOBase)              ((_IOBase) + 0x0du) */  /* /KCX */
  86 /*      ?(_IOBase)              ((_IOBase) + 0x0eu) */  /* /KCD */
  87 /*      ?(_IOBase)              ((_IOBase) + 0x0fu) */  /* GENHP/ */
  88
  89 /* 8514/A VESA approved register definitions */
  90 #define DISP_STAT               0x02e8u         /* Read */
  91 #define SENSE                           0x0001u /* Presumably belong here */
  92 #define VBLANK                          0x0002u
  93 #define HORTOG                          0x0004u
  94 #define H_TOTAL                 0x02e8u         /* Write */
  95 #define IBM_DAC_MASK            0x02eau
  96 #define IBM_DAC_READ            0x02ebu
  97 #define IBM_DAC_WRITE           0x02ecu
  98 #define IBM_DAC_DATA            0x02edu
  99 #define H_DISP                  0x06e8u         /* Write */
 100 #define H_SYNC_STRT             0x0ae8u         /* Write */
 101 #define H_SYNC_WID              0x0ee8u         /* Write */
 102 #define HSYNCPOL_POS                    0x0000u
 103 #define HSYNCPOL_NEG                    0x0020u
 104 #define H_POLARITY_POS                  HSYNCPOL_POS    /* Sigh */
 105 #define H_POLARITY_NEG                  HSYNCPOL_NEG    /* Sigh */
 106 #define V_TOTAL                 0x12e8u         /* Write */
 107 #define V_DISP                  0x16e8u         /* Write */
 108 #define V_SYNC_STRT             0x1ae8u         /* Write */
 109 #define V_SYNC_WID              0x1ee8u         /* Write */
 110 #define VSYNCPOL_POS                    0x0000u
 111 #define VSYNCPOL_NEG                    0x0020u
 112 #define V_POLARITY_POS                  VSYNCPOL_POS    /* Sigh */
 113 #define V_POLARITY_NEG                  VSYNCPOL_NEG    /* Sigh */
 114 #define DISP_CNTL               0x22e8u         /* Write */
 115 #define ODDBNKENAB                      0x0001u
 116 #define MEMCFG_2                        0x0000u
 117 #define MEMCFG_4                        0x0002u
 118 #define MEMCFG_6                        0x0004u
 119 #define MEMCFG_8                        0x0006u
 120 #define DBLSCAN                         0x0008u
 121 #define INTERLACE                       0x0010u
 122 #define DISPEN_NC                       0x0000u
 123 #define DISPEN_ENAB                     0x0020u
 124 #define DISPEN_DISAB                    0x0040u
 125 #define R_H_TOTAL               0x26e8u         /* Read */
 126 /*      ?                       0x2ae8u */
 127 /*      ?                       0x2ee8u */
 128 /*      ?                       0x32e8u */
 129 /*      ?                       0x36e8u */
 130 /*      ?                       0x3ae8u */
 131 /*      ?                       0x3ee8u */
 132 #define SUBSYS_STAT             0x42e8u         /* Read */
 133 #define VBLNKFLG                        0x0001u
 134 #define PICKFLAG                        0x0002u
 135 #define INVALIDIO                       0x0004u
 136 #define GPIDLE                          0x0008u
 137 #define MONITORID_MASK                  0x0070u
 138 /*      MONITORID_?                             0x0000u */
 139 #define MONITORID_8507                          0x0010u
 140 #define MONITORID_8514                          0x0020u
 141 /*      MONITORID_?                             0x0030u */
 142 /*      MONITORID_?                             0x0040u */
 143 #define MONITORID_8503                          0x0050u
 144 #define MONITORID_8512                          0x0060u
 145 #define MONITORID_8513                          0x0060u
 146 #define MONITORID_NONE                          0x0070u
 147 #define _8PLANE                         0x0080u
 148 #define SUBSYS_CNTL             0x42e8u         /* Write */
 149 #define RVBLNKFLG                       0x0001u
 150 #define RPICKFLAG                       0x0002u
 151 #define RINVALIDIO                      0x0004u
 152 #define RGPIDLE                         0x0008u
 153 #define IVBLNKFLG                       0x0100u
 154 #define IPICKFLAG                       0x0200u
 155 #define IINVALIDIO                      0x0400u
 156 #define IGPIDLE                         0x0800u
 157 #define CHPTEST_NC                      0x0000u
 158 #define CHPTEST_NORMAL                  0x1000u
 159 #define CHPTEST_ENAB                    0x2000u
 160 #define GPCTRL_NC                       0x0000u
 161 #define GPCTRL_ENAB                     0x4000u
 162 #define GPCTRL_RESET                    0x8000u
 163 #define ROM_PAGE_SEL            0x46e8u         /* Write */
 164 #define ADVFUNC_CNTL            0x4ae8u         /* Write */
 165 #define DISABPASSTHRU                   0x0001u
 166 #define CLOKSEL                         0x0004u
 167 /*      ?                       0x4ee8u */
 168 #define EXT_CONFIG_0            0x52e8u         /* C & T 82C480 */
 169 #define EXT_CONFIG_1            0x56e8u         /* C & T 82C480 */
 170 #define EXT_CONFIG_2            0x5ae8u         /* C & T 82C480 */
 171 #define EXT_CONFIG_3            0x5ee8u         /* C & T 82C480 */
 172 /*      ?                       0x62e8u */
 173 /*      ?                       0x66e8u */
 174 /*      ?                       0x6ae8u */
 175 /*      ?                       0x6ee8u */
 176 /*      ?                       0x72e8u */
 177 /*      ?                       0x76e8u */
 178 /*      ?                       0x7ae8u */
 179 /*      ?                       0x7ee8u */
 180 #define CUR_Y                   0x82e8u
 181 #define CUR_X                   0x86e8u
 182 #define DESTY_AXSTP             0x8ae8u         /* Write */
 183 #define DESTX_DIASTP            0x8ee8u         /* Write */
 184 #define ERR_TERM                0x92e8u
 185 #define MAJ_AXIS_PCNT           0x96e8u         /* Write */
 186 #define GP_STAT                 0x9ae8u         /* Read */
 187 #define GE_STAT                 0x9ae8u         /* Alias */
 188 #define DATARDY                         0x0100u
 189 #define DATA_READY                      DATARDY /* Alias */
 190 #define GPBUSY                          0x0200u
 191 #define CMD                     0x9ae8u         /* Write */
 192 #define WRTDATA                         0x0001u
 193 #define PLANAR                          0x0002u
 194 #define LASTPIX                         0x0004u
 195 #define LINETYPE                        0x0008u
 196 #define DRAW                            0x0010u
 197 #define INC_X                           0x0020u
 198 #define YMAJAXIS                        0x0040u
 199 #define INC_Y                           0x0080u
 200 #define PCDATA                          0x0100u
 201 #define _16BIT                          0x0200u
 202 #define CMD_NOP                         0x0000u
 203 #define CMD_OP_MSK                      0xf000u
 204 #define BYTSEQ                                  0x1000u
 205 #define CMD_LINE                                0x2000u
 206 #define CMD_RECT                                0x4000u
 207 #define CMD_RECTV1                              0x6000u
 208 #define CMD_RECTV2                              0x8000u
 209 #define CMD_LINEAF                              0xa000u
 210 #define CMD_BITBLT                              0xc000u
 211 #define SHORT_STROKE            0x9ee8u         /* Write */
 212 #define SSVDRAW                         0x0010u
 213 #define VECDIR_000                      0x0000u
 214 #define VECDIR_045                      0x0020u
 215 #define VECDIR_090                      0x0040u
 216 #define VECDIR_135                      0x0060u
 217 #define VECDIR_180                      0x0080u
 218 #define VECDIR_225                      0x00a0u
 219 #define VECDIR_270                      0x00c0u
 220 #define VECDIR_315                      0x00e0u
 221 #define BKGD_COLOR              0xa2e8u         /* Write */
 222 #define FRGD_COLOR              0xa6e8u         /* Write */
 223 #define WRT_MASK                0xaae8u         /* Write */
 224 #define RD_MASK                 0xaee8u         /* Write */
 225 #define COLOR_CMP               0xb2e8u         /* Write */
 226 #define BKGD_MIX                0xb6e8u         /* Write */
 227 /*                                      0x001fu See MIX_* definitions below */
 228 #define BSS_BKGDCOL                     0x0000u
 229 #define BSS_FRGDCOL                     0x0020u
 230 #define BSS_PCDATA                      0x0040u
 231 #define BSS_BITBLT                      0x0060u
 232 #define FRGD_MIX                0xbae8u         /* Write */
 233 /*                                      0x001fu See MIX_* definitions below */
 234 #define FSS_BKGDCOL                     0x0000u
 235 #define FSS_FRGDCOL                     0x0020u
 236 #define FSS_PCDATA                      0x0040u
 237 #define FSS_BITBLT                      0x0060u
 238 #define MULTIFUNC_CNTL          0xbee8u         /* Write */
 239 #define MIN_AXIS_PCNT                   0x0000u
 240 #define SCISSORS_T                      0x1000u
 241 #define SCISSORS_L                      0x2000u
 242 #define SCISSORS_B                      0x3000u
 243 #define SCISSORS_R                      0x4000u
 244 #define M32_MEM_CNTL                    0x5000u
 245 #define HORCFG_4                                0x0000u
 246 #define HORCFG_5                                0x0001u
 247 #define HORCFG_8                                0x0002u
 248 #define HORCFG_10                               0x0003u
 249 #define VRTCFG_2                                0x0000u
 250 #define VRTCFG_4                                0x0004u
 251 #define VRTCFG_6                                0x0008u
 252 #define VRTCFG_8                                0x000cu
 253 #define BUFSWP                                  0x0010u
 254 #define PATTERN_L                       0x8000u
 255 #define PATTERN_H                       0x9000u
 256 #define PIX_CNTL                        0xa000u
 257 #define PLANEMODE                               0x0004u
 258 #define COLCMPOP_F                              0x0000u
 259 #define COLCMPOP_T                              0x0008u
 260 #define COLCMPOP_GE                             0x0010u
 261 #define COLCMPOP_LT                             0x0018u
 262 #define COLCMPOP_NE                             0x0020u
 263 #define COLCMPOP_EQ                             0x0028u
 264 #define COLCMPOP_LE                             0x0030u
 265 #define COLCMPOP_GT                             0x0038u
 266 #define MIXSEL_FRGDMIX                          0x0000u
 267 #define MIXSEL_PATT                             0x0040u
 268 #define MIXSEL_EXPPC                            0x0080u
 269 #define MIXSEL_EXPBLT                           0x00c0u
 270 /*      ?                       0xc2e8u */
 271 /*      ?                       0xc6e8u */
 272 /*      ?                       0xcae8u */
 273 /*      ?                       0xcee8u */
 274 /*      ?                       0xd2e8u */
 275 /*      ?                       0xd6e8u */
 276 /*      ?                       0xdae8u */
 277 /*      ?                       0xdee8u */
 278 #define PIX_TRANS               0xe2e8u
 279 /*      ?                       0xe6e8u */
 280 /*      ?                       0xeae8u */
 281 /*      ?                       0xeee8u */
 282 /*      ?                       0xf2e8u */
 283 /*      ?                       0xf6e8u */
 284 /*      ?                       0xfae8u */
 285 /*      ?                       0xfee8u */
 286
 287 /* ATI Mach8 & Mach32 register definitions */
 288 #define OVERSCAN_COLOR_8        0x02eeu         /* Write */     /* Mach32 */
 289 #define OVERSCAN_BLUE_24        0x02efu         /* Write */     /* Mach32 */
 290 #define OVERSCAN_GREEN_24       0x06eeu         /* Write */     /* Mach32 */
 291 #define OVERSCAN_RED_24         0x06efu         /* Write */     /* Mach32 */
 292 #define CURSOR_OFFSET_LO        0x0aeeu         /* Write */     /* Mach32 */
 293 #define CURSOR_OFFSET_HI        0x0eeeu         /* Write */     /* Mach32 */
 294 #define CONFIG_STATUS_1         0x12eeu         /* Read */
 295 #define CLK_MODE                        0x0001u                 /* Mach8 */
 296 #define BUS_16                          0x0002u                 /* Mach8 */
 297 #define MC_BUS                          0x0004u                 /* Mach8 */
 298 #define EEPROM_ENA                      0x0008u                 /* Mach8 */
 299 #define DRAM_ENA                        0x0010u                 /* Mach8 */
 300 #define MEM_INSTALLED                   0x0060u                 /* Mach8 */
 301 #define ROM_ENA                         0x0080u                 /* Mach8 */
 302 #define ROM_PAGE_ENA                    0x0100u                 /* Mach8 */
 303 #define ROM_LOCATION                    0xfe00u                 /* Mach8 */
 304 #define _8514_ONLY                      0x0001u                 /* Mach32 */
 305 #define BUS_TYPE                        0x000eu                 /* Mach32 */
 306 #define ISA_16_BIT                              0x0000u         /* Mach32 */
 307 #define EISA                                    0x0002u         /* Mach32 */
 308 #define MICRO_C_16_BIT                          0x0004u         /* Mach32 */
 309 #define MICRO_C_8_BIT                           0x0006u         /* Mach32 */
 310 #define LOCAL_386SX                             0x0008u         /* Mach32 */
 311 #define LOCAL_386DX                             0x000au         /* Mach32 */
 312 #define LOCAL_486                               0x000cu         /* Mach32 */
 313 #define PCI                                     0x000eu         /* Mach32 */
 314 #define MEM_TYPE                        0x0070u                 /* Mach32 */
 315 #define CHIP_DIS                        0x0080u                 /* Mach32 */
 316 #define TST_VCTR_ENA                    0x0100u                 /* Mach32 */
 317 #define DACTYPE                         0x0e00u                 /* Mach32 */
 318 #define MC_ADR_DECODE                   0x1000u                 /* Mach32 */
 319 #define CARD_ID                         0xe000u                 /* Mach32 */
 320 #define HORZ_CURSOR_POSN        0x12eeu         /* Write */     /* Mach32 */
 321 #define CONFIG_STATUS_2         0x16eeu         /* Read */
 322 #define SHARE_CLOCK                     0x0001u                 /* Mach8 */
 323 #define HIRES_BOOT                      0x0002u                 /* Mach8 */
 324 #define EPROM_16_ENA                    0x0004u                 /* Mach8 */
 325 #define WRITE_PER_BIT                   0x0008u                 /* Mach8 */
 326 #define FLASH_ENA                       0x0010u                 /* Mach8 */
 327 #define SLOW_SEQ_EN                     0x0001u                 /* Mach32 */
 328 #define MEM_ADDR_DIS                    0x0002u                 /* Mach32 */
 329 #define ISA_16_ENA                      0x0004u                 /* Mach32 */
 330 #define KOR_TXT_MODE_ENA                0x0008u                 /* Mach32 */
 331 #define LOCAL_BUS_SUPPORT               0x0030u                 /* Mach32 */
 332 #define LOCAL_BUS_CONFIG_2              0x0040u                 /* Mach32 */
 333 #define LOCAL_BUS_RD_DLY_ENA            0x0080u                 /* Mach32 */
 334 #define LOCAL_DAC_EN                    0x0100u                 /* Mach32 */
 335 #define LOCAL_RDY_EN                    0x0200u                 /* Mach32 */
 336 #define EEPROM_ADR_SEL                  0x0400u                 /* Mach32 */
 337 #define GE_STRAP_SEL                    0x0800u                 /* Mach32 */
 338 #define VESA_RDY                        0x1000u                 /* Mach32 */
 339 #define Z4GB                            0x2000u                 /* Mach32 */
 340 #define LOC2_MDRAM                      0x4000u                 /* Mach32 */
 341 #define VERT_CURSOR_POSN        0x16eeu         /* Write */     /* Mach32 */
 342 #define FIFO_TEST_DATA          0x1aeeu         /* Read */      /* Mach32 */
 343 #define CURSOR_COLOR_0          0x1aeeu         /* Write */     /* Mach32 */
 344 #define CURSOR_COLOR_1          0x1aefu         /* Write */     /* Mach32 */
 345 #define HORZ_CURSOR_OFFSET      0x1eeeu         /* Write */     /* Mach32 */
 346 #define VERT_CURSOR_OFFSET      0x1eefu         /* Write */     /* Mach32 */
 347 #define PCI_CNTL                0x22eeu                         /* Mach32-PCI */
 348 #define CRT_PITCH               0x26eeu         /* Write */
 349 #define CRT_OFFSET_LO           0x2aeeu         /* Write */
 350 #define CRT_OFFSET_HI           0x2eeeu         /* Write */
 351 #define LOCAL_CNTL              0x32eeu                         /* Mach32 */
 352 #define FIFO_OPT                0x36eeu         /* Write */     /* Mach8 */
 353 #define MISC_OPTIONS            0x36eeu                         /* Mach32 */
 354 #define W_STATE_ENA                     0x0000u                 /* Mach32 */
 355 #define HOST_8_ENA                      0x0001u                 /* Mach32 */
 356 #define MEM_SIZE_ALIAS                  0x000cu                 /* Mach32 */
 357 #define MEM_SIZE_512K                           0x0000u         /* Mach32 */
 358 #define MEM_SIZE_1M                             0x0004u         /* Mach32 */
 359 #define MEM_SIZE_2M                             0x0008u         /* Mach32 */
 360 #define MEM_SIZE_4M                             0x000cu         /* Mach32 */
 361 #define DISABLE_VGA                     0x0010u                 /* Mach32 */
 362 #define _16_BIT_IO                      0x0020u                 /* Mach32 */
 363 #define DISABLE_DAC                     0x0040u                 /* Mach32 */
 364 #define DLY_LATCH_ENA                   0x0080u                 /* Mach32 */
 365 #define TEST_MODE                       0x0100u                 /* Mach32 */
 366 #define BLK_WR_ENA                      0x0400u                 /* Mach32 */
 367 #define _64_DRAW_ENA                    0x0800u                 /* Mach32 */
 368 #define FIFO_TEST_TAG           0x3aeeu         /* Read */      /* Mach32 */
 369 #define EXT_CURSOR_COLOR_0      0x3aeeu         /* Write */     /* Mach32 */
 370 #define EXT_CURSOR_COLOR_1      0x3eeeu         /* Write */     /* Mach32 */
 371 #define MEM_BNDRY               0x42eeu                         /* Mach32 */
 372 #define MEM_PAGE_BNDRY                  0x000fu                 /* Mach32 */
 373 #define MEM_BNDRY_ENA                   0x0010u                 /* Mach32 */
 374 #define SHADOW_CTL              0x46eeu         /* Write */
 375 #define CLOCK_SEL               0x4aeeu
 376 /*      DISABPASSTHRU                   0x0001u See ADVFUNC_CNTL */
 377 #define VFIFO_DEPTH_1                   0x0100u                 /* Mach32 */
 378 #define VFIFO_DEPTH_2                   0x0200u                 /* Mach32 */
 379 #define VFIFO_DEPTH_3                   0x0300u                 /* Mach32 */
 380 #define VFIFO_DEPTH_4                   0x0400u                 /* Mach32 */
 381 #define VFIFO_DEPTH_5                   0x0500u                 /* Mach32 */
 382 #define VFIFO_DEPTH_6                   0x0600u                 /* Mach32 */
 383 #define VFIFO_DEPTH_7                   0x0700u                 /* Mach32 */
 384 #define VFIFO_DEPTH_8                   0x0800u                 /* Mach32 */
 385 #define VFIFO_DEPTH_9                   0x0900u                 /* Mach32 */
 386 #define VFIFO_DEPTH_A                   0x0a00u                 /* Mach32 */
 387 #define VFIFO_DEPTH_B                   0x0b00u                 /* Mach32 */
 388 #define VFIFO_DEPTH_C                   0x0c00u                 /* Mach32 */
 389 #define VFIFO_DEPTH_D                   0x0d00u                 /* Mach32 */
 390 #define VFIFO_DEPTH_E                   0x0e00u                 /* Mach32 */
 391 #define VFIFO_DEPTH_F                   0x0f00u                 /* Mach32 */
 392 #define COMPOSITE_SYNC                  0x1000u
 393 /*      ?                       0x4eeeu */
 394 #define ROM_ADDR_1              0x52eeu
 395 #define BIOS_BASE_SEGMENT               0x007fu                 /* Mach32 */
 396 /*      ?                               0xff80u */              /* Mach32 */
 397 #define ROM_ADDR_2              0x56eeu         /* Sick ... */
 398 #define SHADOW_SET              0x5aeeu         /* Write */
 399 #define MEM_CFG                 0x5eeeu                         /* Mach32 */
 400 #define MEM_APERT_SEL                   0x0003u                 /* Mach32 */
 401 #define MEM_APERT_PAGE                  0x000cu                 /* Mach32 */
 402 #define MEM_APERT_LOC                   0xfff0u                 /* Mach32 */
 403 #define EXT_GE_STATUS           0x62eeu         /* Read */      /* Mach32 */
 404 #define HORZ_OVERSCAN           0x62eeu         /* Write */     /* Mach32 */
 405 #define VERT_OVERSCAN           0x66eeu         /* Write */     /* Mach32 */
 406 #define MAX_WAITSTATES          0x6aeeu
 407 #define GE_OFFSET_LO            0x6eeeu         /* Write */
 408 #define BOUNDS_LEFT             0x72eeu         /* Read */
 409 #define GE_OFFSET_HI            0x72eeu         /* Write */
 410 #define BOUNDS_TOP              0x76eeu         /* Read */
 411 #define GE_PITCH                0x76eeu         /* Write */
 412 #define BOUNDS_RIGHT            0x7aeeu         /* Read */
 413 #define EXT_GE_CONFIG           0x7aeeu         /* Write */     /* Mach32 */
 414 #define MONITOR_ALIAS                   0x0007u                 /* Mach32 */
 415 /*      MONITOR_?                               0x0000u */      /* Mach32 */
 416 #define MONITOR_8507                            0x0001u         /* Mach32 */
 417 #define MONITOR_8514                            0x0002u         /* Mach32 */
 418 /*      MONITOR_?                               0x0003u */      /* Mach32 */
 419 /*      MONITOR_?                               0x0004u */      /* Mach32 */
 420 #define MONITOR_8503                            0x0005u         /* Mach32 */
 421 #define MONITOR_8512                            0x0006u         /* Mach32 */
 422 #define MONITOR_8513                            0x0006u         /* Mach32 */
 423 #define MONITOR_NONE                            0x0007u         /* Mach32 */
 424 #define ALIAS_ENA                       0x0008u                 /* Mach32 */
 425 #define PIXEL_WIDTH_4                   0x0000u                 /* Mach32 */
 426 #define PIXEL_WIDTH_8                   0x0010u                 /* Mach32 */
 427 #define PIXEL_WIDTH_16                  0x0020u                 /* Mach32 */
 428 #define PIXEL_WIDTH_24                  0x0030u                 /* Mach32 */
 429 #define RGB16_555                       0x0000u                 /* Mach32 */
 430 #define RGB16_565                       0x0040u                 /* Mach32 */
 431 #define RGB16_655                       0x0080u                 /* Mach32 */
 432 #define RGB16_664                       0x00c0u                 /* Mach32 */
 433 #define MULTIPLEX_PIXELS                0x0100u                 /* Mach32 */
 434 #define RGB24                           0x0000u                 /* Mach32 */
 435 #define RGBx24                          0x0200u                 /* Mach32 */
 436 #define BGR24                           0x0400u                 /* Mach32 */
 437 #define xBGR24                          0x0600u                 /* Mach32 */
 438 #define DAC_8_BIT_EN                    0x4000u                 /* Mach32 */
 439 #define ORDER_16BPP_565                 RGB16_565               /* Mach32 */
 440 #define BOUNDS_BOTTOM           0x7eeeu         /* Read */
 441 #define MISC_CNTL               0x7eeeu         /* Write */     /* Mach32 */
 442 #define PATT_DATA_INDEX         0x82eeu
 443 /*      ?                       0x86eeu */
 444 /*      ?                       0x8aeeu */
 445 #define R_EXT_GE_CONFIG         0x8eeeu         /* Read */      /* Mach32 */
 446 #define PATT_DATA               0x8eeeu         /* Write */
 447 #define R_MISC_CNTL             0x92eeu         /* Read */      /* Mach32 */
 448 #define BRES_COUNT              0x96eeu
 449 #define EXT_FIFO_STATUS         0x9aeeu         /* Read */
 450 #define LINEDRAW_INDEX          0x9aeeu         /* Write */
 451 /*      ?                       0x9eeeu */
 452 #define LINEDRAW_OPT            0xa2eeu
 453 #define BOUNDS_RESET                    0x0100u
 454 #define CLIP_MODE_0                     0x0000u /* Clip exception disabled */
 455 #define CLIP_MODE_1                     0x0200u /* Line segments */
 456 #define CLIP_MODE_2                     0x0400u /* Polygon boundary lines */
 457 #define CLIP_MODE_3                     0x0600u /* Patterned lines */
 458 #define DEST_X_START            0xa6eeu         /* Write */
 459 #define DEST_X_END              0xaaeeu         /* Write */
 460 #define DEST_Y_END              0xaeeeu         /* Write */
 461 #define R_H_TOTAL_DISP          0xb2eeu         /* Read */      /* Mach32 */
 462 #define SRC_X_STRT              0xb2eeu         /* Write */
 463 #define R_H_SYNC_STRT           0xb6eeu         /* Read */      /* Mach32 */
 464 #define ALU_BG_FN               0xb6eeu         /* Write */
 465 #define R_H_SYNC_WID            0xbaeeu         /* Read */      /* Mach32 */
 466 #define ALU_FG_FN               0xbaeeu         /* Write */
 467 #define SRC_X_END               0xbeeeu         /* Write */
 468 #define R_V_TOTAL               0xc2eeu         /* Read */
 469 #define SRC_Y_DIR               0xc2eeu         /* Write */
 470 #define R_V_DISP                0xc6eeu         /* Read */      /* Mach32 */
 471 #define EXT_SHORT_STROKE        0xc6eeu         /* Write */
 472 #define R_V_SYNC_STRT           0xcaeeu         /* Read */      /* Mach32 */
 473 #define SCAN_X                  0xcaeeu         /* Write */
 474 #define VERT_LINE_CNTR          0xceeeu         /* Read */      /* Mach32 */
 475 #define DP_CONFIG               0xceeeu         /* Write */
 476 #define READ_WRITE                      0x0001u
 477 #define DATA_WIDTH                      0x0200u
 478 #define DATA_ORDER                      0x1000u
 479 #define FG_COLOR_SRC_FG                 0x2000u
 480 #define FG_COLOR_SRC_BLIT               0x6000u
 481 #define R_V_SYNC_WID            0xd2eeu         /* Read */
 482 #define PATT_LENGTH             0xd2eeu         /* Write */
 483 #define PATT_INDEX              0xd6eeu         /* Write */
 484 #define READ_SRC_X              0xdaeeu         /* Read */      /* Mach32 */
 485 #define EXT_SCISSOR_L           0xdaeeu         /* Write */
 486 #define READ_SRC_Y              0xdeeeu         /* Read */      /* Mach32 */
 487 #define EXT_SCISSOR_T           0xdeeeu         /* Write */
 488 #define EXT_SCISSOR_R           0xe2eeu         /* Write */
 489 #define EXT_SCISSOR_B           0xe6eeu         /* Write */
 490 /*      ?                       0xeaeeu */
 491 #define DEST_COMP_FN            0xeeeeu         /* Write */
 492 #define DEST_COLOR_CMP_MASK     0xf2eeu         /* Write */     /* Mach32 */
 493 /*      ?                       0xf6eeu */
 494 #define CHIP_ID                 0xfaeeu         /* Read */      /* Mach32 */
 495 #define CHIP_CODE_0                     0x001fu                 /* Mach32 */
 496 #define CHIP_CODE_1                     0x03e0u                 /* Mach32 */
 497 #define CHIP_CLASS                      0x0c00u                 /* Mach32 */
 498 #define CHIP_REV                        0xf000u                 /* Mach32 */
 499 #define LINEDRAW                0xfeeeu         /* Write */
 500
 501 /* ATI Mach64 register definitions */
 502 #define CRTC_H_TOTAL_DISP       IOPortTag(0x00u, 0x00u)
 503 #define CRTC_H_TOTAL                    0x000001fful
 504 /*      ?                               0x0000fe00ul */
 505 #define CRTC_H_DISP                     0x01ff0000ul
 506 /*      ?                               0xfe000000ul */
 507 #define CRTC_H_SYNC_STRT_WID    IOPortTag(0x01u, 0x01u)
 508 #define CRTC_H_SYNC_STRT                0x000000fful
 509 #define CRTC_H_SYNC_DLY                 0x00000700ul
 510 /*      ?                               0x00000800ul */
 511 #define CRTC_H_SYNC_STRT_HI             0x00001000ul
 512 /*      ?                               0x0000e000ul */
 513 #define CRTC_H_SYNC_WID                 0x001f0000ul
 514 #define CRTC_H_SYNC_POL                 0x00200000ul
 515 /*      ?                               0xffc00000ul */
 516 #define CRTC_V_TOTAL_DISP       IOPortTag(0x02u, 0x02u)
 517 #define CRTC_V_TOTAL                    0x000007fful
 518 /*      ?                               0x0000f800ul */
 519 #define CRTC_V_DISP                     0x07ff0000ul
 520 /*      ?                               0xf8000000ul */
 521 #define CRTC_V_SYNC_STRT_WID    IOPortTag(0x03u, 0x03u)
 522 #define CRTC_V_SYNC_STRT                0x000007fful
 523 /*      ?                               0x0000f800ul */
 524 #define CRTC_V_SYNC_WID                 0x001f0000ul
 525 #define CRTC_V_SYNC_POL                 0x00200000ul
 526 /*      ?                               0xffc00000ul */
 527 #define CRTC_VLINE_CRNT_VLINE   IOPortTag(0x04u, 0x04u)
 528 #define CRTC_VLINE                      0x000007fful
 529 /*      ?                               0x0000f800ul */
 530 #define CRTC_CRNT_VLINE                 0x07ff0000ul
 531 /*      ?                               0xf8000000ul */
 532 #define CRTC_OFF_PITCH          IOPortTag(0x05u, 0x05u)
 533 #define CRTC_OFFSET                     0x000ffffful
 534 #define CRTC_OFFSET_VGA                 0x0003fffful
 535 #define CRTC_OFFSET_LOCK                0x00100000ul    /* XC/XL */
 536 /*      ?                               0x00200000ul */
 537 #define CRTC_PITCH                      0xffc00000ul
 538 #define CRTC_INT_CNTL           IOPortTag(0x06u, 0x06u)
 539 #define CRTC_VBLANK                     0x00000001ul
 540 #define CRTC_VBLANK_INT_EN              0x00000002ul
 541 #define CRTC_VBLANK_INT                 0x00000004ul
 542 #define CRTC_VLINE_INT_EN               0x00000008ul
 543 #define CRTC_VLINE_INT                  0x00000010ul
 544 #define CRTC_VLINE_SYNC                 0x00000020ul
 545 #define CRTC_FRAME                      0x00000040ul
 546 #define CRTC_SNAPSHOT_INT_EN            0x00000080ul    /* GTPro */
 547 #define CRTC_SNAPSHOT_INT               0x00000100ul    /* GTPro */
 548 #define CRTC_I2C_INT_EN                 0x00000200ul    /* GTPro */
 549 #define CRTC_I2C_INT                    0x00000400ul    /* GTPro */
 550 #define CRTC2_VBLANK                    0x00000800ul    /* LTPro */
 551 #define CRTC2_VBLANK_INT_EN             0x00001000ul    /* LTPro */
 552 #define CRTC2_VBLANK_INT                0x00002000ul    /* LTPro */
 553 #define CRTC2_VLINE_INT_EN              0x00004000ul    /* LTPro */
 554 #define CRTC2_VLINE_INT                 0x00008000ul    /* LTPro */
 555 #define CRTC_CAPBUF0_INT_EN             0x00010000ul    /* VT/GT */
 556 #define CRTC_CAPBUF0_INT                0x00020000ul    /* VT/GT */
 557 #define CRTC_CAPBUF1_INT_EN             0x00040000ul    /* VT/GT */
 558 #define CRTC_CAPBUF1_INT                0x00080000ul    /* VT/GT */
 559 #define CRTC_OVERLAY_EOF_INT_EN         0x00100000ul    /* VT/GT */
 560 #define CRTC_OVERLAY_EOF_INT            0x00200000ul    /* VT/GT */
 561 #define CRTC_ONESHOT_CAP_INT_EN         0x00400000ul    /* VT/GT */
 562 #define CRTC_ONESHOT_CAP_INT            0x00800000ul    /* VT/GT */
 563 #define CRTC_BUSMASTER_EOL_INT_EN       0x01000000ul    /* VTB/GTB/LT */
 564 #define CRTC_BUSMASTER_EOL_INT          0x02000000ul    /* VTB/GTB/LT */
 565 #define CRTC_GP_INT_EN                  0x04000000ul    /* VTB/GTB/LT */
 566 #define CRTC_GP_INT                     0x08000000ul    /* VTB/GTB/LT */
 567 #define CRTC2_VLINE_SYNC                0x10000000ul    /* LTPro */
 568 #define CRTC_SNAPSHOT2_INT_EN           0x20000000ul    /* LTPro */
 569 #define CRTC_SNAPSHOT2_INT              0x40000000ul    /* LTPro */
 570 #define CRTC_VBLANK_BIT2_INT            0x80000000ul    /* GTPro */
 571 #define CRTC_INT_ENS    /* *** UPDATE ME *** */         \
 572                 (                                       \
 573                         CRTC_VBLANK_INT_EN |            \
 574                         CRTC_VLINE_INT_EN |             \
 575                         CRTC_SNAPSHOT_INT_EN |          \
 576                         CRTC_I2C_INT_EN |               \
 577                         CRTC2_VBLANK_INT_EN |           \
 578                         CRTC2_VLINE_INT_EN |            \
 579                         CRTC_CAPBUF0_INT_EN |           \
 580                         CRTC_CAPBUF1_INT_EN |           \
 581                         CRTC_OVERLAY_EOF_INT_EN |       \
 582                         CRTC_ONESHOT_CAP_INT_EN |       \
 583                         CRTC_BUSMASTER_EOL_INT_EN |     \
 584                         CRTC_GP_INT_EN |                \
 585                         CRTC_SNAPSHOT2_INT_EN |         \
 586                         0                               \
 587                 )
 588 #define CRTC_INT_ACKS   /* *** UPDATE ME *** */         \
 589                 (                                       \
 590                         CRTC_VBLANK_INT |               \
 591                         CRTC_VLINE_INT |                \
 592                         CRTC_SNAPSHOT_INT |             \
 593                         CRTC_I2C_INT |                  \
 594                         CRTC2_VBLANK_INT |              \
 595                         CRTC2_VLINE_INT |               \
 596                         CRTC_CAPBUF0_INT |              \
 597                         CRTC_CAPBUF1_INT |              \
 598                         CRTC_OVERLAY_EOF_INT |          \
 599                         CRTC_ONESHOT_CAP_INT |          \
 600                         CRTC_BUSMASTER_EOL_INT |        \
 601                         CRTC_GP_INT |                   \
 602                         CRTC_SNAPSHOT2_INT |            \
 603                         CRTC_VBLANK_BIT2_INT |          \
 604                         0                               \
 605                 )
 606 #define CRTC_GEN_CNTL           IOPortTag(0x07u, 0x07u)
 607 #define CRTC_DBL_SCAN_EN                0x00000001ul
 608 #define CRTC_INTERLACE_EN               0x00000002ul
 609 #define CRTC_HSYNC_DIS                  0x00000004ul
 610 #define CRTC_VSYNC_DIS                  0x00000008ul
 611 #define CRTC_CSYNC_EN                   0x00000010ul
 612 #define CRTC_PIX_BY_2_EN                0x00000020ul
 613 #define CRTC2_DBL_SCAN_EN               0x00000020ul    /* LTPro */
 614 #define CRTC_DISPLAY_DIS                0x00000040ul
 615 #define CRTC_VGA_XOVERSCAN              0x00000080ul
 616 #define CRTC_PIX_WIDTH                  0x00000700ul
 617 #define CRTC_BYTE_PIX_ORDER             0x00000800ul
 618 #define CRTC_VSYNC_INT_EN               0x00001000ul    /* XC/XL */
 619 #define CRTC_VSYNC_INT                  0x00002000ul    /* XC/XL */
 620 #define CRTC_FIFO_OVERFILL              0x0000c000ul    /* VT/GT */
 621 #define CRTC2_VSYNC_INT_EN              0x00004000ul    /* XC/XL */
 622 #define CRTC2_VSYNC_INT                 0x00008000ul    /* XC/XL */
 623 #define CRTC_FIFO_LWM                   0x000f0000ul
 624 #define CRTC_HVSYNC_IO_DRIVE            0x00010000ul    /* XC/XL */
 625 #define CRTC2_PIX_WIDTH                 0x000e0000ul    /* LTPro */
 626 #define CRTC_VGA_128KAP_PAGING          0x00100000ul    /* VT/GT */
 627 #define CRTC_DISPREQ_ONLY               0x00200000ul    /* VT/GT */
 628 #define CRTC_VFC_SYNC_TRISTATE          0x00200000ul    /* VTB/GTB/LT */
 629 #define CRTC2_EN                        0x00200000ul    /* LTPro */
 630 #define CRTC_LOCK_REGS                  0x00400000ul    /* VT/GT */
 631 #define CRTC_SYNC_TRISTATE              0x00800000ul    /* VT/GT */
 632 #define CRTC_EXT_DISP_EN                0x01000000ul
 633 #define CRTC_EN                         0x02000000ul
 634 #define CRTC_DISP_REQ_EN                0x04000000ul
 635 #define CRTC_VGA_LINEAR                 0x08000000ul
 636 #define CRTC_VSYNC_FALL_EDGE            0x10000000ul
 637 #define CRTC_VGA_TEXT_132               0x20000000ul
 638 #define CRTC_CNT_EN                     0x40000000ul
 639 #define CRTC_CUR_B_TEST                 0x80000000ul
 640 #define CRTC_INT_ENS_X  /* *** UPDATE ME *** */         \
 641                 (                                       \
 642                         CRTC_VSYNC_INT_EN |             \
 643                         CRTC2_VSYNC_INT_EN |            \
 644                         0                               \
 645                 )
 646 #define CRTC_INT_ACKS_X /* *** UPDATE ME *** */         \
 647                 (                                       \
 648                         CRTC_VSYNC_INT |                \
 649                         CRTC2_VSYNC_INT |               \
 650                         0                               \
 651                 )
 652 #define DSP_CONFIG              BlockIOTag(0x08u)       /* VTB/GTB/LT */
 653 #define DSP_XCLKS_PER_QW                0x00003ffful
 654 /*      ?                               0x00004000ul */
 655 #define DSP_FLUSH_WB                    0x00008000ul
 656 #define DSP_LOOP_LATENCY                0x000f0000ul
 657 #define DSP_PRECISION                   0x00700000ul
 658 /*      ?                               0xff800000ul */
 659 #define DSP_ON_OFF              BlockIOTag(0x09u)       /* VTB/GTB/LT */
 660 #define DSP_OFF                         0x000007fful
 661 /*      ?                               0x0000f800ul */
 662 #define DSP_ON                          0x07ff0000ul
 663 /*      ?                               0xf8000000ul */
 664 #define TIMER_CONFIG            BlockIOTag(0x0au)       /* VTB/GTB/LT */
 665 #define MEM_BUF_CNTL            BlockIOTag(0x0bu)       /* VTB/GTB/LT */
 666 #define SHARED_CNTL             BlockIOTag(0x0cu)       /* VTB/GTB/LT */
 667 #define SHARED_MEM_CONFIG       BlockIOTag(0x0du)       /* VTB/GTB/LT */
 668 #define MEM_ADDR_CONFIG         BlockIOTag(0x0du)       /* GTPro */
 669 #define SHARED_CNTL_CTD         BlockIOTag(0x0eu)       /* CTD */
 670 /*      ?                               0x00fffffful */
 671 #define CTD_FIFO5                       0x01000000ul
 672 /*      ?                               0xfe000000ul */
 673 #define CRT_TRAP                BlockIOTag(0x0eu)       /* VTB/GTB/LT */
 674 #define DSTN_CONTROL            BlockIOTag(0x0fu)       /* LT */
 675 #define I2C_CNTL_0              BlockIOTag(0x0fu)       /* GTPro */
 676 #define OVR_CLR                 IOPortTag(0x08u, 0x10u)
 677 #define OVR_CLR_8                       0x000000fful
 678 #define OVR_CLR_B                       0x0000ff00ul
 679 #define OVR_CLR_G                       0x00ff0000ul
 680 #define OVR_CLR_R                       0xff000000ul
 681 #define OVR_WID_LEFT_RIGHT      IOPortTag(0x09u, 0x11u)
 682 #define OVR_WID_LEFT                    0x0000003ful    /* 0x0f on <LT */
 683 /*      ?                               0x0000ffc0ul */
 684 #define OVR_WID_RIGHT                   0x003f0000ul    /* 0x0f0000 on <LT */
 685 /*      ?                               0xffc00000ul */
 686 #define OVR_WID_TOP_BOTTOM      IOPortTag(0x0au, 0x12u)
 687 #define OVR_WID_TOP                     0x000001fful    /* 0x00ff on <LT */
 688 /*      ?                               0x0000fe00ul */
 689 #define OVR_WID_BOTTOM                  0x01ff0000ul    /* 0x00ff0000 on <LT */
 690 /*      ?                               0xfe000000ul */
 691 #define VGA_DSP_CONFIG          BlockIOTag(0x13u)       /* VTB/GTB/LT */
 692 #define VGA_DSP_XCLKS_PER_QW            DSP_XCLKS_PER_QW
 693 /*      ?                               0x000fc000ul */
 694 #define VGA_DSP_PREC_PCLKBY2            0x00700000ul
 695 /*      ?                               0x00800000ul */
 696 #define VGA_DSP_PREC_PCLK               0x07000000ul
 697 /*      ?                               0xf8000000ul */
 698 #define VGA_DSP_ON_OFF          BlockIOTag(0x14u)       /* VTB/GTB/LT */
 699 #define VGA_DSP_OFF                     DSP_OFF
 700 /*      ?                               0x0000f800ul */
 701 #define VGA_DSP_ON                      DSP_ON
 702 /*      ?                               0xf8000000ul */
 703 #define DSP2_CONFIG             BlockIOTag(0x15u)       /* LTPro */
 704 #define DSP2_ON_OFF             BlockIOTag(0x16u)       /* LTPro */
 705 #define EXT_CRTC_GEN_CNTL       BlockIOTag(0x17u)       /* VT-A4 (W) */
 706 #define CRTC2_OFF_PITCH         BlockIOTag(0x17u)       /* LTPro */
 707 #define CUR_CLR0                IOPortTag(0x0bu, 0x18u)
 708 #define CUR_CLR1                IOPortTag(0x0cu, 0x19u)
 709 /* These are for both CUR_CLR0 and CUR_CLR1 */
 710 #define CUR_CLR_I                       0x000000fful
 711 #define CUR_CLR_B                       0x0000ff00ul
 712 #define CUR_CLR_G                       0x00ff0000ul
 713 #define CUR_CLR_R                       0xff000000ul
 714 #define CUR_CLR                         (CUR_CLR_R | CUR_CLR_G | CUR_CLR_B)
 715 #define CUR_OFFSET              IOPortTag(0x0du, 0x1au)
 716 #define CUR_HORZ_VERT_POSN      IOPortTag(0x0eu, 0x1bu)
 717 #define CUR_HORZ_POSN                   0x000007fful
 718 /*      ?                               0x0000f800ul */
 719 #define CUR_VERT_POSN                   0x07ff0000ul
 720 /*      ?                               0xf8000000ul */
 721 #define CUR_HORZ_VERT_OFF       IOPortTag(0x0fu, 0x1cu)
 722 #define CUR_HORZ_OFF                    0x0000007ful
 723 /*      ?                               0x0000ff80ul */
 724 #define CUR_VERT_OFF                    0x007f0000ul
 725 /*      ?                               0xff800000ul */
 726 #define CONFIG_PANEL            BlockIOTag(0x1du)       /* LT */
 727 #define PANEL_FORMAT                    0x00000007ul
 728 /*      ?                               0x00000008ul */
 729 #define PANEL_TYPE                      0x000000f0ul
 730 #define NO_OF_GREY                      0x00000700ul
 731 #define MOD_GEN                         0x00001800ul
 732 #define EXT_LVDS_CLK                    0x00001800ul    /* LTPro */
 733 #define BLINK_RATE                      0x00006000ul
 734 #define BLINK_RATE_PRO                  0x00002000ul    /* LTPro */
 735 #define DONT_SHADOW_HEND                0x00004000ul    /* LTPro */
 736 #define DONT_USE_F32KHZ                 0x00008000ul
 737 #define LCD_IO_DRIVE                    0x00008000ul    /* XC/XL */
 738 #define FP_POL                          0x00010000ul
 739 #define LP_POL                          0x00020000ul
 740 #define DTMG_POL                        0x00040000ul
 741 #define SCK_POL                         0x00080000ul
 742 #define DITHER_SEL                      0x00300000ul
 743 #define INVERSE_VIDEO_EN                0x00400000ul
 744 #define BL_CLK_SEL                      0x01800000ul
 745 #define BL_LEVEL                        0x0e000000ul
 746 #define BL_CLK_SEL_PRO                  0x00800000ul    /* LTPro */
 747 #define BL_LEVEL_PRO                    0x03000000ul    /* LTPro */
 748 #define BIAS_LEVEL_PRO                  0x0c000000ul    /* LTPro */
 749 #define HSYNC_DELAY                     0xf0000000ul
 750 #define TV_OUT_INDEX            BlockIOTag(0x1du)       /* LTPro */
 751 #define TV_REG_INDEX                    0x000000fful
 752 #define TV_ON                           0x00000100ul
 753 /*      ?                               0xfffffe00ul */
 754 #define GP_IO                   IOPortTag(0x1eu, 0x1eu) /* VT/GT */
 755 #define GP_IO_CNTL              BlockIOTag(0x1fu)       /* VT/GT */
 756 #define HW_DEBUG                BlockIOTag(0x1fu)       /* VTB/GTB/LT */
 757 #define FAST_SRCCOPY_DIS                0x00000001ul
 758 #define BYPASS_SUBPIC_DBF               0x00000001ul    /* XL/XC */
 759 #define SRC_AUTONA_FIX_DIS              0x00000002ul
 760 #define SYNC_PD_EN                      0x00000002ul    /* Mobility */
 761 #define DISP_QW_FIX_DIS                 0x00000004ul
 762 #define GUIDST_WB_EXP_DIS               0x00000008ul
 763 #define CYC_ALL_FIX_DIS                 0x00000008ul    /* GTPro */
 764 #define AGPPLL_FIX_EN                   0x00000008ul    /* Mobility */
 765 #define SRC_AUTONA_ALWAYS_EN            0x00000010ul
 766 #define GUI_BEATS_HOST_P                0x00000010ul    /* GTPro */
 767 #define DRV_CNTL_DQMB_WEB               0x00000020ul
 768 #define FAST_FILL_SCISSOR_DIS           0x00000020ul    /* GT2c/VT4 */
 769 #define INTER_BLIT_FIX_DIS              0x00000020ul    /* GTPro */
 770 #define DRV_CNTL_MA                     0x00000040ul
 771 #define AUTO_BLKWRT_COLOR_DIS           0x00000040ul    /* GT2c/VT4 */
 772 #define INTER_PRIM_DIS                  0x00000040ul    /* GTPro */
 773 #define DRV_CNTL_MD                     0x00000080ul
 774 #define CHG_DEV_ID                      0x00000100ul
 775 #define SRC_TRACK_DST_FIX_DIS           0x00000200ul
 776 #define HCLK_FB_SKEW                    0x00000380ul    /* GT2c/VT4 */
 777 #define SRC_TRACK_DST_FIX_DIS_P         0x00000080ul    /* GTPro */
 778 #define AUTO_BLKWRT_COLOR_DIS_P         0x00000100ul    /* GTPro */
 779 #define INTER_LINE_OVERLAP_DIS          0x00000200ul    /* GTPro */
 780 #define MEM_OE_PULLBACK                 0x00000400ul
 781 #define DBL_BUFFER_EN                   0x00000400ul    /* GTPro */
 782 #define MEM_WE_FIX_DIS                  0x00000800ul
 783 #define MEM_OE_PULLBACK_B               0x00000800ul    /* GT2c/VT4 */
 784 #define CMDFIFO_SIZE_DIS_P              0x00000800ul    /* GTPro */
 785 #define RD_EN_FIX_DIS                   0x00001000ul
 786 #define MEM_WE_FIX_DIS_B                0x00001000ul
 787 #define AUTO_FF_DIS                     0x00001000ul    /* GTPro */
 788 #define CMDFIFO_SIZE_DIS                0x00002000ul    /* GT2c/VT4 */
 789 #define AUTO_BLKWRT_DIS                 0x00002000ul    /* GTPro */
 790 #define GUI_BEATS_HOST                  0x00004000ul    /* GT2c/VT4 */
 791 #define ORED_INVLD_RB_CACHE             0x00004000ul    /* GTPro */
 792 #define BLOCK_DBL_BUF                   0x00008000ul    /* GTPro */
 793 #define R2W_TURNAROUND_DELAY            0x00020000ul    /* GT2c/VT4 */
 794 #define ENA_32BIT_DATA_BUS              0x00040000ul    /* GT2c/VT4 */
 795 #define HCLK_FB_SKEW_P                  0x00070000ul    /* GTPro */
 796 #define ENA_FLASH_ROM                   0x00080000ul    /* GT2c/VT4 */
 797 #define DISABLE_SWITCH_FIX              0x00080000ul    /* GTPro */
 798 #define MCLK_START_EN                   0x00080000ul    /* LTPro */
 799 #define SEL_VBLANK_BDL_BUF              0x00100000ul    /* GTPro */
 800 #define CMDFIFO_64EN                    0x00200000ul    /* GTPro */
 801 #define BM_FIX_DIS                      0x00400000ul    /* GTPro */
 802 #define Z_SWITCH_EN                     0x00800000ul    /* LTPro */
 803 #define FLUSH_HOST_WB                   0x01000000ul    /* GTPro */
 804 #define HW_DEBUG_WRITE_MSK_FIX_DIS      0x02000000ul    /* LTPro */
 805 #define Z_NO_WRITE_EN                   0x04000000ul    /* LTPro */
 806 #define DISABLE_PCLK_RESET_P            0x08000000ul    /* LTPro */
 807 #define PM_D3_SUPPORT_ENABLE_P          0x10000000ul    /* LTPro */
 808 #define STARTCYCLE_FIX_ENABLE           0x20000000ul    /* LTPro */
 809 #define DONT_RST_CHAREN                 0x20000000ul    /* XL/XC */
 810 #define C3_FIX_ENABLE                   0x40000000ul    /* LTPro */
 811 #define BM_HOSTRA_EN                    0x40000000ul    /* XL/XC */
 812 #define PKGBGAb                         0x80000000ul    /* XL/XC */
 813 #define AUTOEXP_HORZ_FIX                0x80000000ul    /* Mobility */
 814 #define SCRATCH_REG0            IOPortTag(0x10u, 0x20u)
 815 #define SCRATCH_REG1            IOPortTag(0x11u, 0x21u)
 816 /*      BIOS_BASE_SEGMENT               0x0000007ful */ /* As above */
 817 /*      ?                               0x00000f80ul */
 818 #define BIOS_INIT_DAC_SUBTYPE           0x0000f000ul
 819 /*      ?                               0xffff0000ul */
 820 #define SCRATCH_REG2            BlockIOTag(0x22u)       /* LT */
 821 #define SCRATCH_REG3            BlockIOTag(0x23u)       /* GTPro */
 822 #define CLOCK_CNTL              IOPortTag(0x12u, 0x24u)
 823 #define CLOCK_BIT                       0x00000004ul    /* For ICS2595 */
 824 #define CLOCK_PULSE                     0x00000008ul    /* For ICS2595 */
 825 #define CLOCK_SELECT                    0x0000000ful
 826 #define CLOCK_DIVIDER                   0x00000030ul
 827 #define CLOCK_STROBE                    0x00000040ul
 828 #define CLOCK_DATA                      0x00000080ul
 829 /*      ?                               0x00000100ul */
 830 #define PLL_WR_EN                       0x00000200ul    /* For internal PLL */
 831 #define PLL_ADDR                        0x0000fc00ul    /* For internal PLL */
 832 #define PLL_DATA                        0x00ff0000ul    /* For internal PLL */
 833 /*      ?                               0xff000000ul */
 834 #define CONFIG_STAT64_1         BlockIOTag(0x25u)       /* GTPro */
 835 #define CFG_SUBSYS_DEV_ID               0x000000fful
 836 #define CFG_SUBSYS_VEN_ID               0x00ffff00ul
 837 /*      ?                               0x1f000000ul */
 838 #define CFG_DIMM_TYPE                   0xe0000000ul
 839 #define CFG_PCI_SUBSYS_DEV_ID           0x0000fffful    /* XC/XL */
 840 #define CFG_PCI_SUBSYS_VEN_ID           0xffff0000ul    /* XC/XL */
 841 #define CONFIG_STAT64_2         BlockIOTag(0x26u)       /* GTPro */
 842 #define CFG_DIMM_TYPE_3                 0x00000001ul
 843 /*      ?                               0x0000001eul */
 844 #define CFG_ROMWRTEN                    0x00000020ul
 845 #define CFG_AGPVCOGAIN                  0x000000c0ul
 846 #define CFG_PCI_TYPE                    0x00000100ul
 847 #define CFG_AGPSKEW                     0x00000e00ul
 848 #define CFG_X1CLKSKEW                   0x00007000ul
 849 #define CFG_PANEL_ID_P                  0x000f8000ul    /* LTPro */
 850 /*      ?                               0x00100000ul */
 851 #define CFG_PREFETCH_EN                 0x00200000ul
 852 #define CFG_ID_DISABLE                  0x00400000ul
 853 #define CFG_PRE_TESTEN                  0x00800000ul
 854 /*      ?                               0x01000000ul */
 855 #define CFG_PCI5VEN                     0x02000000ul    /* LTPro */
 856 #define CFG_VGA_DISABLE                 0x04000000ul
 857 #define CFG_ENINTB                      0x08000000ul
 858 /*      ?                               0x10000000ul */
 859 #define CFG_ROM_REMAP_2                 0x20000000ul
 860 #define CFG_IDSEL                       0x40000000ul
 861 /*      ?                               0x80000000ul */
 862 #define TV_OUT_DATA             BlockIOTag(0x27u)       /* LTPro */
 863 #define BUS_CNTL                IOPortTag(0x13u, 0x28u)
 864 #       define BUS_WS                   0x0000000ful
 865 #       define BUS_DBL_RESYNC           0x00000001ul    /* VTB/GTB/LT */
 866 #       define BUS_MSTR_RESET           0x00000002ul    /* VTB/GTB/LT */
 867 #       define BUS_FLUSH_BUF            0x00000004ul    /* VTB/GTB/LT */
 868 #       define BUS_STOP_REQ_DIS         0x00000008ul    /* VTB/GTB/LT */
 869 #       define BUS_ROM_WS               0x000000f0ul
 870 #       define BUS_APER_REG_DIS         0x00000010ul    /* VTB/GTB/LT */
 871 #       define BUS_EXTRA_PIPE_DIS       0x00000020ul    /* VTB/GTB/LT */
 872 #       define BUS_MASTER_DIS           0x00000040ul    /* VTB/GTB/LT */
 873 #       define BUS_ROM_WRT_EN           0x00000080ul    /* GTPro */
 874 #       define BUS_ROM_PAGE             0x00000f00ul
 875 #       define BUS_MINOR_REV_ID         0x00000700ul    /* LTPro */
 876 #       define BUS_EXT_REG_EN           0x08000000ul
 877 /*              First silicom - Prototype (A11) 0x00000000ul */
 878 /*              Metal mask spin (A12 & A13)     0x00000100ul */
 879 /*              All layer spin (A21)            0x00000200ul */
 880 /*              Fast metal spin (A22) - Prod.   0x00000300ul */
 881 /*              All layer spin (A31)            0x00000700ul */
 882 /*      ?                               0x00000800ul */ /* LTPro */
 883 #define BUS_CHIP_HIDDEN_REV             0x00000300ul    /* XC/XL */
 884 /*      ?                               0x00001c00ul */ /* XC/XL */
 885 #define BUS_ROM_DIS                     0x00001000ul
 886 #define BUS_IO_16_EN                    0x00002000ul    /* GX */
 887 #define BUS_PCI_READ_RETRY_EN           0x00002000ul    /* VTB/GTB/LT */
 888 #define BUS_DAC_SNOOP_EN                0x00004000ul
 889 #define BUS_PCI_RETRY_EN                0x00008000ul    /* VT/GT */
 890 #define BUS_PCI_WRT_RETRY_EN            0x00008000ul    /* VTB/GTB/LT */
 891 #define BUS_FIFO_WS                     0x000f0000ul
 892 #define BUS_RETRY_WS                    0x000f0000ul    /* VTB/GTB/LT */
 893 #define BUS_FIFO_ERR_INT_EN             0x00100000ul
 894 #define BUS_MSTR_RD_MULT                0x00100000ul    /* VTB/GTB/LT */
 895 #define BUS_FIFO_ERR_INT                0x00200000ul
 896 #define BUS_MSTR_RD_LINE                0x00200000ul    /* VTB/GTB/LT */
 897 #define BUS_HOST_ERR_INT_EN             0x00400000ul
 898 #define BUS_SUSPEND                     0x00400000ul    /* GTPro */
 899 #define BUS_HOST_ERR_INT                0x00800000ul
 900 #define BUS_LAT16X                      0x00800000ul    /* GTPro */
 901 #define BUS_PCI_DAC_WS                  0x07000000ul
 902 #define BUS_RD_DISCARD_EN               0x01000000ul    /* VTB/GTB/LT */
 903 #define BUS_RD_ABORT_EN                 0x02000000ul    /* VTB/GTB/LT */
 904 #define BUS_MSTR_WS                     0x04000000ul    /* VTB/GTB/LT */
 905 #define BUS_PCI_DAC_DLY                 0x08000000ul
 906 #define BUS_EXT_REG_EN                  0x08000000ul    /* VT/GT */
 907 #define BUS_PCI_MEMW_WS                 0x10000000ul
 908 #define BUS_MSTR_DISCONNECT_EN          0x10000000ul    /* VTB/GTB/LT */
 909 #define BUS_PCI_BURST_DEC               0x20000000ul    /* GX/CX */
 910 #define BUS_BURST                       0x20000000ul    /* 264xT */
 911 #define BUS_WRT_BURST                   0x20000000ul    /* VTB/GTB/LT */
 912 #define BUS_RDY_READ_DLY                0xc0000000ul
 913 #define BUS_READ_BURST                  0x40000000ul    /* VTB/GTB/LT */
 914 #define BUS_RDY_READ_DLY_B              0x80000000ul    /* VTB/GTB/LT */
 915 #define LCD_INDEX               BlockIOTag(0x29u)       /* LTPro */
 916 #define LCD_REG_INDEX                   0x0000003ful
 917 /*      ?                               0x000000c0ul */
 918 #define LCD_DISPLAY_DIS                 0x00000100ul
 919 #define LCD_SRC_SEL                     0x00000200ul
 920 #define LCD_SRC_SEL_CRTC1                       0x00000000ul
 921 #define LCD_SRC_SEL_CRTC2                       0x00000200ul
 922 #define LCD_CRTC2_DISPLAY_DIS           0x00000400ul
 923 #define LCD_GUI_ACTIVE                  0x00000800ul    /* XC/XL */
 924 /*      ?                               0x00fff000ul */
 925 #define LCD_MONDET_SENSE                0x01000000ul    /* XC/XL */
 926 #define LCD_MONDET_INT_POL              0x02000000ul    /* XC/XL */
 927 #define LCD_MONDET_INT_EN               0x04000000ul    /* XC/XL */
 928 #define LCD_MONDET_INT                  0x08000000ul    /* XC/XL */
 929 #define LCD_MONDET_EN                   0x10000000ul    /* XC/XL */
 930 #define LCD_EN_PL                       0x20000000ul    /* XC/XL */
 931 /*      ?                               0xc0000000ul */
 932 #define HFB_PITCH_ADDR          BlockIOTag(0x2au)       /* LT */
 933 #define LCD_DATA                BlockIOTag(0x2au)       /* LTPro */
 934 #define EXT_MEM_CNTL            BlockIOTag(0x2bu)       /* VTB/GTB/LT */
 935 #define MEM_CNTL                IOPortTag(0x14u, 0x2cu)
 936 #define CTL_MEM_SIZE                    0x00000007ul
 937 /*      ?                               0x00000008ul */
 938 #define CTL_MEM_REFRESH                 0x00000078ul    /* VT/GT */
 939 #define CTL_MEM_SIZEB                   0x0000000ful    /* VTB/GTB/LT */
 940 #define CTL_MEM_RD_LATCH_EN             0x00000010ul
 941 #define CTL_MEM_RD_LATCH_DLY            0x00000020ul
 942 #define CTL_MEM_LATENCY                 0x00000030ul    /* VTB/GTB/LT */
 943 #define CTL_MEM_SD_LATCH_EN             0x00000040ul
 944 #define CTL_MEM_SD_LATCH_DLY            0x00000080ul
 945 #define CTL_MEM_LATCH                   0x000000c0ul    /* VTB/GTB/LT */
 946 #define CTL_MEM_WDOE_CNTL               0x000000c0ul    /* XC/XL */
 947 #define CTL_MEM_FULL_PLS                0x00000100ul
 948 #define CTL_MEM_CYC_LNTH_AUX            0x00000180ul    /* VT/GT */
 949 #define CTL_MEM_TRP                     0x00000300ul    /* VTB/GTB/LT */
 950 #define CTL_MEM_CYC_LNTH                0x00000600ul
 951 #define CTL_MEM_REFRESH_RATE            0x00001800ul    /* 264xT */
 952 #define CTL_MEM_TRCD                    0x00000c00ul    /* VTB/GTB/LT */
 953 #define CTL_MEM_WR_RDY_SEL              0x00000800ul    /* GX/CX */
 954 #define CTL_MEM_EXT_RMW_CYC_EN          0x00001000ul    /* GX/CX */
 955 #define CTL_MEM_TCRD                    0x00001000ul    /* VTB/GTB/LT */
 956 #define CTL_MEM_DLL_RESET               0x00002000ul    /* VT/GT */
 957 #define CTL_MEM_TR2W                    0x00002000ul    /* GTPro */
 958 #define CTL_MEM_ACTV_PRE                0x0000c000ul    /* VT/GT */
 959 #define CTL_MEM_CAS_PHASE               0x00004000ul    /* GTPro */
 960 #define CTL_MEM_OE_PULLBACK             0x00008000ul    /* GTPro */
 961 #define CTL_MEM_TWR                     0x0000c000ul    /* XC/XL */
 962 #define CTL_MEM_BNDRY                   0x00030000ul
 963 #define CTL_MEM_BNDRY_0K                        0x00000000ul
 964 #define CTL_MEM_BNDRY_256K                      0x00010000ul
 965 #define CTL_MEM_BNDRY_512K                      0x00020000ul
 966 #define CTL_MEM_BNDRY_1024K                     0x00030000ul
 967 #define CTL_MEM_DLL_GAIN_CNTL           0x00030000ul    /* VT/GT */
 968 #define CTL_MEM_BNDRY_EN                0x00040000ul
 969 #define CTL_MEM_SDRAM_RESET             0x00040000ul    /* VT/GT */
 970 #define CTL_MEM_TRAS                    0x00070000ul    /* VTB/GTB/LT */
 971 #define CTL_MEM_TILE_SELECT             0x00180000ul    /* VT/GT */
 972 #define CTL_MEM_REFRESH_DIS             0x00080000ul    /* VTB/GTB/LT */
 973 #define CTL_MEM_LOW_LATENCY_MODE        0x00200000ul    /* VT/GT */
 974 #define CTL_MEM_CDE_PULLBACK            0x00400000ul    /* VT/GT */
 975 #define CTL_MEM_REFRESH_RATE_B          0x00f00000ul    /* VTB/GTB/LT */
 976 #define CTL_MEM_PIX_WIDTH               0x07000000ul
 977 #define CTL_MEM_LOWER_APER_ENDIAN       0x03000000ul    /* VTB/GTB/LT */
 978 #define CTL_MEM_OE_SELECT               0x18000000ul    /* VT/GT */
 979 #define CTL_MEM_UPPER_APER_ENDIAN       0x0c000000ul    /* VTB/GTB/LT */
 980 /*      ?                               0xe0000000ul */
 981 #define CTL_MEM_PAGE_SIZE               0x30000000ul    /* VTB/GTB/LT */
 982 #define MEM_VGA_WP_SEL          IOPortTag(0x15u, 0x2du)
 983 #define MEM_VGA_WPS0                    0x0000fffful
 984 #define MEM_VGA_WPS1                    0xffff0000ul
 985 #define MEM_VGA_RP_SEL          IOPortTag(0x16u, 0x2eu)
 986 #define MEM_VGA_RPS0                    0x0000fffful
 987 #define MEM_VGA_RPS1                    0xffff0000ul
 988 #define LT_GIO                  BlockIOTag(0x2fu)       /* LT */
 989 #define I2C_CNTL_1              BlockIOTag(0x2fu)       /* GTPro */
 990 #define DAC_REGS                IOPortTag(0x17u, 0x30u) /* 4 separate bytes */
 991 #define M64_DAC_WRITE                   (DAC_REGS + 0)
 992 #define M64_DAC_DATA                    (DAC_REGS + 1)
 993 #define M64_DAC_MASK                    (DAC_REGS + 2)
 994 #define M64_DAC_READ                    (DAC_REGS + 3)
 995 #define DAC_CNTL                IOPortTag(0x18u, 0x31u)
 996 #define DAC_EXT_SEL                     0x00000003ul
 997 #define DAC_EXT_SEL_RS2                         0x000000001ul
 998 #define DAC_EXT_SEL_RS3                         0x000000002ul
 999 #define DAC_RANGE_CTL                   0x00000003ul    /* VTB/GTB/LT */
1000 #define DAC_BLANKING                    0x00000004ul    /* 264xT */
1001 #define DAC_CMP_DIS                     0x00000008ul    /* 264xT */
1002 #define DAC1_CLK_SEL                    0x00000010ul    /* LTPro */
1003 #define DAC_PALETTE_ACCESS_CNTL         0x00000020ul    /* LTPro */
1004 #define DAC_PALETTE2_SNOOP_EN           0x00000040ul    /* LTPro */
1005 #define DAC_CMP_OUTPUT                  0x00000080ul    /* 264xT */
1006 #define DAC_8BIT_EN                     0x00000100ul
1007 #define DAC_PIX_DLY                     0x00000600ul
1008 #define DAC_DIRECT                      0x00000400ul    /* VTB/GTB/LT */
1009 #define DAC_BLANK_ADJ                   0x00001800ul
1010 #define DAC_PAL_CLK_SEL                 0x00000800ul    /* VTB/GTB/LT */
1011 #define DAC_CRT_SENSE                   0x00000800ul    /* XC/XL */
1012 #define DAC_CRT_DETECTION_ON            0x00001000ul    /* XC/XL */
1013 #define DAC_VGA_ADR_EN                  0x00002000ul
1014 #define DAC_FEA_CON_EN                  0x00004000ul    /* 264xT */
1015 #define DAC_PDMN                        0x00008000ul    /* 264xT */
1016 #define DAC_TYPE                        0x00070000ul
1017 /*      ?                               0x00f80000ul */
1018 #define DAC_MON_ID_STATE0               0x01000000ul    /* GX-E+/CX */
1019 #define DAC_GIO_STATE_1                 0x01000000ul    /* 264xT */
1020 #define DAC_MON_ID_STATE1               0x02000000ul    /* GX-E+/CX */
1021 #define DAC_GIO_STATE_0                 0x02000000ul    /* 264xT */
1022 #define DAC_MON_ID_STATE2               0x04000000ul    /* GX-E+/CX */
1023 #define DAC_GIO_STATE_4                 0x04000000ul    /* 264xT */
1024 #define DAC_MON_ID_DIR0                 0x08000000ul    /* GX-E+/CX */
1025 #define DAC_GIO_DIR_1                   0x08000000ul    /* 264xT */
1026 #define DAC_MON_ID_DIR1                 0x10000000ul    /* GX-E+/CX */
1027 #define DAC_GIO_DIR_0                   0x10000000ul    /* 264xT */
1028 #define DAC_MON_ID_DIR2                 0x20000000ul    /* GX-E+/CX */
1029 #define DAC_GIO_DIR_4                   0x20000000ul    /* 264xT */
1030 #define DAC_MAN_CMP_STATE               0x40000000ul    /* GX-E+ */
1031 #define DAC_RW_WS                       0x80000000ul    /* VT/GT */
1032 #define HORZ_STRETCHING         BlockIOTag(0x32u)       /* LT */
1033 #define HORZ_STRETCH_BLEND              0x00000ffful
1034 #define HORZ_STRETCH_RATIO              0x0000fffful
1035 #define HORZ_STRETCH_LOOP               0x00070000ul
1036 #define HORZ_STRETCH_LOOP09                     0x00000000ul
1037 #define HORZ_STRETCH_LOOP11                     0x00010000ul
1038 #define HORZ_STRETCH_LOOP12                     0x00020000ul
1039 #define HORZ_STRETCH_LOOP14                     0x00030000ul
1040 #define HORZ_STRETCH_LOOP15                     0x00040000ul
1041 /*      ?                                       0x00050000ul */
1042 /*      ?                                       0x00060000ul */
1043 /*      ?                                       0x00070000ul */
1044 /*      ?                               0x00080000ul */
1045 #define HORZ_PANEL_SIZE                 0x0ff00000ul    /* XC/XL */
1046 /*      ?                               0x10000000ul */
1047 #define AUTO_HORZ_RATIO                 0x20000000ul    /* XC/XL */
1048 #define HORZ_STRETCH_MODE               0x40000000ul
1049 #define HORZ_STRETCH_EN                 0x80000000ul
1050 #define EXT_DAC_REGS            BlockIOTag(0x32u)       /* GTPro */
1051 #define VERT_STRETCHING         BlockIOTag(0x33u)       /* LT */
1052 #define VERT_STRETCH_RATIO0             0x000003fful
1053 #define VERT_STRETCH_RATIO1             0x000ffc00ul
1054 #define VERT_STRETCH_RATIO2             0x3ff00000ul
1055 #define VERT_STRETCH_USE0               0x40000000ul
1056 #define VERT_STRETCH_EN                 0x80000000ul
1057 #define GEN_TEST_CNTL           IOPortTag(0x19u, 0x34u)
1058 #define GEN_EE_DATA_OUT                 0x00000001ul    /* GX/CX */
1059 #define GEN_GIO2_DATA_OUT               0x00000001ul    /* 264xT */
1060 #define GEN_EE_CLOCK                    0x00000002ul    /* GX/CX */
1061 /*      ?                               0x00000002ul */ /* 264xT */
1062 #define GEN_EE_CHIP_SEL                 0x00000004ul    /* GX/CX */
1063 #define GEN_GIO3_DATA_OUT               0x00000004ul    /* 264xT */
1064 #define GEN_EE_DATA_IN                  0x00000008ul    /* GX/CX */
1065 #define GEN_GIO2_DATA_IN                0x00000008ul    /* 264xT */
1066 #define GEN_EE_EN                       0x00000010ul    /* GX/CX */
1067 #define GEN_GIO2_ENABLE                 0x00000010ul    /* 264xT */
1068 #define GEN_ICON2_ENABLE                0x00000010ul    /* XC/XL */
1069 #define GEN_OVR_OUTPUT_EN               0x00000020ul    /* GX/CX */
1070 #define GEN_GIO2_WRITE                  0x00000020ul    /* 264xT */
1071 #define GEN_CUR2_ENABLE                 0x00000020ul    /* XC/XL */
1072 #define GEN_OVR_POLARITY                0x00000040ul    /* GX/CX */
1073 #define GEN_ICON_ENABLE                 0x00000040ul    /* XC/XL */
1074 #define GEN_CUR_EN                      0x00000080ul
1075 #define GEN_GUI_EN                      0x00000100ul    /* GX/CX */
1076 #define GEN_GUI_RESETB                  0x00000100ul    /* 264xT */
1077 #define GEN_BLOCK_WR_EN                 0x00000200ul    /* GX */
1078 /*      ?                               0x00000200ul */ /* CX/264xT */
1079 #define GEN_SOFT_RESET                  0x00000200ul    /* VTB/GTB/LT */
1080 #define GEN_MEM_TRISTATE                0x00000400ul    /* GTPro */
1081 /*      ?                               0x00000800ul */
1082 #define GEN_TEST_VECT_MODE              0x00003000ul    /* VT/GT */
1083 /*      ?                               0x0000c000ul */
1084 #define GEN_TEST_FIFO_EN                0x00010000ul    /* GX/CX */
1085 #define GEN_TEST_GUI_REGS_EN            0x00020000ul    /* GX/CX */
1086 #define GEN_TEST_VECT_EN                0x00040000ul    /* GX/CX */
1087 #define GEN_TEST_CRC_STR                0x00080000ul    /* GX-C/-D */
1088 /*      ?                               0x00080000ul */ /* GX-E+/CX */
1089 #define GEN_TEST_MODE_T                 0x000f0000ul    /* 264xT */
1090 #define GEN_TEST_MODE                   0x00700000ul    /* GX/CX */
1091 #define GEN_TEST_CNT_EN                 0x00100000ul    /* 264xT */
1092 #define GEN_TEST_CRC_EN                 0x00200000ul    /* 264xT */
1093 /*      ?                               0x00400000ul */ /* 264xT */
1094 /*      ?                               0x00800000ul */
1095 #define GEN_TEST_MEM_WR                 0x01000000ul    /* GX-C/-D */
1096 #define GEN_TEST_MEM_STROBE             0x02000000ul    /* GX-C/-D */
1097 #define GEN_TEST_DST_SS_EN              0x04000000ul    /* GX/CX */
1098 #define GEN_TEST_DST_SS_STROBE          0x08000000ul    /* GX/CX */
1099 #define GEN_TEST_SRC_SS_EN              0x10000000ul    /* GX/CX */
1100 #define GEN_TEST_SRC_SS_STROBE          0x20000000ul    /* GX/CX */
1101 #define GEN_TEST_CNT_VALUE              0x3f000000ul    /* 264xT */
1102 #define GEN_TEST_CC_EN                  0x40000000ul    /* GX/CX */
1103 #define GEN_TEST_CC_STROBE              0x80000000ul    /* GX/CX */
1104 /*      ?                               0xc0000000ul */ /* 264xT */
1105 #define GEN_DEBUG_MODE                  0xff000000ul    /* VTB/GTB/LT */
1106 #define LCD_GEN_CTRL            BlockIOTag(0x35u)       /* LT */
1107 #define CRT_ON                          0x00000001ul
1108 #define LCD_ON                          0x00000002ul
1109 #define HORZ_DIVBY2_EN                  0x00000004ul
1110 #define DONT_DS_ICON                    0x00000008ul
1111 #define LOCK_8DOT                       0x00000010ul
1112 #define ICON_ENABLE                     0x00000020ul
1113 #define DONT_SHADOW_VPAR                0x00000040ul
1114 #define V2CLK_PM_EN                     0x00000080ul
1115 #define RST_FM                          0x00000100ul
1116 #define DISABLE_PCLK_RESET              0x00000200ul    /* XC/XL */
1117 #define DIS_HOR_CRT_DIVBY2              0x00000400ul
1118 #define SCLK_SEL                        0x00000800ul
1119 #define SCLK_DELAY                      0x0000f000ul
1120 #define TVCLK_PM_EN                     0x00010000ul
1121 #define VCLK_DAC_PM_EN                  0x00020000ul
1122 #define VCLK_LCD_OFF                    0x00040000ul
1123 #define SELECT_WAIT_4MS                 0x00080000ul
1124 #define XTALIN_PM_EN                    0x00080000ul    /* XC/XL */
1125 #define V2CLK_DAC_PM_EN                 0x00100000ul
1126 #define LVDS_EN                         0x00200000ul
1127 #define LVDS_PLL_EN                     0x00400000ul
1128 #define LVDS_PLL_RESET                  0x00800000ul
1129 #define LVDS_RESERVED_BITS              0x07000000ul
1130 #define CRTC_RW_SELECT                  0x08000000ul    /* LTPro */
1131 #define USE_SHADOWED_VEND               0x10000000ul
1132 #define USE_SHADOWED_ROWCUR             0x20000000ul
1133 #define SHADOW_EN                       0x40000000ul
1134 #define SHADOW_RW_EN                    0x80000000ul
1135 #define CUSTOM_MACRO_CNTL       BlockIOTag(0x35u)       /* GTPro */
1136 #define POWER_MANAGEMENT        BlockIOTag(0x36u)       /* LT */
1137 #define PWR_MGT_ON                      0x00000001ul
1138 #define PWR_MGT_MODE                    0x00000006ul
1139 #define AUTO_PWRUP_EN                   0x00000008ul
1140 #define ACTIVITY_PIN_ON                 0x00000010ul
1141 #define STANDBY_POL                     0x00000020ul
1142 #define SUSPEND_POL                     0x00000040ul
1143 #define SELF_REFRESH                    0x00000080ul
1144 #define ACTIVITY_PIN_EN                 0x00000100ul
1145 #define KEYBD_SNOOP                     0x00000200ul
1146 #define USE_F32KHZ                      0x00000400ul    /* LTPro */
1147 #define DONT_USE_XTALIN                 0x00000400ul    /* XC/XL */
1148 #define TRISTATE_MEM_EN                 0x00000800ul    /* LTPro */
1149 #define LCDENG_TEST_MODE                0x0000f000ul
1150 #define STANDBY_COUNT                   0x000f0000ul
1151 #define SUSPEND_COUNT                   0x00f00000ul
1152 #define BAISON                          0x01000000ul
1153 #define BLON                            0x02000000ul
1154 #define DIGON                           0x04000000ul
1155 #define PM_D3_SUPPORT_ENABLE            0x08000000ul    /* XC/XL */
1156 #define STANDBY_NOW                     0x10000000ul
1157 #define SUSPEND_NOW                     0x20000000ul
1158 #define PWR_MGT_STATUS                  0xc0000000ul
1159 #define CONFIG_CNTL             IOPortTag(0x1au, 0x37u)
1160 #define CFG_MEM_AP_SIZE                 0x00000003ul
1161 #define CFG_MEM_VGA_AP_EN               0x00000004ul
1162 /*      ?                               0x00000008ul */
1163 #define CFG_MEM_AP_LOC                  0x00003ff0ul
1164 /*      ?                               0x0000c000ul */
1165 #define CFG_CARD_ID                     0x00070000ul
1166 #define CFG_VGA_DIS                     0x00080000ul
1167 /*      ?                               0x00f00000ul */
1168 #define CFG_CDE_WINDOW                  0x3f000000ul    /* VT/GT */
1169 /*      ?                               0xc0000000ul */
1170 #define CONFIG_CHIP_ID          IOPortTag(0x1bu, 0x38u) /* Read */
1171 #define CFG_CHIP_TYPE0                  0x000000fful
1172 #define CFG_CHIP_TYPE1                  0x0000ff00ul
1173 #define CFG_CHIP_TYPE                   0x0000fffful
1174 #define CFG_CHIP_CLASS                  0x00ff0000ul
1175 #define CFG_CHIP_REV                    0xff000000ul
1176 #define CFG_CHIP_VERSION                0x07000000ul    /* 264xT */
1177 #define CFG_CHIP_FOUNDRY                0x38000000ul    /* 264xT */
1178 #define CFG_CHIP_REVISION               0xc0000000ul    /* 264xT */
1179 #define CONFIG_STATUS64_0       IOPortTag(0x1cu, 0x39u) /* Read (R/W (264xT)) */
1180 #define CFG_BUS_TYPE                    0x00000007ul    /* GX/CX */
1181 #define CFG_MEM_TYPE_T                  0x00000007ul    /* 264xT */
1182 #define CFG_MEM_TYPE                    0x00000038ul    /* GX/CX */
1183 #define CFG_DUAL_CAS_EN_T               0x00000008ul    /* 264xT */
1184 #define CFG_ROM_128K_EN                 0x00000008ul    /* VTB/GTB/LT */
1185 #define CFG_ROM_REMAP                   0x00000008ul    /* GTPro */
1186 #define CFG_VGA_EN_T                    0x00000010ul    /* VT/GT */
1187 #define CFG_CLOCK_EN                    0x00000020ul    /* 264xT */
1188 #define CFG_DUAL_CAS_EN                 0x00000040ul    /* GX/CX */
1189 #define CFG_VMC_SENSE                   0x00000040ul    /* VT/GT */
1190 #define CFG_SHARED_MEM_EN               0x00000040ul    /* VTB/GTB/LT */
1191 #define CFG_LOCAL_BUS_OPTION            0x00000180ul    /* GX/CX */
1192 #define CFG_VFC_SENSE                   0x00000080ul    /* VT/GT */
1193 #define CFG_INIT_DAC_TYPE               0x00000e00ul    /* GX/CX */
1194 #define CFG_INIT_CARD_ID                0x00007000ul    /* GX-C/-D */
1195 #define CFG_BLK_WR_SIZE                 0x00001000ul    /* GX-E+ */
1196 #define CFG_INT_QSF_EN                  0x00002000ul    /* GX-E+ */
1197 /*      ?                               0x00004000ul */ /* GX-E+ */
1198 /*      ?                               0x00007000ul */ /* CX */
1199 #define CFG_TRI_BUF_DIS                 0x00008000ul    /* GX/CX */
1200 #define CFG_BOARD_ID                    0x0000ff00ul    /* VT/GT */
1201 #define CFG_EXT_RAM_ADDR                0x003f0000ul    /* GX/CX */
1202 #define CFG_PANEL_ID                    0x001f0000ul    /* LT */
1203 #define CFG_MACROVISION_EN              0x00200000ul    /* GTPro */
1204 #define CFG_ROM_DIS                     0x00400000ul    /* GX/CX */
1205 #define CFG_PCI33EN                     0x00400000ul    /* GTPro */
1206 #define CFG_VGA_EN                      0x00800000ul    /* GX/CX */
1207 #define CFG_FULLAGP                     0x00800000ul    /* GTPro */
1208 #define CFG_ARITHMOS_ENABLE             0x00800000ul    /* XC/XL */
1209 #define CFG_LOCAL_BUS_CFG               0x01000000ul    /* GX/CX */
1210 #define CFG_CHIP_EN                     0x02000000ul    /* GX/CX */
1211 #define CFG_LOCAL_READ_DLY_DIS          0x04000000ul    /* GX/CX */
1212 #define CFG_ROM_OPTION                  0x08000000ul    /* GX/CX */
1213 #define CFG_BUS_OPTION                  0x10000000ul    /* GX/CX */
1214 #define CFG_LOCAL_DAC_WR_EN             0x20000000ul    /* GX/CX */
1215 #define CFG_VLB_RDY_DIS                 0x40000000ul    /* GX/CX */
1216 #define CFG_AP_4GBYTE_DIS               0x80000000ul    /* GX/CX */
1217 #define CONFIG_STATUS64_1       IOPortTag(0x1du, 0x3au) /* Read */
1218 #define CFG_PCI_DAC_CFG                 0x00000001ul    /* GX/CX */
1219 /*      ?                               0x0000001eul */ /* GX/CX */
1220 #define CFG_1C8_IO_SEL                  0x00000020ul    /* GX/CX */
1221 /*      ?                               0xffffffc0ul */ /* GX/CX */
1222 #define CRC_SIG                         0xfffffffful    /* 264xT */
1223 #define MPP_CONFIG              BlockIOTag(0x3bu)       /* VTB/GTB/LT */
1224 #define MPP_STROBE_CONFIG       BlockIOTag(0x3cu)       /* VTB/GTB/LT */
1225 #define MPP_ADDR                BlockIOTag(0x3du)       /* VTB/GTB/LT */
1226 #define MPP_DATA                BlockIOTag(0x3eu)       /* VTB/GTB/LT */
1227 #define TVO_CNTL                BlockIOTag(0x3fu)       /* VTB/GTB/LT */
1228 /*      GP_IO                   IOPortTag(0x1eu, 0x1eu) */      /* See above */
1229 /*      CRTC_H_TOTAL_DISP       IOPortTag(0x1fu, 0x00u) */      /* Duplicate */
1230 #define DST_OFF_PITCH           BlockIOTag(0x40u)
1231 #define DST_OFFSET                      0x000ffffful
1232 /*      ?                               0x00300000ul */
1233 #define DST_PITCH                       0xffc00000ul
1234 #define DST_X                   BlockIOTag(0x41u)
1235 #define DST_Y                   BlockIOTag(0x42u)
1236 #define DST_Y_X                 BlockIOTag(0x43u)
1237 #define DST_WIDTH               BlockIOTag(0x44u)
1238 #define DST_HEIGHT              BlockIOTag(0x45u)
1239 #define DST_HEIGHT_WIDTH        BlockIOTag(0x46u)
1240 #define DST_X_WIDTH             BlockIOTag(0x47u)
1241 #define DST_BRES_LNTH           BlockIOTag(0x48u)
1242 #define DST_BRES_ERR            BlockIOTag(0x49u)
1243 #define DST_BRES_INC            BlockIOTag(0x4au)
1244 #define DST_BRES_DEC            BlockIOTag(0x4bu)
1245 #define DST_CNTL                BlockIOTag(0x4cu)
1246 #define DST_X_DIR                       0x00000001ul
1247 #define DST_Y_DIR                       0x00000002ul
1248 #define DST_Y_MAJOR                     0x00000004ul
1249 #define DST_X_TILE                      0x00000008ul
1250 #define DST_Y_TILE                      0x00000010ul
1251 #define DST_LAST_PEL                    0x00000020ul
1252 #define DST_POLYGON_EN                  0x00000040ul
1253 #define DST_24_ROT_EN                   0x00000080ul
1254 #define DST_24_ROT                      0x00000700ul
1255 #define DST_BRES_SIGN                   0x00000800ul    /* GX/CX */
1256 #define DST_BRES_ZERO                   0x00000800ul    /* CT */
1257 #define DST_POLYGON_RTEDGE_DIS          0x00001000ul    /* CT */
1258 #define TRAIL_X_DIR                     0x00002000ul    /* GT */
1259 #define TRAP_FILL_DIR                   0x00004000ul    /* GT */
1260 #define TRAIL_BRES_SIGN                 0x00008000ul    /* GT */
1261 /*      ?                               0x00010000ul */
1262 #define BRES_SIGN_AUTO                  0x00020000ul    /* GT */
1263 /*      ?                               0x00040000ul */
1264 #define ALPHA_OVERLAP_ENB               0x00080000ul    /* GTPro */
1265 #define SUB_PIX_ON                      0x00100000ul    /* GTPro */
1266 /*      ?                               0xffe00000ul */
1267 /*      DST_Y_X                 BlockIOTag(0x4du) */    /* Duplicate */
1268 #define TRAIL_BRES_ERR          BlockIOTag(0x4eu)       /* GT */
1269 #define TRAIL_BRES_INC          BlockIOTag(0x4fu)       /* GT */
1270 #define TRAIL_BRES_DEC          BlockIOTag(0x50u)       /* GT */
1271 #define LEAD_BRES_LNTH          BlockIOTag(0x51u)       /* GT */
1272 #define Z_OFF_PITCH             BlockIOTag(0x52u)       /* GT */
1273 #define Z_CNTL                  BlockIOTag(0x53u)       /* GT */
1274 #define ALPHA_TST_CNTL          BlockIOTag(0x54u)       /* GTPro */
1275 /*      ?                       BlockIOTag(0x55u) */
1276 #define SECONDARY_STW_EXP       BlockIOTag(0x56u)       /* GTPro */
1277 #define SECONDARY_S_X_INC       BlockIOTag(0x57u)       /* GTPro */
1278 #define SECONDARY_S_Y_INC       BlockIOTag(0x58u)       /* GTPro */
1279 #define SECONDARY_S_START       BlockIOTag(0x59u)       /* GTPro */
1280 #define SECONDARY_W_X_INC       BlockIOTag(0x5au)       /* GTPro */
1281 #define SECONDARY_W_Y_INC       BlockIOTag(0x5bu)       /* GTPro */
1282 #define SECONDARY_W_START       BlockIOTag(0x5cu)       /* GTPro */
1283 #define SECONDARY_T_X_INC       BlockIOTag(0x5du)       /* GTPro */
1284 #define SECONDARY_T_Y_INC       BlockIOTag(0x5eu)       /* GTPro */
1285 #define SECONDARY_T_START       BlockIOTag(0x5fu)       /* GTPro */
1286 #define SRC_OFF_PITCH           BlockIOTag(0x60u)
1287 #define SRC_OFFSET                      0x000ffffful
1288 /*      ?                               0x00300000ul */
1289 #define SRC_PITCH                       0xffc00000ul
1290 #define SRC_X                   BlockIOTag(0x61u)
1291 #define SRC_Y                   BlockIOTag(0x62u)
1292 #define SRC_Y_X                 BlockIOTag(0x63u)
1293 #define SRC_WIDTH1              BlockIOTag(0x64u)
1294 #define SRC_HEIGHT1             BlockIOTag(0x65u)
1295 #define SRC_HEIGHT1_WIDTH1      BlockIOTag(0x66u)
1296 #define SRC_X_START             BlockIOTag(0x67u)
1297 #define SRC_Y_START             BlockIOTag(0x68u)
1298 #define SRC_Y_X_START           BlockIOTag(0x69u)
1299 #define SRC_WIDTH2              BlockIOTag(0x6au)
1300 #define SRC_HEIGHT2             BlockIOTag(0x6bu)
1301 #define SRC_HEIGHT2_WIDTH2      BlockIOTag(0x6cu)
1302 #define SRC_CNTL                BlockIOTag(0x6du)
1303 #       define SRC_PATT_EN              0x00000001ul
1304 #       define SRC_PATT_ROT_EN          0x00000002ul
1305 #       define SRC_LINEAR_EN            0x00000004ul
1306 #       define SRC_BYTE_ALIGN           0x00000008ul
1307 #       define SRC_LINE_X_DIR           0x00000010ul
1308 #       define SRC_8X8X8_BRUSH          0x00000020ul    /* VTB/GTB */
1309 #       define FAST_FILL_EN             0x00000040ul    /* VTB/GTB */
1310 #       define SRC_TRACK_DST            0x00000080ul    /* VTB/GTB */
1311 #       define BUS_MASTER_EN            0x00000100ul    /* VTB/GTB */
1312 #       define BUS_MASTER_SYNC          0x00000200ul    /* VTB/GTB */
1313 #       define BUS_MASTER_OP            0x00000c00ul    /* VTB/GTB */
1314 #       define BM_OP_FRAME_TO_SYSTEM    (0 << 10)
1315 #       define BM_OP_SYSTEM_TO_FRAME    (1 << 10)
1316 #       define BM_OP_REG_TO_SYSTEM      (2 << 10)
1317 #       define BM_OP_SYSTEM_TO_REG      (3 << 10)
1318 #       define SRC_8X8X8_BRUSH_LOADED   0x00001000ul    /* VTB/GTB */
1319 #       define COLOR_REG_WRITE_EN       0x00002000ul    /* VTB/GTB */
1320 #       define BLOCK_WRITE_EN           0x00004000ul    /* VTB/GTB */
1321 /*      ?                               0xffff8000ul */
1322 /*      ?                       BlockIOTag(0x6eu) */
1323 /*      ?                       BlockIOTag(0x6fu) */
1324 #define SCALE_Y_OFF             BlockIOTag(0x70u)       /* GT */
1325 #define SCALE_OFF               BlockIOTag(0x70u)       /* GTPro */
1326 #define SECONDARY_SCALE_OFF     BlockIOTag(0x70u)       /* GTPro */
1327 #define TEX_0_OFF               BlockIOTag(0x70u)       /* GT */
1328 #define TEX_1_OFF               BlockIOTag(0x71u)       /* GT */
1329 #define TEX_2_OFF               BlockIOTag(0x72u)       /* GT */
1330 #define TEX_3_OFF               BlockIOTag(0x73u)       /* GT */
1331 #define TEX_4_OFF               BlockIOTag(0x74u)       /* GT */
1332 #define TEX_5_OFF               BlockIOTag(0x75u)       /* GT */
1333 #define TEX_6_OFF               BlockIOTag(0x76u)       /* GT */
1334 #define SCALE_WIDTH             BlockIOTag(0x77u)       /* GT */
1335 #define TEX_7_OFF               BlockIOTag(0x77u)       /* GT */
1336 #define SCALE_HEIGHT            BlockIOTag(0x78u)       /* GT */
1337 #define TEX_8_OFF               BlockIOTag(0x78u)       /* GT */
1338 #define TEX_9_OFF               BlockIOTag(0x79u)       /* GT */
1339 #define TEX_10_OFF              BlockIOTag(0x7au)       /* GT */
1340 #define S_Y_INC                 BlockIOTag(0x7bu)       /* GT */
1341 #define SCALE_Y_PITCH           BlockIOTag(0x7bu)       /* GT */
1342 #define SCALE_X_INC             BlockIOTag(0x7cu)       /* GT */
1343 #define RED_X_INC               BlockIOTag(0x7cu)       /* GT */
1344 #define GREEN_X_INC             BlockIOTag(0x7du)       /* GT */
1345 #define SCALE_Y_INC             BlockIOTag(0x7du)       /* GT */
1346 #define SCALE_VACC              BlockIOTag(0x7eu)       /* GT */
1347 #define SCALE_3D_CNTL           BlockIOTag(0x7fu)       /* GT */
1348 #define HOST_DATA_0             BlockIOTag(0x80u)
1349 #define HOST_DATA_1             BlockIOTag(0x81u)
1350 #define HOST_DATA_2             BlockIOTag(0x82u)
1351 #define HOST_DATA_3             BlockIOTag(0x83u)
1352 #define HOST_DATA_4             BlockIOTag(0x84u)
1353 #define HOST_DATA_5             BlockIOTag(0x85u)
1354 #define HOST_DATA_6             BlockIOTag(0x86u)
1355 #define HOST_DATA_7             BlockIOTag(0x87u)
1356 #define HOST_DATA_8             BlockIOTag(0x88u)
1357 #define HOST_DATA_9             BlockIOTag(0x89u)
1358 #define HOST_DATA_A             BlockIOTag(0x8au)
1359 #define HOST_DATA_B             BlockIOTag(0x8bu)
1360 #define HOST_DATA_C             BlockIOTag(0x8cu)
1361 #define HOST_DATA_D             BlockIOTag(0x8du)
1362 #define HOST_DATA_E             BlockIOTag(0x8eu)
1363 #define HOST_DATA_F             BlockIOTag(0x8fu)
1364 #define HOST_CNTL               BlockIOTag(0x90u)
1365 #define HOST_BYTE_ALIGN                 0x00000001ul
1366 #define HOST_BIG_ENDIAN_EN              0x00000002ul    /* GX-E/CT */
1367 /*      ?                               0xfffffffcul */
1368 #define BM_HOSTDATA             BlockIOTag(0x91u)       /* VTB/GTB */
1369 #define BM_ADDR                 BlockIOTag(0x92u)       /* VTB/GTB */
1370 #define BM_DATA                 BlockIOTag(0x92u)       /* VTB/GTB */
1371 #define BM_GUI_TABLE_CMD        BlockIOTag(0x93u)       /* GTPro */
1372 #       define CIRCULAR_BUF_SIZE_16KB   (0 << 0)
1373 #       define CIRCULAR_BUF_SIZE_32KB   (1 << 0)
1374 #       define CIRCULAR_BUF_SIZE_64KB   (2 << 0)
1375 #       define CIRCULAR_BUF_SIZE_128KB  (3 << 0)
1376 #       define LAST_DESCRIPTOR          (1 << 31)
1377 /*      ?                       BlockIOTag(0x94u) */
1378 /*      ?                       BlockIOTag(0x95u) */
1379 /*      ?                       BlockIOTag(0x96u) */
1380 /*      ?                       BlockIOTag(0x97u) */
1381 /*      ?                       BlockIOTag(0x98u) */
1382 /*      ?                       BlockIOTag(0x99u) */
1383 /*      ?                       BlockIOTag(0x9au) */
1384 /*      ?                       BlockIOTag(0x9bu) */
1385 /*      ?                       BlockIOTag(0x9cu) */
1386 /*      ?                       BlockIOTag(0x9du) */
1387 /*      ?                       BlockIOTag(0x9eu) */
1388 /*      ?                       BlockIOTag(0x9fu) */
1389 #define PAT_REG0                BlockIOTag(0xa0u)
1390 #define PAT_REG1                BlockIOTag(0xa1u)
1391 #define PAT_CNTL                BlockIOTag(0xa2u)
1392 #define PAT_MONO_EN                     0x00000001ul
1393 #define PAT_CLR_4x2_EN                  0x00000002ul
1394 #define PAT_CLR_8x1_EN                  0x00000004ul
1395 /*      ?                               0xfffffff8ul */
1396 /*      ?                       BlockIOTag(0xa3u) */
1397 /*      ?                       BlockIOTag(0xa4u) */
1398 /*      ?                       BlockIOTag(0xa5u) */
1399 /*      ?                       BlockIOTag(0xa6u) */
1400 /*      ?                       BlockIOTag(0xa7u) */
1401 #define SC_LEFT                 BlockIOTag(0xa8u)
1402 #define SC_RIGHT                BlockIOTag(0xa9u)
1403 #define SC_LEFT_RIGHT           BlockIOTag(0xaau)
1404 #define SC_TOP                  BlockIOTag(0xabu)
1405 #define SC_BOTTOM               BlockIOTag(0xacu)
1406 #define SC_TOP_BOTTOM           BlockIOTag(0xadu)
1407 #define USR1_DST_OFF_PITCH      BlockIOTag(0xaeu)       /* LTPro */
1408 #define USR2_DST_OFF_PITCH      BlockIOTag(0xafu)       /* LTPro */
1409 #define DP_BKGD_CLR             BlockIOTag(0xb0u)
1410 #define DP_FRGD_CLR             BlockIOTag(0xb1u)
1411 #define DP_WRITE_MASK           BlockIOTag(0xb2u)
1412 #define DP_CHAIN_MASK           BlockIOTag(0xb3u)
1413 #define DP_CHAIN_1BPP                   0x00000000ul    /* Irrelevant */
1414 #define DP_CHAIN_4BPP                   0x00008888ul
1415 #define DP_CHAIN_8BPP                   0x00008080ul
1416 #define DP_CHAIN_8BPP_332               0x00009292ul
1417 #define DP_CHAIN_15BPP_1555             0x00004210ul
1418 #define DP_CHAIN_16BPP_565              0x00008410ul
1419 #define DP_CHAIN_24BPP_888              0x00008080ul
1420 #define DP_CHAIN_32BPP_8888             0x00008080ul
1421 /*      ?                               0xffff0000ul */
1422 #define DP_PIX_WIDTH            BlockIOTag(0xb4u)
1423 #define DP_DST_PIX_WIDTH                0x0000000ful
1424 #define COMPOSITE_PIX_WIDTH             0x000000f0ul    /* GTPro */
1425 #define DP_SRC_PIX_WIDTH                0x00000f00ul
1426 /*      ?                               0x00001000ul */
1427 #define DP_HOST_TRIPLE_EN               0x00002000ul    /* GT2c/VT4 */
1428 #define DP_SRC_AUTONA_FIX_DIS           0x00004000ul    /* GTB */
1429 #define DP_FAST_SRCCOPY_DIS             0x00008000ul    /* GTB */
1430 #define DP_HOST_PIX_WIDTH               0x000f0000ul
1431 #define DP_CI4_RGB_INDEX                0x00f00000ul    /* GTB */
1432 #define DP_BYTE_PIX_ORDER               0x01000000ul
1433 #define DP_CONVERSION_TEMP              0x02000000ul    /* GTB */
1434 #define DP_CI4_RGB_LOW_NIBBLE           0x04000000ul    /* GTB */
1435 #define DP_C14_RGB_HIGH_NIBBLE          0x08000000ul    /* GTB */
1436 #define DP_SCALE_PIX_WIDTH              0xf0000000ul    /* GTB */
1437 #define DP_MIX                  BlockIOTag(0xb5u)
1438 #       define BKGD_MIX_NOT_D           (0 << 0)
1439 #       define BKGD_MIX_ZERO            (1 << 0)
1440 #       define BKGD_MIX_ONE             (2 << 0)
1441 #       define BKGD_MIX_D       (3 << 0)
1442 #       define BKGD_MIX_NOT_S           (4 << 0)
1443 #       define BKGD_MIX_D_XOR_S         (5 << 0)
1444 #       define BKGD_MIX_NOT_D_XOR_S     (6 << 0)
1445 #       define BKGD_MIX_S       (7 << 0)
1446 #       define BKGD_MIX_NOT_D_OR_NOT_S  (8 << 0)
1447 #       define BKGD_MIX_D_OR_NOT_S      (9 << 0)
1448 #       define BKGD_MIX_NOT_D_OR_S      (10 << 0)
1449 #       define BKGD_MIX_D_OR_S          (11 << 0)
1450 #       define BKGD_MIX_D_AND_S         (12 << 0)
1451 #       define BKGD_MIX_NOT_D_AND_S     (13 << 0)
1452 #       define BKGD_MIX_D_AND_NOT_S     (14 << 0)
1453 #       define BKGD_MIX_NOT_D_AND_NOT_S (15 << 0)
1454 #       define BKGD_MIX_D_PLUS_S_DIV2   (23 << 0)
1455 #       define FRGD_MIX_NOT_D           (0 << 16)
1456 #       define FRGD_MIX_ZERO            (1 << 16)
1457 #       define FRGD_MIX_ONE             (2 << 16)
1458 #       define FRGD_MIX_D               (3 << 16)
1459 #       define FRGD_MIX_NOT_S           (4 << 16)
1460 #       define FRGD_MIX_D_XOR_S         (5 << 16)
1461 #       define FRGD_MIX_NOT_D_XOR_S     (6 << 16)
1462 #       define FRGD_MIX_S               (7 << 16)
1463 #       define FRGD_MIX_NOT_D_OR_NOT_S  (8 << 16)
1464 #       define FRGD_MIX_D_OR_NOT_S      (9 << 16)
1465 #       define FRGD_MIX_NOT_D_OR_S      (10 << 16)
1466 #       define FRGD_MIX_D_OR_S          (11 << 16)
1467 #       define FRGD_MIX_D_AND_S         (12 << 16)
1468 #       define FRGD_MIX_NOT_D_AND_S     (13 << 16)
1469 #       define FRGD_MIX_D_AND_NOT_S     (14 << 16)
1470 #       define FRGD_MIX_NOT_D_AND_NOT_S (15 << 16)
1471 #       define FRGD_MIX_D_PLUS_S_DIV2   (23 << 16)
1472 #define DP_SRC                  BlockIOTag(0xb6u)
1473 #       define BKGD_SRC_BKGD_CLR        (0 << 0)
1474 #       define BKGD_SRC_FRGD_CLR        (1 << 0)
1475 #       define BKGD_SRC_HOST            (2 << 0)
1476 #       define BKGD_SRC_BLIT            (3 << 0)
1477 #       define BKGD_SRC_PATTERN         (4 << 0)
1478 #       define BKGD_SRC_3D              (5 << 0)
1479 #       define FRGD_SRC_BKGD_CLR        (0 << 8)
1480 #       define FRGD_SRC_FRGD_CLR        (1 << 8)
1481 #       define FRGD_SRC_HOST            (2 << 8)
1482 #       define FRGD_SRC_BLIT            (3 << 8)
1483 #       define FRGD_SRC_PATTERN         (4 << 8)
1484 #       define FRGD_SRC_3D              (5 << 8)
1485 #       define MONO_SRC_ONE             (0 << 16)
1486 #       define MONO_SRC_PATTERN         (1 << 16)
1487 #       define MONO_SRC_HOST            (2 << 16)
1488 #       define MONO_SRC_BLIT            (3 << 16)
1489 #define DP_FRGD_CLR_MIX         BlockIOTag(0xb7u)       /* VTB/GTB */
1490 #define DP_FRGD_BKGD_CLR        BlockIOTag(0xb8u)       /* VTB/GTB */
1491 /*      ?                       BlockIOTag(0xb9u) */
1492 #define DST_X_Y                 BlockIOTag(0xbau)       /* VTB/GTB */
1493 #define DST_WIDTH_HEIGHT        BlockIOTag(0xbbu)       /* VTB/GTB */
1494 #define USR_DST_PITCH           BlockIOTag(0xbcu)       /* GTPro */
1495 /*      ?                       BlockIOTag(0xbdu) */
1496 #define DP_SET_GUI_ENGINE2      BlockIOTag(0xbeu)       /* GTPro */
1497 #define DP_SET_GUI_ENGINE       BlockIOTag(0xbfu)       /* VTB/GTB */
1498 #define CLR_CMP_CLR             BlockIOTag(0xc0u)
1499 #define CLR_CMP_MSK             BlockIOTag(0xc1u)
1500 #define CLR_CMP_CNTL            BlockIOTag(0xc2u)
1501 #define CLR_CMP_FN                      0x00000007ul
1502 #define CLR_CMP_FN_FALSE                        0x00000000ul
1503 #define CLR_CMP_FN_TRUE                         0x00000001ul
1504 /*      ?                                       0x00000002ul */
1505 /*      ?                                       0x00000003ul */
1506 #define CLR_CMP_FN_NOT_EQUAL                    0x00000004ul
1507 #define CLR_CMP_FN_EQUAL                        0x00000005ul
1508 /*      ?                                       0x00000006ul */
1509 /*      ?                                       0x00000007ul */
1510 /*      ?                               0x00fffff8ul */
1511 #define CLR_CMP_SRC                     0x03000000ul
1512 #define CLR_CMP_SRC_DST                         0x00000000ul
1513 #define CLR_CMP_SRC_2D                          0x01000000ul
1514 #define CLR_CMP_SRC_TEXEL                       0x02000000ul
1515 /*      ?                                       0x03000000ul */
1516 /*      ?                               0xfc000000ul */
1517 /*      ?                       BlockIOTag(0xc3u) */
1518 #define FIFO_STAT               BlockIOTag(0xc4u)
1519 #define FIFO_STAT_BITS                  0x0000fffful
1520 /*      ?                               0x7fff0000ul */
1521 #define FIFO_ERR                        0x80000000ul
1522 /*      ?                       BlockIOTag(0xc5u) */
1523 /*      ?                       BlockIOTag(0xc6u) */
1524 /*      ?                       BlockIOTag(0xc7u) */
1525 #define CONTEXT_MASK            BlockIOTag(0xc8u)
1526 /*      ?                       BlockIOTag(0xc9u) */
1527 /*      ?                       BlockIOTag(0xcau) */
1528 #define CONTEXT_LOAD_CNTL       BlockIOTag(0xcbu)
1529 #define CONTEXT_LOAD_PTR                0x00007ffful
1530 /*      ?                               0x00008000ul */
1531 #define CONTEXT_LOAD_CMD                0x00030000ul
1532 #define CONTEXT_LOAD_NONE                       0x00000000ul
1533 #define CONTEXT_LOAD_ONLY                       0x00010000ul
1534 #define CONTEXT_LOAD_FILL                       0x00020000ul
1535 #define CONTEXT_LOAD_LINE                       0x00030000ul
1536 /*      ?                               0x7ffc0000ul */
1537 #define CONTEXT_LOAD_DIS                0x80000000ul
1538 #define GUI_TRAJ_CNTL           BlockIOTag(0xccu)
1539 /*      ?                       BlockIOTag(0xcdu) */
1540 #define GUI_STAT                BlockIOTag(0xceu)
1541 #define GUI_ACTIVE                      0x00000001ul
1542 /*      ?                               0x000000feul */
1543 #define DSTX_LT_SCISSOR_LEFT            0x00000100ul
1544 #define DSTX_GT_SCISSOR_RIGHT           0x00000200ul
1545 #define DSTY_LT_SCISSOR_TOP             0x00000400ul
1546 #define DSTY_GT_SCISSOR_BOTTOM          0x00000800ul
1547 /*      ?                               0x0000f000ul */
1548 #define GUI_FIFO                        0x03ff0000ul    /* VTB/GTB */
1549 /*      ?                               0xfc000000ul */
1550 /*      ?                       BlockIOTag(0xcfu) */
1551 #define S_X_INC2                BlockIOTag(0xd0u)       /* GTB */
1552 #define TEX_PALETTE_INDEX       BlockIOTag(0xd0u)       /* GTPro */
1553 #define S_Y_INC2                BlockIOTag(0xd1u)       /* GTB */
1554 #define STW_EXP                 BlockIOTag(0xd1u)       /* GTPro */
1555 #define S_XY_INC2               BlockIOTag(0xd2u)       /* GTB */
1556 #define LOG_MAX_INC             BlockIOTag(0xd2u)       /* GTPro */
1557 #define S_XINC_START            BlockIOTag(0xd3u)       /* GTB */
1558 /*      S_Y_INC                 BlockIOTag(0xd4u) */    /* Duplicate */
1559 /*      SCALE_Y_PITCH           BlockIOTag(0xd4u) */    /* Duplicate */
1560 #define S_START                 BlockIOTag(0xd5u)       /* GTB */
1561 #define T_X_INC2                BlockIOTag(0xd6u)       /* GTB */
1562 #define W_X_INC                 BlockIOTag(0xd6u)       /* GTPro */
1563 #define T_Y_INC2                BlockIOTag(0xd7u)       /* GTB */
1564 #define W_Y_INC                 BlockIOTag(0xd7u)       /* GTPro */
1565 #define T_XY_INC2               BlockIOTag(0xd8u)       /* GTB */
1566 #define W_START                 BlockIOTag(0xd8u)       /* GTPro */
1567 #define T_XINC_START            BlockIOTag(0xd9u)       /* GTB */
1568 #define T_Y_INC                 BlockIOTag(0xdau)       /* GTB */
1569 #define SECONDARY_SCALE_PITCH   BlockIOTag(0xdau)       /* GTPro */
1570 #define T_START                 BlockIOTag(0xdbu)       /* GTB */
1571 #define TEX_SIZE_PITCH          BlockIOTag(0xdcu)       /* GTB */
1572 #define TEX_CNTL                BlockIOTag(0xddu)       /* GTPro */
1573 #define SECONDARY_TEX_OFFSET    BlockIOTag(0xdeu)       /* GTPro */
1574 #define TEX_PAL_WR              BlockIOTag(0xdfu)       /* GTB */
1575 #define TEX_PALETTE             BlockIOTag(0xdfu)       /* GTPro */
1576 #define SCALE_PITCH_BOTH        BlockIOTag(0xe0u)       /* GTPro */
1577 #define SECONDARY_SCALE_OFF_ACC BlockIOTag(0xe1u)       /* GTPro */
1578 #define SCALE_OFF_ACC           BlockIOTag(0xe2u)       /* GTPro */
1579 #define SCALE_DST_Y_X           BlockIOTag(0xe3u)       /* GTPro */
1580 /*      ?                       BlockIOTag(0xe4u) */
1581 /*      ?                       BlockIOTag(0xe5u) */
1582 #define COMPOSITE_SHADOW_ID     BlockIOTag(0xe6u)       /* GTPro */
1583 #define SECONDARY_SCALE_X_INC   BlockIOTag(0xe7u)       /* GTPro */
1584 #define SPECULAR_RED_X_INC      BlockIOTag(0xe7u)       /* GTPro */
1585 #define SPECULAR_RED_Y_INC      BlockIOTag(0xe8u)       /* GTPro */
1586 #define SPECULAR_RED_START      BlockIOTag(0xe9u)       /* GTPro */
1587 #define SECONDARY_SCALE_HACC    BlockIOTag(0xe9u)       /* GTPro */
1588 #define SPECULAR_GREEN_X_INC    BlockIOTag(0xeau)       /* GTPro */
1589 #define SPECULAR_GREEN_Y_INC    BlockIOTag(0xebu)       /* GTPro */
1590 #define SPECULAR_GREEN_START    BlockIOTag(0xecu)       /* GTPro */
1591 #define SPECULAR_BLUE_X_INC     BlockIOTag(0xedu)       /* GTPro */
1592 #define SPECULAR_BLUE_Y_INC     BlockIOTag(0xeeu)       /* GTPro */
1593 #define SPECULAR_BLUE_START     BlockIOTag(0xefu)       /* GTPro */
1594 /*      SCALE_X_INC             BlockIOTag(0xf0u) */    /* Duplicate */
1595 /*      RED_X_INC               BlockIOTag(0xf0u) */    /* Duplicate */
1596 #define RED_Y_INC               BlockIOTag(0xf1u)       /* GTB */
1597 #define SCALE_HACC              BlockIOTag(0xf2u)       /* GTB */
1598 #define RED_START               BlockIOTag(0xf2u)       /* GTB */
1599 /*      GREEN_X_INC             BlockIOTag(0xf3u) */    /* Duplicate */
1600 /*      SCALE_Y_INC             BlockIOTag(0xf3u) */    /* Duplicate */
1601 #define GREEN_Y_INC             BlockIOTag(0xf4u)       /* GTB */
1602 #define SECONDARY_SCALE_Y_INC   BlockIOTag(0xf4u)       /* GTPro */
1603 #define SECONDARY_SCALE_VACC    BlockIOTag(0xf5u)       /* GTPro */
1604 #define GREEN_START             BlockIOTag(0xf5u)       /* GTB */
1605 #define BLUE_X_INC              BlockIOTag(0xf6u)       /* GTB */
1606 #define SCALE_XUV_INC           BlockIOTag(0xf6u)       /* GTB */
1607 #define BLUE_Y_INC              BlockIOTag(0xf7u)       /* GTB */
1608 #define BLUE_START              BlockIOTag(0xf8u)       /* GTB */
1609 #define SCALE_UV_HACC           BlockIOTag(0xf8u)       /* GTB */
1610 #define Z_X_INC                 BlockIOTag(0xf9u)       /* GTB */
1611 #define Z_Y_INC                 BlockIOTag(0xfau)       /* GTB */
1612 #define Z_START                 BlockIOTag(0xfbu)       /* GTB */
1613 #define ALPHA_FOG_X_INC         BlockIOTag(0xfcu)       /* GTB */
1614 #define ALPHA_FOG_Y_INC         BlockIOTag(0xfdu)       /* GTB */
1615 #define ALPHA_FOG_START         BlockIOTag(0xfeu)       /* GTB */
1616 /*      ?                       BlockIOTag(0xffu) */
1617 #define OVERLAY_Y_X_START       BlockIOTag(0x100u)
1618 #define OVERLAY_Y_X_END         BlockIOTag(0x101u)
1619 #define OVERLAY_VIDEO_KEY_CLR   BlockIOTag(0x102u)
1620 #define OVERLAY_VIDEO_KEY_MSK   BlockIOTag(0x103u)
1621 #define OVERLAY_GRAPHICS_KEY_CLR BlockIOTag(0x104u)
1622 #define OVERLAY_GRAPHICS_KEY_MSK BlockIOTag(0x105u)
1623 #define OVERLAY_KEY_CNTL        BlockIOTag(0x106u)
1624 #       define VIDEO_KEY_FN_MASK                0x00000007L
1625 #       define VIDEO_KEY_FN_FALSE               0x00000000L
1626 #       define VIDEO_KEY_FN_TRUE                0x00000001L
1627 #       define VIDEO_KEY_FN_NE                  0x00000004L
1628 #       define VIDEO_KEY_FN_EQ                  0x00000005L // EQ and NE are exchanged relative to radeon
1629 #       define GRAPHIC_KEY_FN_MASK              0x00000070L
1630 #       define GRAPHIC_KEY_FN_FALSE             0x00000000L
1631 #       define GRAPHIC_KEY_FN_TRUE              0x00000010L
1632 #       define GRAPHIC_KEY_FN_NE                0x00000040L
1633 #       define GRAPHIC_KEY_FN_EQ                0x00000050L // EQ and NE are exchanged relative to radeon
1634 #       define CMP_MIX_MASK                     0x00000100L
1635 #       define CMP_MIX_OR                       0x00000000L
1636 #       define CMP_MIX_AND                      0x00000100L
1637 /*      ?                       BlockIOTag(0x107u) */
1638 #define OVERLAY_SCALE_INC       BlockIOTag(0x108u)
1639 #define OVERLAY_SCALE_CNTL      BlockIOTag(0x109u)
1640 #define SCALER_HEIGHT_WIDTH     BlockIOTag(0x10au)
1641 #define OVERLAY_TEST            BlockIOTag(0x10bu)
1642 #define SCALER_THRESHOLD        BlockIOTag(0x10cu)
1643 #define SCALER_BUF0_OFFSET      BlockIOTag(0x10du)      /* VTB/GTB */
1644 #define SCALER_BUF1_OFFSET      BlockIOTag(0x10eu)      /* VTB/GTB */
1645 #define SCALER_BUF_PITCH        BlockIOTag(0x10fu)      /* VTB/GTB */
1646 #define CAPTURE_Y_X             BlockIOTag(0x110u)
1647 #define CAPTURE_START_END       BlockIOTag(0x110u)      /* VTB/GTB */
1648 #define CAPTURE_HEIGHT_WIDTH    BlockIOTag(0x111u)
1649 #define CAPTURE_X_WIDTH         BlockIOTag(0x111u)      /* VTB/GTB */
1650 #define VIDEO_FORMAT            BlockIOTag(0x112u)
1651 #define VIDEO_CONFIG            BlockIOTag(0x113u)
1652 #define VBI_START_END           BlockIOTag(0x113u)      /* VTB/GTB */
1653 #define CAPTURE_CONFIG          BlockIOTag(0x114u)
1654 #define TRIG_CNTL               BlockIOTag(0x115u)
1655 #define VIDEO_SYNC_TEST         BlockIOTag(0x116u)
1656 #define OVERLAY_EXCLUSIVE_HORZ  BlockIOTag(0x116u)      /* VTB/GTB */
1657 #define EXT_CRTC_GEN_CNTL_R     BlockIOTag(0x117u)      /* VT-A4 (R) */
1658 #define OVERLAY_EXCLUSIVE_VERT  BlockIOTag(0x117u)      /* VTB/GTB */
1659 #define VMC_CONFIG              BlockIOTag(0x118u)
1660 #define VBI_WIDTH               BlockIOTag(0x118u)      /* VTB/GTB */
1661 #define VMC_STATUS              BlockIOTag(0x119u)
1662 #define CAPTURE_DEBUG           BlockIOTag(0x119u)      /* VTB/GTB */
1663 #define VMC_CMD                 BlockIOTag(0x11au)
1664 #define VIDEO_SYNC_TEST_B       BlockIOTag(0x11au)      /* VTB/GTB */
1665 #define VMC_ARG0                BlockIOTag(0x11bu)
1666 #define VMC_ARG1                BlockIOTag(0x11cu)
1667 #define SNAPSHOT_VH_COUNTS      BlockIOTag(0x11cu)      /* GTPro */
1668 #define VMC_SNOOP_ARG0          BlockIOTag(0x11du)
1669 #define SNAPSHOT_F_COUNT        BlockIOTag(0x11du)      /* GTPro */
1670 #define VMC_SNOOP_ARG1          BlockIOTag(0x11eu)
1671 #define N_VIF_COUNT             BlockIOTag(0x11eu)      /* GTPro */
1672 #define SNAPSHOT_VIF_COUNT      BlockIOTag(0x11fu)      /* GTPro */
1673 #define BUF0_OFFSET             BlockIOTag(0x120u)
1674 #define CAPTURE_BUF0_OFFSET     BlockIOTag(0x120u)      /* VTB/GTB */
1675 #define CAPTURE_BUF1_OFFSET     BlockIOTag(0x121u)      /* VTB/GTB */
1676 #define ONESHOT_BUF_OFFSET      BlockIOTag(0x122u)      /* VTB/GTB */
1677 #define BUF0_PITCH              BlockIOTag(0x123u)
1678 /*      ?                       BlockIOTag(0x124u) */
1679 /*      ?                       BlockIOTag(0x125u) */
1680 #define BUF1_OFFSET             BlockIOTag(0x126u)
1681 /*      ?                       BlockIOTag(0x127u) */
1682 /*      ?                       BlockIOTag(0x128u) */
1683 #define BUF1_PITCH              BlockIOTag(0x129u)
1684 /*      ?                       BlockIOTag(0x12au) */
1685 #define BUF0_CAP_ODD_OFFSET     BlockIOTag(0x12bu)
1686 #define BUF1_CAP_ODD_OFFSET     BlockIOTag(0x12cu)
1687 #define SNAPSHOT2_VH_COUNTS     BlockIOTag(0x12cu)      /* LTPro */
1688 #define SNAPSHOT2_F_COUNT       BlockIOTag(0x12du)      /* LTPro */
1689 #define N_VIF2_COUNT            BlockIOTag(0x12eu)      /* LTPro */
1690 #define SNAPSHOT2_VIF_COUNT     BlockIOTag(0x12fu)      /* LTPro */
1691 #define VMC_STRM_DATA_0         BlockIOTag(0x130u)
1692 /*      MPP_CONFIG              BlockIOTag(0x130u) */   /* See 0x3bu */
1693 #define VMC_STRM_DATA_1         BlockIOTag(0x131u)
1694 /*      MPP_STROBE_SEQ          BlockIOTag(0x131u) */   /* See 0x3cu */
1695 #define VMC_STRM_DATA_2         BlockIOTag(0x132u)
1696 /*      MPP_ADDR                BlockIOTag(0x132u) */   /* See 0x3du */
1697 #define VMC_STRM_DATA_3         BlockIOTag(0x133u)
1698 /*      MPP_DATA                BlockIOTag(0x133u) */   /* See 0x3eu */
1699 #define VMC_STRM_DATA_4         BlockIOTag(0x134u)
1700 #define VMC_STRM_DATA_5         BlockIOTag(0x135u)
1701 #define VMC_STRM_DATA_6         BlockIOTag(0x136u)
1702 #define VMC_STRM_DATA_7         BlockIOTag(0x137u)
1703 #define VMC_STRM_DATA_8         BlockIOTag(0x138u)
1704 #define VMC_STRM_DATA_9         BlockIOTag(0x139u)
1705 #define VMC_STRM_DATA_A         BlockIOTag(0x13au)
1706 #define VMC_STRM_DATA_B         BlockIOTag(0x13bu)
1707 #define VMC_STRM_DATA_C         BlockIOTag(0x13cu)
1708 #define VMC_STRM_DATA_D         BlockIOTag(0x13du)
1709 #define VMC_STRM_DATA_E         BlockIOTag(0x13eu)
1710 #define VMC_STRM_DATA_F         BlockIOTag(0x13fu)
1711 /*      TVO_CNTL                BlockIOTag(0x140u) */   /* See 0x3fu */
1712 /*      ?                       BlockIOTag(0x141u) */
1713 /*      ?                       BlockIOTag(0x142u) */
1714 /*      ?                       BlockIOTag(0x143u) */
1715 /*      ?                       BlockIOTag(0x144u) */
1716 /*      ?                       BlockIOTag(0x145u) */
1717 /*      ?                       BlockIOTag(0x146u) */
1718 /*      ?                       BlockIOTag(0x147u) */
1719 /*      ?                       BlockIOTag(0x148u) */
1720 /*      ?                       BlockIOTag(0x149u) */
1721 /*      ?                       BlockIOTag(0x14au) */
1722 /*      ?                       BlockIOTag(0x14bu) */
1723 /*      ?                       BlockIOTag(0x14cu) */
1724 /*      ?                       BlockIOTag(0x14du) */
1725 /*      ?                       BlockIOTag(0x14eu) */
1726 /*      ?                       BlockIOTag(0x14fu) */
1727 /*      ?                       BlockIOTag(0x150u) */
1728 #define CRT_HORZ_VERT_LOAD      BlockIOTag(0x151u)      /* VTB/GTB */
1729 #define AGP_BASE                BlockIOTag(0x152u)      /* GTPro */
1730 #define AGP_CNTL                BlockIOTag(0x153u)      /* GTPro */
1731 #define SCALER_COLOUR_CNTL      BlockIOTag(0x154u)      /* GTPro */
1732 #define SCALER_H_COEFF0         BlockIOTag(0x155u)      /* GTPro */
1733 #define SCALER_H_COEFF1         BlockIOTag(0x156u)      /* GTPro */
1734 #define SCALER_H_COEFF2         BlockIOTag(0x157u)      /* GTPro */
1735 #define SCALER_H_COEFF3         BlockIOTag(0x158u)      /* GTPro */
1736 #define SCALER_H_COEFF4         BlockIOTag(0x159u)      /* GTPro */
1737 /*      ?                       BlockIOTag(0x15au) */
1738 /*      ?                       BlockIOTag(0x15bu) */
1739 #define GUI_CMDFIFO_DEBUG       BlockIOTag(0x15cu)      /* GT2c/VT4 */
1740 #define GUI_CMDFIFO_DATA        BlockIOTag(0x15du)      /* GT2c/VT4 */
1741 #define GUI_CNTL                BlockIOTag(0x15eu)      /* GT2c/VT4 */
1742 #       define CMDFIFO_SIZE_MASK        0x00000003ul
1743 #       define CMDFIFO_SIZE_192         0x00000000ul
1744 #       define CMDFIFO_SIZE_128         0x00000001ul
1745 #       define CMDFIFO_SIZE_64          0x00000002ul
1746 /*      ?                               0x0000fffcul */
1747 #       define IDCT_PRSR_MODE           0x00010000ul    /* XL/XC */
1748 #       define IDCT_BLOCK_GUI_INITIATOR 0x00020000ul    /* XL/XC */
1749 /*      ?                               0xfffc0000ul */
1750 /*      ?                       BlockIOTag(0x15fu) */
1751 /* BUS MASTERING */
1752 #define BM_FRAME_BUF_OFFSET     BlockIOTag(0x160u)      /* VTB/GTB */
1753 #define BM_SYSTEM_MEM_ADDR      BlockIOTag(0x161u)      /* VTB/GTB */
1754 #define BM_COMMAND              BlockIOTag(0x162u)      /* VTB/GTB */
1755 #define BM_STATUS               BlockIOTag(0x163u)      /* VTB/GTB */
1756 /*      ?                       BlockIOTag(0x164u) */
1757 /*      ?                       BlockIOTag(0x165u) */
1758 /*      ?                       BlockIOTag(0x166u) */
1759 /*      ?                       BlockIOTag(0x167u) */
1760 /*      ?                       BlockIOTag(0x168u) */
1761 /*      ?                       BlockIOTag(0x169u) */
1762 /*      ?                       BlockIOTag(0x16au) */
1763 /*      ?                       BlockIOTag(0x16bu) */
1764 /*      ?                       BlockIOTag(0x16cu) */
1765 /*      ?                       BlockIOTag(0x16du) */
1766 #define BM_GUI_TABLE            BlockIOTag(0x16eu)      /* VTB/GTB */
1767 #define BM_SYSTEM_TABLE         BlockIOTag(0x16fu)      /* VTB/GTB */
1768 #       define DMA_GUI_COMMAND__BYTE_COUNT_MASK                 0x001fffff
1769 #       define DMA_GUI_COMMAND__HOLD_VIDEO_OFFSET               0x40000000
1770 #       define DMA_GUI_COMMAND__EOL                             0x80000000
1771 #       define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO                           0x0
1772 #       define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM                           0x1
1773 #       define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF0_READY          0x2
1774 #       define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF1_READY          0x3
1775 #       define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_SNAPSHOT_READY      0x4
1776 /*      ?                       BlockIOTag(0x170u) */
1777 /*      ?                       BlockIOTag(0x171u) */
1778 /*      ?                       BlockIOTag(0x172u) */
1779 /*      ?                       BlockIOTag(0x173u) */
1780 /*      ?                       BlockIOTag(0x174u) */
1781 #define SCALER_BUF0_OFFSET_V    BlockIOTag(0x175u)      /* GTPro */
1782 #define SCALER_BUF0_OFFSET_U    BlockIOTag(0x176u)      /* GTPro */
1783 #define SCALER_BUF1_OFFSET_V    BlockIOTag(0x177u)      /* GTPro */
1784 #define SCALER_BUF1_OFFSET_U    BlockIOTag(0x178u)      /* GTPro */
1785 /*      ?                       BlockIOTag(0x179u) */
1786 /*      ?                       BlockIOTag(0x17au) */
1787 /*      ?                       BlockIOTag(0x17bu) */
1788 /*      ?                       BlockIOTag(0x17cu) */
1789 /*      ?                       BlockIOTag(0x17du) */
1790 /*      ?                       BlockIOTag(0x17eu) */
1791 /*      ?                       BlockIOTag(0x17fu) */
1792 /*      ?                       BlockIOTag(0x180u) */
1793 /*      ?                       BlockIOTag(0x181u) */
1794 /*      ?                       BlockIOTag(0x182u) */
1795 /*      ?                       BlockIOTag(0x183u) */
1796 /*      ?                       BlockIOTag(0x184u) */
1797 /*      ?                       BlockIOTag(0x185u) */
1798 /*      ?                       BlockIOTag(0x186u) */
1799 /*      ?                       BlockIOTag(0x187u) */
1800 /*      ?                       BlockIOTag(0x188u) */
1801 /*      ?                       BlockIOTag(0x189u) */
1802 /*      ?                       BlockIOTag(0x18au) */
1803 /*      ?                       BlockIOTag(0x18bu) */
1804 /*      ?                       BlockIOTag(0x18cu) */
1805 /*      ?                       BlockIOTag(0x18du) */
1806 /*      ?                       BlockIOTag(0x18eu) */
1807 /*      ?                       BlockIOTag(0x18fu) */
1808 #define VERTEX_1_S              BlockIOTag(0x190u)      /* GTPro */
1809 #define VERTEX_1_T              BlockIOTag(0x191u)      /* GTPro */
1810 #define VERTEX_1_W              BlockIOTag(0x192u)      /* GTPro */
1811 #define VERTEX_1_SPEC_ARGB      BlockIOTag(0x193u)      /* GTPro */
1812 #define VERTEX_1_Z              BlockIOTag(0x194u)      /* GTPro */
1813 #define VERTEX_1_ARGB           BlockIOTag(0x195u)      /* GTPro */
1814 #define VERTEX_1_X_Y            BlockIOTag(0x196u)      /* GTPro */
1815 #define ONE_OVER_AREA           BlockIOTag(0x197u)      /* GTPro */
1816 #define VERTEX_2_S              BlockIOTag(0x198u)      /* GTPro */
1817 #define VERTEX_2_T              BlockIOTag(0x199u)      /* GTPro */
1818 #define VERTEX_2_W              BlockIOTag(0x19au)      /* GTPro */
1819 #define VERTEX_2_SPEC_ARGB      BlockIOTag(0x19bu)      /* GTPro */
1820 #define VERTEX_2_Z              BlockIOTag(0x19cu)      /* GTPro */
1821 #define VERTEX_2_ARGB           BlockIOTag(0x19du)      /* GTPro */
1822 #define VERTEX_2_X_Y            BlockIOTag(0x19eu)      /* GTPro */
1823 /*      ONE_OVER_AREA           BlockIOTag(0x19fu) */   /* Duplicate */
1824 #define VERTEX_3_S              BlockIOTag(0x1a0u)      /* GTPro */
1825 #define VERTEX_3_T              BlockIOTag(0x1a1u)      /* GTPro */
1826 #define VERTEX_3_W              BlockIOTag(0x1a2u)      /* GTPro */
1827 #define VERTEX_3_SPEC_ARGB      BlockIOTag(0x1a3u)      /* GTPro */
1828 #define VERTEX_3_Z              BlockIOTag(0x1a4u)      /* GTPro */
1829 #define VERTEX_3_ARGB           BlockIOTag(0x1a5u)      /* GTPro */
1830 #define VERTEX_3_X_Y            BlockIOTag(0x1a6u)      /* GTPro */
1831 /*      ONE_OVER_AREA           BlockIOTag(0x1a7u) */   /* Duplicate */
1832 #define VERTEX_3_SECONDARY_S    BlockIOTag(0x1a8u)      /* GTPro */
1833 #define VERTEX_3_SECONDARY_T    BlockIOTag(0x1a9u)      /* GTPro */
1834 #define VERTEX_3_SECONDARY_W    BlockIOTag(0x1aau)      /* GTPro */
1835 /*      VERTEX_1_S              BlockIOTag(0x1abu) */   /* Duplicate */
1836 /*      VERTEX_1_T              BlockIOTag(0x1acu) */   /* Duplicate */
1837 /*      VERTEX_1_W              BlockIOTag(0x1adu) */   /* Duplicate */
1838 /*      VERTEX_2_S              BlockIOTag(0x1aeu) */   /* Duplicate */
1839 /*      VERTEX_2_T              BlockIOTag(0x1afu) */   /* Duplicate */
1840 /*      VERTEX_2_W              BlockIOTag(0x1b0u) */   /* Duplicate */
1841 /*      VERTEX_3_S              BlockIOTag(0x1b1u) */   /* Duplicate */
1842 /*      VERTEX_3_T              BlockIOTag(0x1b2u) */   /* Duplicate */
1843 /*      VERTEX_3_W              BlockIOTag(0x1b3u) */   /* Duplicate */
1844 /*      VERTEX_1_SPEC_ARGB      BlockIOTag(0x1b4u) */   /* Duplicate */
1845 /*      VERTEX_2_SPEC_ARGB      BlockIOTag(0x1b5u) */   /* Duplicate */
1846 /*      VERTEX_3_SPEC_ARGB      BlockIOTag(0x1b6u) */   /* Duplicate */
1847 /*      VERTEX_1_Z              BlockIOTag(0x1b7u) */   /* Duplicate */
1848 /*      VERTEX_2_Z              BlockIOTag(0x1b8u) */   /* Duplicate */
1849 /*      VERTEX_3_Z              BlockIOTag(0x1b9u) */   /* Duplicate */
1850 /*      VERTEX_1_ARGB           BlockIOTag(0x1bau) */   /* Duplicate */
1851 /*      VERTEX_2_ARGB           BlockIOTag(0x1bbu) */   /* Duplicate */
1852 /*      VERTEX_3_ARGB           BlockIOTag(0x1bcu) */   /* Duplicate */
1853 /*      VERTEX_1_X_Y            BlockIOTag(0x1bdu) */   /* Duplicate */
1854 /*      VERTEX_2_X_Y            BlockIOTag(0x1beu) */   /* Duplicate */
1855 /*      VERTEX_3_X_Y            BlockIOTag(0x1bfu) */   /* Duplicate */
1856 #define ONE_OVER_AREA_UC        BlockIOTag(0x1c0u)      /* GTPro */
1857 #define SETUP_CNTL              BlockIOTag(0x1c1u)      /* GTPro */
1858 /*      ?                       BlockIOTag(0x1c2u) */
1859 /*      ?                       BlockIOTag(0x1c3u) */
1860 /*      ?                       BlockIOTag(0x1c4u) */
1861 /*      ?                       BlockIOTag(0x1c5u) */
1862 /*      ?                       BlockIOTag(0x1c6u) */
1863 /*      ?                       BlockIOTag(0x1c7u) */
1864 /*      ?                       BlockIOTag(0x1c8u) */
1865 /*      ?                       BlockIOTag(0x1c9u) */
1866 #define VERTEX_1_SECONDARY_S    BlockIOTag(0x1cau)      /* GTPro */
1867 #define VERTEX_1_SECONDARY_T    BlockIOTag(0x1cbu)      /* GTPro */
1868 #define VERTEX_1_SECONDARY_W    BlockIOTag(0x1ccu)      /* GTPro */
1869 #define VERTEX_2_SECONDARY_S    BlockIOTag(0x1cdu)      /* GTPro */
1870 #define VERTEX_2_SECONDARY_T    BlockIOTag(0x1ceu)      /* GTPro */
1871 #define VERTEX_2_SECONDARY_W    BlockIOTag(0x1cfu)      /* GTPro */
1872 /*      ?                       BlockIOTag(0x1d0u) */
1873 /*      ?                       BlockIOTag(0x1d1u) */
1874 /*      ?                       BlockIOTag(0x1d2u) */
1875 /*      ?                       BlockIOTag(0x1d3u) */
1876 /*      ?                       BlockIOTag(0x1d4u) */
1877 /*      ?                       BlockIOTag(0x1d5u) */
1878 /*      ?                       BlockIOTag(0x1d6u) */
1879 /*      ?                       BlockIOTag(0x1d7u) */
1880 /*      ?                       BlockIOTag(0x1d8u) */
1881 /*      ?                       BlockIOTag(0x1d9u) */
1882 /*      ?                       BlockIOTag(0x1dau) */
1883 /*      ?                       BlockIOTag(0x1dbu) */
1884 /*      ?                       BlockIOTag(0x1dcu) */
1885 /*      ?                       BlockIOTag(0x1ddu) */
1886 /*      ?                       BlockIOTag(0x1deu) */
1887 /*      ?                       BlockIOTag(0x1dfu) */
1888 /*      ?                       BlockIOTag(0x1e0u) */
1889 /*      ?                       BlockIOTag(0x1e1u) */
1890 /*      ?                       BlockIOTag(0x1e2u) */
1891 /*      ?                       BlockIOTag(0x1e3u) */
1892 /*      ?                       BlockIOTag(0x1e4u) */
1893 /*      ?                       BlockIOTag(0x1e5u) */
1894 /*      ?                       BlockIOTag(0x1e6u) */
1895 /*      ?                       BlockIOTag(0x1e7u) */
1896 /*      ?                       BlockIOTag(0x1e8u) */
1897 /*      ?                       BlockIOTag(0x1e9u) */
1898 /*      ?                       BlockIOTag(0x1eau) */
1899 /*      ?                       BlockIOTag(0x1ebu) */
1900 /*      ?                       BlockIOTag(0x1ecu) */
1901 /*      ?                       BlockIOTag(0x1edu) */
1902 /*      ?                       BlockIOTag(0x1eeu) */
1903 /*      ?                       BlockIOTag(0x1efu) */
1904 /*      ?                       BlockIOTag(0x1f0u) */
1905 /*      ?                       BlockIOTag(0x1f1u) */
1906 /*      ?                       BlockIOTag(0x1f2u) */
1907 /*      ?                       BlockIOTag(0x1f3u) */
1908 /*      ?                       BlockIOTag(0x1f4u) */
1909 /*      ?                       BlockIOTag(0x1f5u) */
1910 /*      ?                       BlockIOTag(0x1f6u) */
1911 /*      ?                       BlockIOTag(0x1f7u) */
1912 /*      ?                       BlockIOTag(0x1f8u) */
1913 /*      ?                       BlockIOTag(0x1f9u) */
1914 /*      ?                       BlockIOTag(0x1fau) */
1915 /*      ?                       BlockIOTag(0x1fbu) */
1916 /*      ?                       BlockIOTag(0x1fcu) */
1917 /*      ?                       BlockIOTag(0x1fdu) */
1918 /*      ?                       BlockIOTag(0x1feu) */
1919 /*      ?                       BlockIOTag(0x1ffu) */
1920
1921 /* Definitions for MEM_CNTL's CTL_MEM_?????_APER_ENDIAN fields */
1922 #define CTL_MEM_APER_BYTE_ENDIAN        0x00u
1923 #define CTL_MEM_APER_WORD_ENDIAN        0x01u
1924 #define CTL_MEM_APER_LONG_ENDIAN        0x02u
1925 /*      ?                               0x03u */
1926
1927 /* Definitions for an ICS2595's programme word */
1928 #define ICS2595_CLOCK           0x000001f0ul
1929 #define ICS2595_FB_DIV          0x0001fe00ul            /* Feedback divider */
1930 #define ICS2595_POST_DIV        0x000c0000ul            /* Post-divider */
1931 #define ICS2595_STOP            0x00300000ul            /* Stop bits */
1932 #define ICS2595_TOGGLE          (ICS2595_POST_DIV | ICS2595_STOP)
1933
1934 /* Definitions for internal PLL registers on a 264xT */
1935 #define PLL_MPLL_CNTL           0x00u
1936 #define MPLL_PC_GAIN                    0x07u
1937 #define MPLL_VC_GAIN                    0x18u
1938 #define MPLL_D_CYC                      0x60u
1939 #define MPLL_RANGE                      0x80u
1940 #define VPLL_CNTL               0x01u
1941 #define VPLL_PC_GAIN                    0x07u
1942 #define VPLL_VC_GAIN                    0x18u
1943 #define VPLL_D_CYC                      0x60u
1944 #define VPLL_RANGE                      0x80u
1945 #define PLL_REF_DIV             0x02u
1946 #define PLL_GEN_CNTL            0x03u
1947 #define PLL_OVERRIDE                    0x01u
1948 #define PLL_SLEEP                       0x01u   /* GTPro */
1949 #define PLL_MCLK_RESET                  0x02u
1950 #define PLL_OSC_EN                      0x04u
1951 #define PLL_EXT_CLK_EN                  0x08u
1952 #define PLL_MCLK_SRC_SEL                0x70u
1953 #define PLL_EXT_CLK_CNTL                0x80u   /* CT/ET */
1954 #define PLL_DLL_PWDN                    0x80u   /* VTB/GTB/LT */
1955 #define PLL_MCLK_FB_DIV         0x04u
1956 #define PLL_VCLK_CNTL           0x05u
1957 #define PLL_VCLK_SRC_SEL                0x03u
1958 #define PLL_VCLK_RESET                  0x04u
1959 #define PLL_VCLK_INVERT                 0x08u
1960 #define PLL_ECP_DIV                     0x30u   /* VT/GT */
1961 #define PLL_ERATE_GT_XRATE              0x40u   /* VT/GT */
1962 #define PLL_SCALER_LOCK_EN              0x80u   /* VT/GT */
1963 #define PLL_VCLK_POST_DIV       0x06u
1964 #define PLL_VCLK0_POST_DIV              0x03u
1965 #define PLL_VCLK1_POST_DIV              0x0cu
1966 #define PLL_VCLK2_POST_DIV              0x30u
1967 #define PLL_VCLK3_POST_DIV              0xc0u
1968 #define PLL_VCLK0_FB_DIV        0x07u
1969 #define PLL_VCLK1_FB_DIV        0x08u
1970 #define PLL_VCLK2_FB_DIV        0x09u
1971 #define PLL_VCLK3_FB_DIV        0x0au
1972 #define PLL_XCLK_CNTL           0x0bu           /* VT/GT */
1973 #define PLL_XCLK_MCLK_RATIO             0x03u
1974 #define PLL_XCLK_SRC_SEL                0x07u   /* VTB/GTB/LT */
1975 #define PLL_MFB_TIMES_4_2B              0x08u
1976 #define PLL_VCLK0_XDIV                  0x10u
1977 #define PLL_VCLK1_XDIV                  0x20u
1978 #define PLL_VCLK2_XDIV                  0x40u
1979 #define PLL_VCLK3_XDIV                  0x80u
1980 #define PLL_FCP_CNTL            0x0cu           /* VT/GT */
1981 #define PLL_FCP_POST_DIV                0x0fu
1982 #define PLL_FCP_SRC_SEL                 0x70u
1983 #define PLL_DCLK_BY2_EN                 0x80u
1984 #define PLL_DLL_CNTL            0x0cu           /* VTB/GTB/LT */
1985 #define PLL_DLL_REF_SRC                 0x03u
1986 #define PLL_DLL_FB_SRC                  0x0cu
1987 #define PLL_DLL_GAIN                    0x30u
1988 #define PLL_DLL_RESET                   0x40u
1989 #define PLL_DLL_HCLK_OUT_EN             0x80u
1990 #define PLL_VFC_CNTL            0x0du           /* VT/GT */
1991 #define PLL_DCLK_INVB                   0x01u
1992 #define PLL_DCLKBY2_EN                  0x02u
1993 #define PLL_VFC_2PHASE                  0x04u
1994 #define PLL_VFC_DELAY                   0x18u
1995 #define PLL_VFC_DCLKBY2_SHIFT           0x20u
1996 /*      ?                               0x40u */
1997 #define PLL_TST_SRC_SEL_BIT5            0x80u   /* VTB/GTB/LT */
1998 #define PLL_TEST_CNTL           0x0eu
1999 #define PLL_TST_SRC_SEL                 0x1fu
2000 #define PLL_TST_DIVIDERS                0x20u
2001 #define PLL_TST_MASK_READ               0x40u
2002 #define PLL_TST_ANALOG_MON_EN           0x80u
2003 #define PLL_TEST_COUNT          0x0fu
2004 #define PLL_LVDSPLL_CNTL0       0x10u           /* LT */
2005 #define PLL_FPDI_NS_TIMING              0x01u
2006 #define PLL_CURR_LEVEL                  0x0eu
2007 #define PLL_LVDS_TEST_MODE              0xf0u
2008 #define PLL_LVDSPLL_CNTL1       0x11u           /* LT */
2009 #define PLL_LPPL_RANGE                  0x01u
2010 #define PLL_LPLL_DUTY                   0x06u
2011 #define PLL_LPLL_VC_GAIN                0x18u
2012 #define PLL_LPLL_CP_GAIN                0xe0u
2013 #define PLL_AGP1_CNTL           0x12u           /* GTPro */
2014 #define PLL_AGP2_CNTL           0x13u           /* GTPro */
2015 #define PLL_DLL2_CNTL           0x14u           /* GTPro */
2016 #define PLL_SCLK_FB_DIV         0x15u           /* GTPro */
2017 #define PLL_SPLL_CNTL1          0x16u           /* GTPro */
2018 #define PLL_SPLL_CNTL2          0x17u           /* GTPro */
2019 #define PLL_APLL_STRAPS         0x18u           /* GTPro */
2020 #define PLL_EXT_VPLL_CNTL       0x19u           /* GTPro */
2021 #define PLL_EXT_VPLL_REF_SRC            0x03u
2022 #define PLL_EXT_VPLL_EN                 0x04u
2023 #define PLL_EXT_VPLL_VGA_EN             0x08u
2024 #define PLL_EXT_VPLL_INSYNC             0x10u
2025 /*      ?                               0x60u */
2026 #define PLL_EXT_V2PLL_EN                0x80u
2027 #define PLL_EXT_VPLL_REF_DIV    0x1au           /* GTPro */
2028 #define PLL_EXT_VPLL_FB_DIV     0x1bu           /* GTPro */
2029 #define PLL_EXT_VPLL_MSB        0x1cu           /* GTPro */
2030 #define PLL_HTOTAL_CNTL         0x1du           /* GTPro */
2031 #define PLL_BYTE_CLK_CNTL       0x1eu           /* GTPro */
2032 #define PLL_TV_REF_DIV          0x1fu           /* LTPro */
2033 #define PLL_TV_FB_DIV           0x20u           /* LTPro */
2034 #define PLL_TV_CNTL             0x21u           /* LTPro */
2035 #define PLL_TV_GEN_CNTL         0x22u           /* LTPro */
2036 #define PLL_V2_CNTL             0x23u           /* LTPro */
2037 #define PLL_V2_GEN_CNTL         0x24u           /* LTPro */
2038 #define PLL_V2_REF_DIV          0x25u           /* LTPro */
2039 #define PLL_V2_FB_DIV           0x26u           /* LTPro */
2040 #define PLL_V2_MSB              0x27u           /* LTPro */
2041 #define PLL_HTOTAL2_CNTL        0x28u           /* LTPro */
2042 #define PLL_YCLK_CNTL           0x29u           /* XC/XL */
2043 #define PM_DYN_CLK_CNTL         0x2au           /* XC/XL */
2044 /*      ?                       0x2bu */
2045 /*      ?                       0x2cu */
2046 /*      ?                       0x2du */
2047 /*      ?                       0x2eu */
2048 /*      ?                       0x2fu */
2049 /*      ?                       0x30u */
2050 /*      ?                       0x31u */
2051 /*      ?                       0x32u */
2052 /*      ?                       0x33u */
2053 /*      ?                       0x34u */
2054 /*      ?                       0x35u */
2055 /*      ?                       0x36u */
2056 /*      ?                       0x37u */
2057 /*      ?                       0x38u */
2058 /*      ?                       0x39u */
2059 /*      ?                       0x3au */
2060 /*      ?                       0x3bu */
2061 /*      ?                       0x3cu */
2062 /*      ?                       0x3du */
2063 /*      ?                       0x3eu */
2064 /*      ?                       0x3fu */
2065
2066 /* Definitions for an LTPro's 32-bit LCD registers */
2067 #define LCD_CONFIG_PANEL        0x00u   /* See LT's CONFIG_PANEL (0x1d) */
2068 #define LCD_GEN_CNTL            0x01u   /* See LT's LCD_GEN_CTRL (0x35) */
2069 #define LCD_DSTN_CONTROL        0x02u   /* See LT's DSTN_CONTROL (0x1f) */
2070 #define LCD_HFB_PITCH_ADDR      0x03u   /* See LT's HFB_PITCH_ADDR (0x2a) */
2071 #define LCD_HORZ_STRETCHING     0x04u   /* See LT's HORZ_STRETCHING (0x32) */
2072 #define LCD_VERT_STRETCHING     0x05u   /* See LT's VERT_STRETCHING (0x33) */
2073 #define LCD_EXT_VERT_STRETCH    0x06u
2074 #define VERT_STRETCH_RATIO3             0x000003fful
2075 #define FORCE_DAC_DATA                  0x000000fful
2076 #define FORCE_DAC_DATA_SEL              0x00000300ul
2077 #define VERT_STRETCH_MODE               0x00000400ul
2078 #define VERT_PANEL_SIZE                 0x003ff800ul
2079 #define AUTO_VERT_RATIO                 0x00400000ul
2080 #define USE_AUTO_FP_POS                 0x00800000ul
2081 #define USE_AUTO_LCD_VSYNC              0x01000000ul
2082 /*      ?                               0xfe000000ul */
2083 #define LCD_LT_GIO              0x07u   /* See LT's LT_GIO (0x2f) */
2084 #define LCD_POWER_MANAGEMENT    0x08u   /* See LT's POWER_MANAGEMENT (0x36) */
2085 #define LCD_ZVGPIO              0x09u
2086 #define LCD_ICON_CLR0           0x0au                   /* XC/XL */
2087 #define LCD_ICON_CLR1           0x0bu                   /* XC/XL */
2088 #define LCD_ICON_OFFSET         0x0cu                   /* XC/XL */
2089 #define LCD_ICON_HORZ_VERT_POSN 0x0du                   /* XC/XL */
2090 #define LCD_ICON_HORZ_VERT_OFF  0x0eu                   /* XC/XL */
2091 #define LCD_ICON2_CLR0          0x0fu                   /* XC/XL */
2092 #define LCD_ICON2_CLR1          0x10u                   /* XC/XL */
2093 #define LCD_ICON2_OFFSET        0x11u                   /* XC/XL */
2094 #define LCD_ICON2_HORZ_VERT_POSN 0x12u                  /* XC/XL */
2095 #define LCD_ICON2_HORZ_VERT_OFF 0x13u                   /* XC/XL */
2096 #define LCD_MISC_CNTL           0x14u                   /* XC/XL */
2097 #define BL_MOD_LEVEL                    0x000000fful
2098 #define BIAS_MOD_LEVEL                  0x0000ff00ul
2099 #define BLMOD_EN                        0x00010000ul
2100 #define BIASMOD_EN                      0x00020000ul
2101 /*      ?                               0x00040000ul */
2102 #define PWRSEQ_MODE                     0x00080000ul
2103 #define APC_EN                          0x00100000ul
2104 #define MONITOR_DET_EN                  0x00200000ul
2105 #define FORCE_DAC_DATA_SEL_X            0x00c00000ul
2106 #define FORCE_DAC_DATA_X                0xff000000ul
2107 #define LCD_TMDS_CNTL           0x15u                   /* XC/XL */
2108 #define LCD_TMDS_SYNC_CHAR_SETA 0x16u                   /* XC/XL */
2109 #define LCD_TMDS_SYNC_CHAR_SETB 0x17u                   /* XC/XL */
2110 #define LCD_TMDS_SRC            0x18u                   /* XC/XL */
2111 #define LCD_PLTSTBLK_CNTL       0x19u                   /* XC/XL */
2112 #define LCD_SYNC_GEN_CNTL       0x1au                   /* XC/XL */
2113 #define LCD_PATTERN_GEN_SEED    0x1bu                   /* XC/XL */
2114 #define LCD_APC_CNTL            0x1cu                   /* XC/XL */
2115 #define LCD_POWER_MANAGEMENT_2  0x1du                   /* XC/XL */
2116 #define LCD_XCLK_DISP_PM_EN             0x00000001ul
2117 #define LCD_XCLK_DISP2_PM_EN            0x00000002ul    /* Mobility */
2118 #define LCD_XCLK_VID_PM_EN              0x00000004ul
2119 #define LCD_XCLK_SCL_PM_EN              0x00000008ul
2120 #define LCD_XCLK_GUI_PM_EN              0x00000010ul
2121 #define LCD_XCLK_SUB_PM_EN              0x00000020ul
2122 /*      ?                               0x000000c0ul */
2123 #define LCD_MCLK_PM_EN                  0x00000100ul
2124 #define LCD_SS_EN                       0x00000200ul
2125 #define LCD_BLON_DIGON_EN               0x00000400ul
2126 /*      ?                               0x00000800ul */
2127 #define LCD_PM_DYN_XCLK_SYNC            0x00003000ul
2128 #define LCD_SEL_W4MS                    0x00004000ul
2129 /*      ?                               0x00008000ul */
2130 #define LCD_PM_DYN_XCLK_EN              0x00010000ul
2131 #define LCD_PM_XCLK_ALWAYS              0x00020000ul
2132 #define LCD_PM_DYN_XCLK_STATUS          0x00040000ul
2133 #define LCD_PCI_ACC_DIS                 0x00080000ul
2134 #define LCD_PM_DYN_XCLK_DISP            0x00100000ul
2135 #define LCD_PM_DYN_XCLK_DISP2           0x00200000ul    /* Mobility */
2136 #define LCD_PM_DYN_XCLK_VID             0x00400000ul
2137 #define LCD_PM_DYN_XCLK_HFB             0x00800000ul
2138 #define LCD_PM_DYN_XCLK_SCL             0x01000000ul
2139 #define LCD_PM_DYN_XCLK_SUB             0x02000000ul
2140 #define LCD_PM_DYN_XCLK_GUI             0x04000000ul
2141 #define LCD_PM_DYN_XCLK_HOST            0x08000000ul
2142 /*      ?                               0xf0000000ul */
2143 #define LCD_PRI_ERR_PATTERN     0x1eu                   /* XC/XL */
2144 #define LCD_CUR_ERR_PATTERN     0x1fu                   /* XC/XL */
2145 #define LCD_PLTSTBLK_RPT        0x20u                   /* XC/XL */
2146 #define LCD_SYNC_RPT            0x21u                   /* XC/XL */
2147 #define LCD_CRC_PATTERN_RPT     0x22u                   /* XC/XL */
2148 #define LCD_PL_TRANSMITTER_CNTL 0x23u                   /* XC/XL */
2149 #define LCD_PL_PLL_CNTL         0x24u                   /* XC/XL */
2150 #define LCD_ALPHA_BLENDING      0x25u                   /* XC/XL */
2151 #define LCD_PORTRAIT_GEN_CNTL   0x26u                   /* XC/XL */
2152 #define LCD_APC_CTRL_IO         0x27u                   /* XC/XL */
2153 #define LCD_TEST_IO             0x28u                   /* XC/XL */
2154 /*      ?                       0x29u */
2155 #define LCD_DP1_MEM_ACCESS      0x2au                   /* XC/XL */
2156 #define LCD_DP0_MEM_ACCESS      0x2bu                   /* XC/XL */
2157 #define LCD_DP0_DEBUG_A         0x2cu                   /* XC/XL */
2158 #define LCD_DP0_DEBUG_B         0x2du                   /* XC/XL */
2159 #define LCD_DP1_DEBUG_A         0x2eu                   /* XC/XL */
2160 #define LCD_DP1_DEBUG_B         0x2fu                   /* XC/XL */
2161 #define LCD_DPCTRL_DEBUG_A      0x30u                   /* XC/XL */
2162 #define LCD_DPCTRL_DEBUG_B      0x31u                   /* XC/XL */
2163 #define LCD_MEMBLK_DEBUG        0x32u                   /* XC/XL */
2164 #define LCD_APC_LUT_AB          0x33u                   /* XC/XL */
2165 #define LCD_APC_LUT_CD          0x34u                   /* XC/XL */
2166 #define LCD_APC_LUT_EF          0x35u                   /* XC/XL */
2167 #define LCD_APC_LUT_GH          0x36u                   /* XC/XL */
2168 #define LCD_APC_LUT_IJ          0x37u                   /* XC/XL */
2169 #define LCD_APC_LUT_KL          0x38u                   /* XC/XL */
2170 #define LCD_APC_LUT_MN          0x39u                   /* XC/XL */
2171 #define LCD_APC_LUT_OP          0x3au                   /* XC/XL */
2172 /*      ?                       0x3bu */
2173 /*      ?                       0x3cu */
2174 /*      ?                       0x3du */
2175 /*      ?                       0x3eu */
2176 /*      ?                       0x3fu */
2177
2178 /* Definitions for an LTPro's TV registers */
2179 /*      ?                       0x00u */
2180 /*      ?                       0x01u */
2181 /*      ?                       0x02u */
2182 /*      ?                       0x03u */
2183 /*      ?                       0x04u */
2184 /*      ?                       0x05u */
2185 /*      ?                       0x06u */
2186 /*      ?                       0x07u */
2187 /*      ?                       0x08u */
2188 /*      ?                       0x09u */
2189 /*      ?                       0x0au */
2190 /*      ?                       0x0bu */
2191 /*      ?                       0x0cu */
2192 /*      ?                       0x0du */
2193 /*      ?                       0x0eu */
2194 /*      ?                       0x0fu */
2195 #define TV_MASTER_CNTL          0x10u
2196 /*      ?                       0x11u */
2197 #define TV_RGB_CNTL             0x12u
2198 /*      ?                       0x13u */
2199 #define TV_SYNC_CNTL            0x14u
2200 /*      ?                       0x15u */
2201 /*      ?                       0x16u */
2202 /*      ?                       0x17u */
2203 /*      ?                       0x18u */
2204 /*      ?                       0x19u */
2205 /*      ?                       0x1au */
2206 /*      ?                       0x1bu */
2207 /*      ?                       0x1cu */
2208 /*      ?                       0x1du */
2209 /*      ?                       0x1eu */
2210 /*      ?                       0x1fu */
2211 #define TV_HTOTAL               0x20u
2212 #define TV_HDISP                0x21u
2213 #define TV_HSIZE                0x22u
2214 #define TV_HSTART               0x23u
2215 #define TV_HCOUNT               0x24u
2216 #define TV_VTOTAL               0x25u
2217 #define TV_VDISP                0x26u
2218 #define TV_VCOUNT               0x27u
2219 #define TV_FTOTAL               0x28u
2220 #define TV_FCOUNT               0x29u
2221 #define TV_FRESTART             0x2au
2222 #define TV_HRESTART             0x2bu
2223 #define TV_VRESTART             0x2cu
2224 /*      ?                       0x2du */
2225 /*      ?                       0x2eu */
2226 /*      ?                       0x2fu */
2227 /*      ?                       0x30u */
2228 /*      ?                       0x31u */
2229 /*      ?                       0x32u */
2230 /*      ?                       0x33u */
2231 /*      ?                       0x34u */
2232 /*      ?                       0x35u */
2233 /*      ?                       0x36u */
2234 /*      ?                       0x37u */
2235 /*      ?                       0x38u */
2236 /*      ?                       0x39u */
2237 /*      ?                       0x3au */
2238 /*      ?                       0x3bu */
2239 /*      ?                       0x3cu */
2240 /*      ?                       0x3du */
2241 /*      ?                       0x3eu */
2242 /*      ?                       0x3fu */
2243 /*      ?                       0x40u */
2244 /*      ?                       0x41u */
2245 /*      ?                       0x42u */
2246 /*      ?                       0x43u */
2247 /*      ?                       0x44u */
2248 /*      ?                       0x45u */
2249 /*      ?                       0x46u */
2250 /*      ?                       0x47u */
2251 /*      ?                       0x48u */
2252 /*      ?                       0x49u */
2253 /*      ?                       0x4au */
2254 /*      ?                       0x4bu */
2255 /*      ?                       0x4cu */
2256 /*      ?                       0x4du */
2257 /*      ?                       0x4eu */
2258 /*      ?                       0x4fu */
2259 /*      ?                       0x50u */
2260 /*      ?                       0x51u */
2261 /*      ?                       0x52u */
2262 /*      ?                       0x53u */
2263 /*      ?                       0x54u */
2264 /*      ?                       0x55u */
2265 /*      ?                       0x56u */
2266 /*      ?                       0x57u */
2267 /*      ?                       0x58u */
2268 /*      ?                       0x59u */
2269 /*      ?                       0x5au */
2270 /*      ?                       0x5bu */
2271 /*      ?                       0x5cu */
2272 /*      ?                       0x5du */
2273 /*      ?                       0x5eu */
2274 /*      ?                       0x5fu */
2275 #define TV_HOST_READ_DATA       0x60u
2276 #define TV_HOST_WRITE_DATA      0x61u
2277 #define TV_HOST_RD_WT_CNTL      0x62u
2278 /*      ?                       0x63u */
2279 /*      ?                       0x64u */
2280 /*      ?                       0x65u */
2281 /*      ?                       0x66u */
2282 /*      ?                       0x67u */
2283 /*      ?                       0x68u */
2284 /*      ?                       0x69u */
2285 /*      ?                       0x6au */
2286 /*      ?                       0x6bu */
2287 /*      ?                       0x6cu */
2288 /*      ?                       0x6du */
2289 /*      ?                       0x6eu */
2290 /*      ?                       0x6fu */
2291 #define TV_VSCALER_CNTL         0x70u
2292 #define TV_TIMING_CNTL          0x71u
2293 #define TV_GAMMA_CNTL           0x72u
2294 #define TV_Y_FALL_CNTL          0x73u
2295 #define TV_Y_RISE_CNTL          0x74u
2296 #define TV_Y_SAW_TOOTH_CNTL     0x75u
2297 /*      ?                       0x76u */
2298 /*      ?                       0x77u */
2299 /*      ?                       0x78u */
2300 /*      ?                       0x79u */
2301 /*      ?                       0x7au */
2302 /*      ?                       0x7bu */
2303 /*      ?                       0x7cu */
2304 /*      ?                       0x7du */
2305 /*      ?                       0x7eu */
2306 /*      ?                       0x7fu */
2307 #define TV_MODULATOR_CNTL1      0x80u
2308 #define TV_MODULATOR_CNTL2      0x81u
2309 /*      ?                       0x82u */
2310 /*      ?                       0x83u */
2311 /*      ?                       0x84u */
2312 /*      ?                       0x85u */
2313 /*      ?                       0x86u */
2314 /*      ?                       0x87u */
2315 /*      ?                       0x88u */
2316 /*      ?                       0x89u */
2317 /*      ?                       0x8au */
2318 /*      ?                       0x8bu */
2319 /*      ?                       0x8cu */
2320 /*      ?                       0x8du */
2321 /*      ?                       0x8eu */
2322 /*      ?                       0x8fu */
2323 #define TV_PRE_DAC_MUX_CNTL     0x90u
2324 /*      ?                       0x91u */
2325 /*      ?                       0x92u */
2326 /*      ?                       0x93u */
2327 /*      ?                       0x94u */
2328 /*      ?                       0x95u */
2329 /*      ?                       0x96u */
2330 /*      ?                       0x97u */
2331 /*      ?                       0x98u */
2332 /*      ?                       0x99u */
2333 /*      ?                       0x9au */
2334 /*      ?                       0x9bu */
2335 /*      ?                       0x9cu */
2336 /*      ?                       0x9du */
2337 /*      ?                       0x9eu */
2338 /*      ?                       0x9fu */
2339 #define TV_DAC_CNTL             0xa0u
2340 /*      ?                       0xa1u */
2341 /*      ?                       0xa2u */
2342 /*      ?                       0xa3u */
2343 /*      ?                       0xa4u */
2344 /*      ?                       0xa5u */
2345 /*      ?                       0xa6u */
2346 /*      ?                       0xa7u */
2347 /*      ?                       0xa8u */
2348 /*      ?                       0xa9u */
2349 /*      ?                       0xaau */
2350 /*      ?                       0xabu */
2351 /*      ?                       0xacu */
2352 /*      ?                       0xadu */
2353 /*      ?                       0xaeu */
2354 /*      ?                       0xafu */
2355 #define TV_CRC_CNTL             0xb0u
2356 #define TV_VIDEO_PORT_SIG       0xb1u
2357 /*      ?                       0xb2u */
2358 /*      ?                       0xb3u */
2359 /*      ?                       0xb4u */
2360 /*      ?                       0xb5u */
2361 /*      ?                       0xb6u */
2362 /*      ?                       0xb7u */
2363 #define TV_VBI_CC_CNTL          0xb8u
2364 #define TV_VBI_EDS_CNTL         0xb9u
2365 #define TV_VBI_20BIT_CNTL       0xbau
2366 /*      ?                       0xbbu */
2367 /*      ?                       0xbcu */
2368 #define TV_VBI_DTO_CNTL         0xbdu
2369 #define TV_VBI_LEVEL_CNTL       0xbeu
2370 /*      ?                       0xbfu */
2371 #define TV_UV_ADR               0xc0u
2372 #define TV_FIFO_TEST_CNTL       0xc1u
2373 /*      ?                       0xc2u */
2374 /*      ?                       0xc3u */
2375 /*      ?                       0xc4u */
2376 /*      ?                       0xc5u */
2377 /*      ?                       0xc6u */
2378 /*      ?                       0xc7u */
2379 /*      ?                       0xc8u */
2380 /*      ?                       0xc9u */
2381 /*      ?                       0xcau */
2382 /*      ?                       0xcbu */
2383 /*      ?                       0xccu */
2384 /*      ?                       0xcdu */
2385 /*      ?                       0xceu */
2386 /*      ?                       0xcfu */
2387 /*      ?                       0xd0u */
2388 /*      ?                       0xd1u */
2389 /*      ?                       0xd2u */
2390 /*      ?                       0xd3u */
2391 /*      ?                       0xd4u */
2392 /*      ?                       0xd5u */
2393 /*      ?                       0xd6u */
2394 /*      ?                       0xd7u */
2395 /*      ?                       0xd8u */
2396 /*      ?                       0xd9u */
2397 /*      ?                       0xdau */
2398 /*      ?                       0xdbu */
2399 /*      ?                       0xdcu */
2400 /*      ?                       0xddu */
2401 /*      ?                       0xdeu */
2402 /*      ?                       0xdfu */
2403 /*      ?                       0xe0u */
2404 /*      ?                       0xe1u */
2405 /*      ?                       0xe2u */
2406 /*      ?                       0xe3u */
2407 /*      ?                       0xe4u */
2408 /*      ?                       0xe5u */
2409 /*      ?                       0xe6u */
2410 /*      ?                       0xe7u */
2411 /*      ?                       0xe8u */
2412 /*      ?                       0xe9u */
2413 /*      ?                       0xeau */
2414 /*      ?                       0xebu */
2415 /*      ?                       0xecu */
2416 /*      ?                       0xedu */
2417 /*      ?                       0xeeu */
2418 /*      ?                       0xefu */
2419 /*      ?                       0xf0u */
2420 /*      ?                       0xf1u */
2421 /*      ?                       0xf2u */
2422 /*      ?                       0xf3u */
2423 /*      ?                       0xf4u */
2424 /*      ?                       0xf5u */
2425 /*      ?                       0xf6u */
2426 /*      ?                       0xf7u */
2427 /*      ?                       0xf8u */
2428 /*      ?                       0xf9u */
2429 /*      ?                       0xfau */
2430 /*      ?                       0xfbu */
2431 /*      ?                       0xfcu */
2432 /*      ?                       0xfdu */
2433 /*      ?                       0xfeu */
2434 /*      ?                       0xffu */
2435
2436 /* Miscellaneous */
2437
2438 /* Current X, Y & Dest X, Y mask */
2439 #define COORD_MASK      0x07ffu
2440
2441 /* Pixel widths */
2442 #define PIX_WIDTH_1BPP                  0x00u
2443 #define PIX_WIDTH_4BPP                  0x01u   /* CRTC2: 8bpp */
2444 #define PIX_WIDTH_8BPP                  0x02u   /* CRTC2: Undefined */
2445 #define PIX_WIDTH_15BPP                 0x03u
2446 #define PIX_WIDTH_16BPP                 0x04u
2447 #define PIX_WIDTH_24BPP                 0x05u
2448 #define PIX_WIDTH_32BPP                 0x06u
2449 #define PIX_WIDTH_YUV422                0x07u   /* CRTC2 only */
2450
2451 /* Source definitions */
2452 #define SRC_BKGD                        0x00u
2453 #define SRC_FRGD                        0x01u
2454 #define SRC_HOST                        0x02u
2455 #define SRC_BLIT                        0x03u
2456 #define SRC_PATTERN                     0x04u
2457 #define SRC_SCALER_3D                   0x05u
2458 /*      ?                               0x06u */
2459 /*      ?                               0x07u */
2460
2461 /* The Mixes */
2462 #define MIX_MASK                        0x001fu
2463
2464 #define MIX_NOT_DST                     0x0000u
2465 #define MIX_0                           0x0001u
2466 #define MIX_1                           0x0002u
2467 #define MIX_DST                         0x0003u
2468 #define MIX_NOT_SRC                     0x0004u
2469 #define MIX_XOR                         0x0005u
2470 #define MIX_XNOR                        0x0006u
2471 #define MIX_SRC                         0x0007u
2472 #define MIX_NAND                        0x0008u
2473 #define MIX_NOT_SRC_OR_DST              0x0009u
2474 #define MIX_SRC_OR_NOT_DST              0x000au
2475 #define MIX_OR                          0x000bu
2476 #define MIX_AND                         0x000cu
2477 #define MIX_SRC_AND_NOT_DST             0x000du
2478 #define MIX_NOT_SRC_AND_DST             0x000eu
2479 #define MIX_NOR                         0x000fu
2480
2481 #define MIX_MIN                         0x0010u
2482 #define MIX_DST_MINUS_SRC               0x0011u
2483 #define MIX_SRC_MINUS_DST               0x0012u
2484 #define MIX_PLUS                        0x0013u
2485 #define MIX_MAX                         0x0014u
2486 #define MIX_HALF__DST_MINUS_SRC         0x0015u
2487 #define MIX_HALF__SRC_MINUS_DST         0x0016u
2488 #define MIX_AVERAGE                     0x0017u
2489 #define MIX_DST_MINUS_SRC_SAT           0x0018u
2490 #define MIX_SRC_MINUS_DST_SAT           0x001au
2491 #define MIX_HALF__DST_MINUS_SRC_SAT     0x001cu
2492 #define MIX_HALF__SRC_MINUS_DST_SAT     0x001eu
2493 #define MIX_AVERAGE_SAT                 0x001fu
2494 #define MIX_FN_PAINT                    MIX_SRC
2495
2496
2497 #endif /* MPLAYER_MACH64_H */