cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #if HAVE_MALLOC_H
   8 #include <malloc.h>
   9 #endif
  10 #include <stdlib.h>
  11
  12 #if ARCH_X86
  13
  14 #include <stdio.h>
  15 #include <string.h>
  16
  17 #if defined (__NetBSD__) || defined(__OpenBSD__)
  18 #include <sys/param.h>
  19 #include <sys/sysctl.h>
  20 #include <machine/cpu.h>
  21 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
  22 #include <sys/types.h>
  23 #include <sys/sysctl.h>
  24 #elif defined(__linux__)
  25 #include <signal.h>
  26 #elif defined(__MINGW32__) || defined(__CYGWIN__)
  27 #include <windows.h>
  28 #elif defined(__OS2__)
  29 #define INCL_DOS
  30 #include <os2.h>
  31 #elif defined(__AMIGAOS4__)
  32 #include <proto/exec.h>
  33 #endif
  34
  35 /* Thanks to the FreeBSD project for some of this cpuid code, and
  36  * help understanding how to use it.  Thanks to the Mesa
  37  * team for SSE support detection and more cpu detect code.
  38  */
  39
  40 /* I believe this code works.  However, it has only been used on a PII and PIII */
  41
  42 static void check_os_katmai_support( void );
  43
  44 // return TRUE if cpuid supported
  45 static int has_cpuid(void)
  46 {
  47         long a, c;
  48
  49 // code from libavcodec:
  50 #if ARCH_X86_64
  51 #define PUSHF "pushfq\n\t"
  52 #define POPF "popfq\n\t"
  53 #else
  54 #define PUSHF "pushfl\n\t"
  55 #define POPF "popfl\n\t"
  56 #endif
  57     __asm__ volatile (
  58                           /* See if CPUID instruction is supported ... */
  59                           /* ... Get copies of EFLAGS into eax and ecx */
  60                           PUSHF
  61                           "pop %0\n\t"
  62                           "mov %0, %1\n\t"
  63
  64                           /* ... Toggle the ID bit in one copy and store */
  65                           /*     to the EFLAGS reg */
  66                           "xor $0x200000, %0\n\t"
  67                           "push %0\n\t"
  68                           POPF
  69
  70                           /* ... Get the (hopefully modified) EFLAGS */
  71                           PUSHF
  72                           "pop %0\n\t"
  73                           : "=a" (a), "=c" (c)
  74                           :
  75                           : "cc"
  76                           );
  77 #undef PUSHF
  78 #undef POPF
  79
  80         return a != c;
  81 }
  82
  83 static void
  84 do_cpuid(unsigned int ax, unsigned int *p)
  85 {
  86 #if 0
  87         __asm__ volatile(
  88         "cpuid;"
  89         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  90         :  "0" (ax)
  91         );
  92 #else
  93 // code from libavcodec:
  94     __asm__ volatile
  95         ("mov %%"REG_b", %%"REG_S"\n\t"
  96          "cpuid\n\t"
  97          "xchg %%"REG_b", %%"REG_S
  98          : "=a" (p[0]), "=S" (p[1]),
  99            "=c" (p[2]), "=d" (p[3])
 100          : "0" (ax));
 101 #endif
 102
 103 }
 104
 105 void GetCpuCaps( CpuCaps *caps)
 106 {
 107         unsigned int regs[4];
 108         unsigned int regs2[4];
 109
 110         memset(caps, 0, sizeof(*caps));
 111         caps->isX86=1;
 112         caps->cl_size=32; /* default */
 113         if (!has_cpuid()) {
 114             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 115             return;
 116         }
 117         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 118         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 119                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 120         if (regs[0]>=0x00000001)
 121         {
 122                 char *tmpstr, *ptmpstr;
 123                 unsigned cl_size;
 124
 125                 do_cpuid(0x00000001, regs2);
 126
 127                 caps->cpuType=(regs2[0] >> 8)&0xf;
 128                 caps->cpuModel=(regs2[0] >> 4)&0xf;
 129
 130 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 131 // System Instructions, Table 3-2: Effective family computation, page 120.
 132                 if(caps->cpuType==0xf){
 133                     // use extended family (P4, IA64, K8)
 134                     caps->cpuType=0xf+((regs2[0]>>20)&255);
 135                 }
 136                 if(caps->cpuType==0xf || caps->cpuType==6)
 137                     caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 138
 139                 caps->cpuStepping=regs2[0] & 0xf;
 140
 141                 // general feature flags:
 142                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 143                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 144                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 145                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 146                 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >>  9; // 0x0000200
 147                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 148                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 149                 if(cl_size) caps->cl_size = cl_size;
 150
 151                 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 152                 while(*ptmpstr == ' ')        // strip leading spaces
 153                     ptmpstr++;
 154                 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr);
 155                 free(tmpstr);
 156                 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n",
 157                     caps->cpuType, caps->cpuModel, caps->cpuStepping);
 158
 159         }
 160         do_cpuid(0x80000000, regs);
 161         if (regs[0]>=0x80000001) {
 162                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 163                 do_cpuid(0x80000001, regs2);
 164                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 165                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 166                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 167                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 168                 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >>  6; // 0x0000040
 169         }
 170         if(regs[0]>=0x80000006)
 171         {
 172                 do_cpuid(0x80000006, regs2);
 173                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 174                 caps->cl_size  = regs2[2] & 0xFF;
 175         }
 176         mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 177 #if 0
 178         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 179                 gCpuCaps.hasMMX,
 180                 gCpuCaps.hasMMX2,
 181                 gCpuCaps.hasSSE,
 182                 gCpuCaps.hasSSE2,
 183                 gCpuCaps.has3DNow,
 184                 gCpuCaps.has3DNowExt );
 185 #endif
 186
 187                 /* FIXME: Does SSE2 need more OS support, too? */
 188 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \
 189   || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \
 190   || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \
 191   || defined(__OS2__)
 192                 if (caps->hasSSE)
 193                         check_os_katmai_support();
 194                 if (!caps->hasSSE)
 195                         caps->hasSSE2 = 0;
 196 #else
 197                 caps->hasSSE=0;
 198                 caps->hasSSE2 = 0;
 199 #endif
 200 //              caps->has3DNow=1;
 201 //              caps->hasMMX2 = 0;
 202 //              caps->hasMMX = 0;
 203
 204 #ifndef RUNTIME_CPUDETECT
 205 #if !HAVE_MMX
 206         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 207         caps->hasMMX=0;
 208 #endif
 209 #if !HAVE_MMX2
 210         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 211         caps->hasMMX2=0;
 212 #endif
 213 #if !HAVE_SSE
 214         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 215         caps->hasSSE=0;
 216 #endif
 217 #if !HAVE_SSE2
 218         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 219         caps->hasSSE2=0;
 220 #endif
 221 #if !HAVE_AMD3DNOW
 222         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 223         caps->has3DNow=0;
 224 #endif
 225 #if !HAVE_AMD3DNOWEXT
 226         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 227         caps->has3DNowExt=0;
 228 #endif
 229 #endif  // RUNTIME_CPUDETECT
 230 }
 231
 232 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 233         char vendor[13];
 234         char *retname;
 235         int i;
 236
 237         if (NULL==(retname=malloc(256))) {
 238                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 239                 exit(1);
 240         }
 241         retname[0] = '\0';
 242
 243         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 244
 245         do_cpuid(0x80000000,regs);
 246         if (regs[0] >= 0x80000004)
 247         {
 248                 // CPU has built-in namestring
 249                 for (i = 0x80000002; i <= 0x80000004; i++)
 250                 {
 251                         do_cpuid(i, regs);
 252                         strncat(retname, (char*)regs, 16);
 253                 }
 254         }
 255         return retname;
 256 }
 257
 258 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64
 259 static void sigill_handler_sse( int signal, struct sigcontext sc )
 260 {
 261    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 262
 263    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 264     * instructions are 3 bytes long.  We must increment the instruction
 265     * pointer manually to avoid repeated execution of the offending
 266     * instruction.
 267     *
 268     * If the SIGILL is caused by a divide-by-zero when unmasked
 269     * exceptions aren't supported, the SIMD FPU status and control
 270     * word will be restored at the end of the test, so we don't need
 271     * to worry about doing it here.  Besides, we may not be able to...
 272     */
 273    sc.eip += 3;
 274
 275    gCpuCaps.hasSSE=0;
 276 }
 277 #endif /* __linux__ && _POSIX_SOURCE */
 278
 279 #if defined(__MINGW32__) || defined(__CYGWIN__)
 280 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 281 {
 282    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 283       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 284       ep->ContextRecord->Eip +=3;
 285       gCpuCaps.hasSSE=0;
 286           return EXCEPTION_CONTINUE_EXECUTION;
 287    }
 288    return EXCEPTION_CONTINUE_SEARCH;
 289 }
 290 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
 291
 292 #ifdef __OS2__
 293 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD       p1,
 294                                    PEXCEPTIONREGISTRATIONRECORD p2,
 295                                    PCONTEXTRECORD               p3,
 296                                    PVOID                        p4 )
 297 {
 298    if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
 299       mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
 300
 301       p3->ctx_RegEip += 3;
 302       gCpuCaps.hasSSE = 0;
 303
 304       return XCPT_CONTINUE_EXECUTION;
 305    }
 306    return XCPT_CONTINUE_SEARCH;
 307 }
 308 #endif
 309
 310 /* If we're running on a processor that can do SSE, let's see if we
 311  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 312  * haven't been configured for a Pentium III but are running on one,
 313  * and RedHat patched 2.2 kernels that have broken exception handling
 314  * support for user space apps that do SSE.
 315  */
 316
 317 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
 318 #define SSE_SYSCTL_NAME "hw.instruction_sse"
 319 #elif defined(__APPLE__)
 320 #define SSE_SYSCTL_NAME "hw.optional.sse"
 321 #endif
 322
 323 static void check_os_katmai_support( void )
 324 {
 325 #if ARCH_X86_64
 326    gCpuCaps.hasSSE=1;
 327    gCpuCaps.hasSSE2=1;
 328 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 329    int has_sse=0, ret;
 330    size_t len=sizeof(has_sse);
 331
 332    ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 333    if (ret || !has_sse)
 334       gCpuCaps.hasSSE=0;
 335
 336 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 337 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 338    int has_sse, has_sse2, ret, mib[2];
 339    size_t varlen;
 340
 341    mib[0] = CTL_MACHDEP;
 342    mib[1] = CPU_SSE;
 343    varlen = sizeof(has_sse);
 344
 345    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 346    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 347    gCpuCaps.hasSSE = ret >= 0 && has_sse;
 348    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 349
 350    mib[1] = CPU_SSE2;
 351    varlen = sizeof(has_sse2);
 352    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 353    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 354    gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
 355    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
 356 #else
 357    gCpuCaps.hasSSE = 0;
 358    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 359 #endif
 360 #elif defined(__MINGW32__) || defined(__CYGWIN__)
 361    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 362    if ( gCpuCaps.hasSSE ) {
 363       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 364       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 365       __asm__ volatile ("xorps %xmm0, %xmm0");
 366       SetUnhandledExceptionFilter(exc_fil);
 367       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 368    }
 369 #elif defined(__OS2__)
 370    EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
 371    if ( gCpuCaps.hasSSE ) {
 372       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 373       DosSetExceptionHandler( &RegRec );
 374       __asm__ volatile ("xorps %xmm0, %xmm0");
 375       DosUnsetExceptionHandler( &RegRec );
 376       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 377    }
 378 #elif defined(__linux__)
 379 #if defined(_POSIX_SOURCE)
 380    struct sigaction saved_sigill;
 381
 382    /* Save the original signal handlers.
 383     */
 384    sigaction( SIGILL, NULL, &saved_sigill );
 385
 386    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 387
 388    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 389     * supports the extended FPU save and restore required for SSE.  If
 390     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 391     * doesn't support Streaming SIMD Exceptions, even if the processor
 392     * does.
 393     */
 394    if ( gCpuCaps.hasSSE ) {
 395       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 396
 397 //      __asm__ volatile ("xorps %%xmm0, %%xmm0");
 398       __asm__ volatile ("xorps %xmm0, %xmm0");
 399
 400       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 401    }
 402
 403    /* Restore the original signal handlers.
 404     */
 405    sigaction( SIGILL, &saved_sigill, NULL );
 406
 407    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 408     * safe to go ahead and hook out the SSE code throughout Mesa.
 409     */
 410    mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
 411 #else
 412    /* We can't use POSIX signal handling to test the availability of
 413     * SSE, so we disable it by default.
 414     */
 415    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 416    gCpuCaps.hasSSE=0;
 417 #endif /* _POSIX_SOURCE */
 418 #else
 419    /* Do nothing on other platforms for now.
 420     */
 421    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 422    gCpuCaps.hasSSE=0;
 423 #endif /* __linux__ */
 424 }
 425 #else /* ARCH_X86 */
 426
 427 #ifdef __APPLE__
 428 #include <sys/sysctl.h>
 429 #elif defined(__AMIGAOS4__)
 430 /* nothing */
 431 #else
 432 #include <signal.h>
 433 #include <setjmp.h>
 434
 435 static sigjmp_buf jmpbuf;
 436 static volatile sig_atomic_t canjump = 0;
 437
 438 static void sigill_handler (int sig)
 439 {
 440     if (!canjump) {
 441         signal (sig, SIG_DFL);
 442         raise (sig);
 443     }
 444
 445     canjump = 0;
 446     siglongjmp (jmpbuf, 1);
 447 }
 448 #endif /* __APPLE__ */
 449
 450 void GetCpuCaps( CpuCaps *caps)
 451 {
 452         caps->cpuType=0;
 453         caps->cpuModel=0;
 454         caps->cpuStepping=0;
 455         caps->hasMMX=0;
 456         caps->hasMMX2=0;
 457         caps->has3DNow=0;
 458         caps->has3DNowExt=0;
 459         caps->hasSSE=0;
 460         caps->hasSSE2=0;
 461         caps->hasSSSE3=0;
 462         caps->hasSSE4a=0;
 463         caps->isX86=0;
 464         caps->hasAltiVec = 0;
 465 #if HAVE_ALTIVEC
 466 #ifdef __APPLE__
 467 /*
 468   rip-off from ffmpeg altivec detection code.
 469   this code also appears on Apple's AltiVec pages.
 470  */
 471         {
 472                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 473                 int has_vu = 0;
 474                 size_t len = sizeof(has_vu);
 475                 int err;
 476
 477                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 478
 479                 if (err == 0)
 480                         if (has_vu != 0)
 481                                 caps->hasAltiVec = 1;
 482         }
 483 #elif defined(__AMIGAOS4__)
 484         ULONG result = 0;
 485
 486         GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 487         if (result == VECTORTYPE_ALTIVEC)
 488                 caps->hasAltiVec = 1;
 489 #else
 490 /* no Darwin, do it the brute-force way */
 491 /* this is borrowed from the libmpeg2 library */
 492         {
 493           signal (SIGILL, sigill_handler);
 494           if (sigsetjmp (jmpbuf, 1)) {
 495             signal (SIGILL, SIG_DFL);
 496           } else {
 497             canjump = 1;
 498
 499             __asm__ volatile ("mtspr 256, %0\n\t"
 500                           "vand %%v0, %%v0, %%v0"
 501                           :
 502                           : "r" (-1));
 503
 504             signal (SIGILL, SIG_DFL);
 505             caps->hasAltiVec = 1;
 506           }
 507         }
 508 #endif /* __APPLE__ */
 509         mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 510 #endif /* HAVE_ALTIVEC */
 511
 512 if (ARCH_IA64)
 513         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n");
 514
 515 if (ARCH_SPARC)
 516         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n");
 517
 518 if (ARCH_ARM)
 519         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n");
 520
 521 if (ARCH_PPC)
 522         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n");
 523
 524 if (ARCH_ALPHA)
 525         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n");
 526
 527 if (ARCH_SGI_MIPS)
 528         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: SGI MIPS\n");
 529
 530 if (ARCH_PA_RISC)
 531         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n");
 532
 533 if (ARCH_S390)
 534         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n");
 535
 536 if (ARCH_S390X)
 537         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n");
 538
 539 if (ARCH_VAX)
 540         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" );
 541
 542 if (ARCH_XTENSA)
 543         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" );
 544 }
 545 #endif /* !ARCH_X86 */